Claims
- 1. A method for forming a multilayered interconnecting metallurgical pad for making an electrical contact with an electronic component comprising the steps of:
- a) depositing a layer of chromium directly on said electronic component,
- b) depositing a layer of soluble noble metal on said layer of chromium,
- c) depositing a layer of nickel directly on said layer of soluble noble metal, and
- d) depositing a layer of noble or relatively noble metal directly on said layer of nickel, thereby forming said multilayered interconnecting metallurgical pad.
- 2. The method of claim 1, wherein said soluble noble metal layer is selected from the group consisting of platinum, palladium, rhodium and mixtures thereof.
- 3. The method of claim 1, wherein said noble or relatively noble metal is selected from the group consisting of gold, platinum, palladium, rhodium, tin and mixtures thereof.
- 4. The method of claim 1, wherein said electronic component is a semiconductor chip.
- 5. The method of claim 1, wherein said electronic component is a ceramic substrate.
- 6. The method of claim 1, wherein at least a portion of said noble or relatively noble metal layer is in contact with a solder material.
- 7. The method of claim 1, wherein at least a portion of said pad makes an electrical contact with at least a portion of a connecting device.
- 8. The method of claim 7, wherein said connecting device is selected from a group comprising a wire, a base metallurgical pad, a pin, a solder ball or a connector.
- 9. The method of claim 8, wherein said base metallurgical pad has at least one metal, and where said metal is selected from the group consisting of chromium, cobalt, copper, hafnium, molybdenum nickel, niobium, tantalum, titanium, zirconium, noble metals and mixtures thereof.
- 10. The method of claim 1, wherein the process for the formation of said pad is selected from a group comprising, chemical vapor deposition, etching, evaporation or sputter deposition.
- 11. The method of claim 1, wherein said chromium layer has a thickness from 0.01 to 0.3 micron, said soluble noble metal layer has a thickness from 0.02 to 5.0 micron, said nickel layer has a thickness from 1.0 to 5.0 micron, and said noble or relatively noble metal layer has a thickness from 0.1 to 20.0 micron.
- 12. The method of claim 1, wherein said electronic component has at least one via.
- 13. The method of claim 12, wherein at least a portion of said layer of chromium makes electrical contact with at least a portion of at least one of said via.
- 14. A method for forming a multilayered interconnecting metallurgical pad for making an electrical contact with an electronic component comprising the steps of:
- (a) depositing a layer of chromium directly on said electronic component,
- b) depositing a layer of nickel directly on said layer of chromium, and
- c) depositing a layer of noble or relatively noble metal directly on said layer of nickel, thereby forming said multilayered interconnecting metallurgical pad.
- 15. The method of claim 14, wherein said noble or relatively noble metal is selected from the group consisting of gold, platinum, palladium, rhodium, tin and mixtures thereof.
- 16. The method of claim 14, wherein said electronic component is a semiconductor chip.
- 17. The method of claim 14, wherein said electronic component is a ceramic substrate.
- 18. The method of claim 14, wherein at least a portion of said noble or relatively noble metal layer is in contact with a solder material.
- 19. The method of claim 14, wherein at least a portion of said pad makes an electrical contact with at least a portion of a connecting device.
- 20. The method of claim 19, wherein said connecting device is selected from a group comprising a wire, a base metallurgical pad, a pin, a solder ball or a connector.
- 21. The method of claim 20, wherein said base metallurgical pad has at least one metal, and where said metal is selected from the group consisting of chromium, cobalt, copper, hafnium, molybdenum nickel, niobium, tantalum, titanium, zirconium, noble metals and mixtures thereof.
- 22. The method of claim 14, wherein the process for the formation of said pad is selected from a group comprising, chemical vapor deposition, etching, evaporation or sputter deposition.
- 23. The method of claim 14, wherein said chromium layer has a thickness from 0.01 to 0.3 micron, said nickel layer has a thickness from 1.0 to 5.0 micron, and said noble or relatively noble metal layer has a thickness from 0.1 to 20.0 micron.
- 24. The method of claim 14, wherein said electronic component has at least one via.
- 25. The method of claim 24, wherein at least a portion of said layer of chromium makes electrical contact with at least a portion of at least one of said via.
Parent Case Info
This Patent Application is a Division of U.S. Pat. application Ser. No. 07/683,169, filed on Apr. 10, 1991, now U.S. Pat. No. 5,175,609.
US Referenced Citations (21)
Foreign Referenced Citations (2)
Number |
Date |
Country |
59-48941 |
Feb 1984 |
JPX |
59-32154 |
Mar 1984 |
JPX |
Non-Patent Literature Citations (1)
Entry |
"Backside Preparation and Metallization of Silicon Wafers for Die-Bonding," Research Disclosure, No. 267 (Jul. 1986). |
Divisions (1)
|
Number |
Date |
Country |
Parent |
683169 |
Apr 1991 |
|