Patent Application
20230262906
Plated through holes (PTHs) through the various layers of the substrate provide electrical communication between different layers to improve effective electrical circuit occupancy.
Plated through holes are provide for ground, signal transmission and power supply. Generally speaking, crosstalk among signal PTH would be a major signal integrity problem, especially for high performance DDR (Double Data Rate SDRAM) interface and PCIe (Peripheral Component Interconnect express) signals. Minimizing mutual-inductance, and hence the crosstalk, is needed to achieve the next generation DDR performance and PCIe performance.
Conventional PTH requires one PTH for signal/power and one PTH for ground (or shared ground PTH). Physically, separate signal/power PTH and ground PTH would take a lot of routing space and electrically, it may create high mutual-inductance. The consequence is high crosstalk among those signals.
Broadly speaking, the present invention fills these needs by providing a substrate, a chip, a circuit package and a process of fabricating a substrate in order to achieve high performance and high routing density for packages such as CPU/AI chips. It should be appreciated that the present invention can be implemented in numerous ways, including as a method, a system, or a device. Several inventive embodiments of the present invention are described below.
In accordance with aspects of the invention, a multi-conductor through hole structure can include one or more through holes disposed in a first insulating region. A first conductor region can be disposed about a wall of the one or more through holes. A second conductor region can be disposed in the one or more through holes. A second insulating region can be disposed between an inside all of the first conductor region and a wall of the second conductor region.
In accordance with one aspect of the invention, a substrate is provided. The substrate is provided between an integrated circuit and a printed circuit board, and comprises a core insulating layer and a buildup insulating layer. The core insulating layer comprises first and second plated through holes extending through the core insulating layer. The buildup insulating layer is disposed over first and second surfaces of the core insulating layer. The first plated through hole is operable to provide ground through from the printed circuit board to the integrated circuit. The second plated through hole is operable to provide electrical communication carrying signals or power between the integrated circuit and the printed circuit board through the buildup insulating layers. The first plated through hole is formed in tubular, cylindrical, conical, rectangular or similar shape defined by an outer wall and an inner wall, and the second plated through hole is formed in the inner wall of the first plated through hole and is insulated from the first plated through hole.
Alternatively, the first plated through hole and the second plated through hole are arranged coaxially.
Alternatively, an insulative material is disposed between the second plated through hole and the inner wall of the first plated through hole.
Alternatively, the insulative material is arranged coaxial between the first plated through hole and the second plated through hole.
Alternatively, the insulative material and the first plated through hole are both formed to be cylindrical.
Alternatively, a first conductive material layer can be disposed between the buildup insulating layer and the core insulating layer and electrically coupled to first plated through holes.
Alternatively, the substrate further comprises a second conductive material layer disposed between the buildup insulating layer and the core insulating layer, for providing electrical communication carrying signals or power. The first plated through hole on the first or second surface of the core insulating layer can be discontinuous at a gap area, and the second conductive material layer disposed between the buildup insulating layer and the core insulating layer can be electrically coupled to the second plated through hole through the gap area.
Alternatively, the substrate further comprises a third conductive material layer disposed on the surface of the buildup insulating layer opposite to the core insulating layer. A third plated through hole extends through the buildup insulating layer and has electrical communication with the third conductive material layer, for providing electrical communication carrying signals or power.
In accordance with another aspect of the invention, a chip is provided. The chip comprises an integrated circuit, and the substrate according to anyone of last aspect. The substrate disposed between the integrated circuit and a printed circuit board.
In accordance with another aspect of the invention, a circuit package is provided. The circuit package comprises the chip according to the last aspect, and a printed circuit board. The chip is disposed on the printed circuit board.
In accordance with aspects of the invention, a method of fabricating a multi-conductor through hole structure can include forming a through hole through a first insulating layer. A first conductor layer can be formed in the first though hole. A second insulating layer can be formed in the first conductor layer, and a second conductor layer can be formed in the second insulating layer.
In accordance with another aspect of the invention, a process of fabricating substrate is provided. The process comprises: forming a first through hole through a core insulating layer; plating a conductive material in the first through hole; forming a second through hole through the core insulating layer in the conductive material, with the portion between the first and the second through hole as a first plated through hole for providing ground; forming an insulative material in the first plated through hole; forming, through the core insulating layer in the insulative material, a second plated through hole for providing electrical communication carrying signals or power.
In accordance with another aspect of the invention, a process of fabricating substrate is provided. The process comprises: forming a first through hole through a core insulating layer, and forming a pre-made piece by forming in an insulative material a second plated through hole for providing electrical communication carrying signals or power; plating a conductive material in the first through hole; forming a second through hole through the core insulating layer in the conductive material, with the portion between the first and the second through hole as a first plated through hole for providing ground; fitting the pre-made piece into the second through hole through the core insulating layer.
In accordance with another aspect of the invention, a process of fabricating substrate is provided. The process comprises: forming a first through hole through a core insulating layer, and forming a pre-made piece by: forming in an insulative material a second plated through hole for providing electrical communication carrying signals or power, and plating a conductive material on the outer wall of an insulative material; fitting the pre-made piece into the first through hole through the core insulating layer, to form a first plated through hole defined by the outer wall of an insulative material and the first through hole for providing ground.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
The following embodiments describe an apparatus and method for minimizing differential loss and cross-talk in a multilayer substrate. It will be obvious, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
Referring further to
Specifically, the DC power supply provides through conducting layer 121, 131 supply a voltage to the integrated circuit 103 to activate a device on the integrated circuit 103 through certain power path. The electric flow generated by the activated device on the integrated circuit 103 is grounded through a return path 111.
Physically, the structure of signal plated through hole 120 or power plated through hole 130 and ground plated through hole 110 is taking a lot of routing space and electrically, plated through holes are creating high mutual-inductance and high crosstalk among those signals.
In one implementation, a substrate 200 of the embodiment can be provided between an integrated circuit (not shown) and a printed circuit board (not shown). The substrate 200 comprises a core insulating layer 201 and a buildup insulating layer 202. A buildup insulating layer 202 herein may be one or plurality of buildup insulating layers. One or more multi-conductor through hole structures 210-245 can be formed through the core insulating layer 201.
The multi-conductor through hole structures 210-245 can include a through hole 210, 215, a ground plated region 212 disposed in the through hole 210, 215, a power/signal region 220,230 disposed in the through hole 210, 215, and an insulative material region 240, 245 disposed between the ground plated region 212 and the power/signal region 220, 230. The ground plated region 212 and the power/signal region 220, 230 can extend through the core insulating layer 201. A buildup insulating layer 202 can be disposed over first and second surfaces of the core insulating layer 201. The ground plated region 212 can further be disposed on one or more portions of the surfaces of the core insulating layer 201.
Furthermore, the ground plated region 212 is operable to provide a ground through from the printed circuit board to the integrated circuit, and the power/signal region 220,230 is operable to provide electrical communication carrying signals or power between the integrated circuit and the printed circuit board through the buildup insulating layers 202. It should be noted that one or more portions of the ground plated region 212 disposed on the surface of a core insulating layer 201 may be of any shape and may be different from one another.
Furthermore, the ground plated region 212 can have tubular shape defined by an outer wall and an inner wall, wherein the outer wall of the ground plated region 212 is coincident with the wall of the through hole 210, 215. The insulative material region 240, 245 similarly can have a tubular shape defined by an outer wall and an inner wall, wherein the outer wall of the insulative material region 240, 245 is coincident with the inner wall of the ground plated region 212. The power/signal region 220,230 can be disposed inside the inner wall of the insulative material region 240, 245. Therefore, the power/signal region 220, 230 can be disposed within the ground plated region 212, and insulated from each other by the insulative material region 240, 245.
In the embodiment of the present invention, a short distance between the ground plated region 212 and the power/signal region 220, 230 is realized compared to separate plated through hole structures, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface, the coaxial structure of the ground plater region 212 and power/signal region 220, 230 significantly reduces the area needed for ground and signal/power routing.
For the purpose of clarity, only two types of plated through hole structures are shown for ground and power/signal, respectively. In addition, the relative thicknesses of the various layers are not drawn to scale. The buildup insulating layer 202 consists of insulating layers with conductive layers in between. In one embodiment, the substrate 200 consists of four conducting layers and three insulating layers as buildup insulating layers 202 and one core insulating layer 201. Between the first insulating layer and the second insulating layer as buildup insulating layers 202 is a conductive layer. A core insulating layer 201 may be used to separate the buildup insulating layer 202 on one side of the core insulating layer from the buildup insulating layer 202 on the other side. In one embodiment, the thickness for the core insulating layer 201 is of certain value such 800 μm or so. For each buildup insulating layer 202 is of certain value such as 35 μm or so. The exemplary thicknesses of the core insulating layer 201 and the buildup layer 202 are for illustrative purposes and are not meant to be limiting.
The through hole 210 and the power/signal region 220,230 are arranged coaxially within a certain tolerance. In other word, extremely low self-induct among the PDN path is created. As self-inductance cross plated through holes is a major contribution of the total PDN self-inductance, coaxial PTH structure significantly decreases the self-inductance.
In some embodiments, the insulative material region 240, 245, having an inner wall and outer wall, is provided around the conductive material which forms in the power/signal region 220, 230, the inner wall of the insulative material being in contact with the conductive material of the power/signal region 220, 230, and the outer wall of the insulative material regions 240, 245 being in contact with the conductive material from the ground plated region 212. In other words, the conductive material which forms in the power/signal region 220, 230 has an outer wall that contacts the insulative material region 240, 245, and the conductive material from the ground plated region 212 has an inner wall that contacts the insulative material region 240, 245. Furthermore, the core insulating layer 201 has a wall that contacts the conductive material of the ground plated region 212.
For the fabrication process of the multi-conductor through hole structures 210-245, a number of steps can be taken as follows: forming a first through hole 210, 215 through a core insulating layer 201, plating a conductive material 212 in the first through hole, forming an insulative material 240, 245 within the walls of the conductive plating material 212, forming a second through hole through the insulative material 240, 245, and forming a conductive material 220, 230 in the second through hole.
In another fabrication process of the multi-conductor through hole structures 210-245, a number of steps can be taken as follows: forming a first through hole 210, 215 through a core insulating layer 201, plating a conductive material 212 in the first through hole, forming a layer or film of insulative material 240, 245 on the inner walls of the conductive plating material 212, forming a conductive material 220, 230 filling the space within the inner walls of the layers of insulative material 240, 245.
Alternatively, the multi-conductor through hole structure 210-245 may otherwise be formed by fitting, into a first through hole 210, 215 of the core insulating layer 201, a pre-made piece which has a conductive coating over an insulative material 240, 245 surrounding a conductive core 220, 230. When the pre-made piece is being processed into a tubular shape, the surface (that is, the outer wall of the insulative material 240 or the outer wall of the coating) of the pre-made piece is not necessarily formed coaxially with the conductive core 220, 230, in this way, a certain process tolerance is considered, enhancing the efficiency of the process. Similarly, multi-conductor through hole structure 210-245 may otherwise be formed by fitting, into a first plated through hole of the core insulating layer, a pre-made piece which has a conductive coating over an insulative material 245.
The second conductive material 220, 230 can be disposed in a tubular through hole 210, 215. Specifically, the tubular through hole 210 is formed or defined by an inner wall belonging to the core insulating layer. The insulative material 240, 245 can be disposed between the outer wall of second conductive material 220, 230 and the inner wall of the first conductive material 212 disposed on the wall of the through hole 210, 215. In one example, the insulative material 240, 245 is arranged coaxial with the first conductive material and the second conductive material 220, 230. In one example, the insulative material 240, 245 and the through hole 210, 215 are both formed to be cylindrical.
In some embodiments, in the fabrication process of the second conductive material 220, 230, a number of steps can be taken by: forming an insulative material 240, 245 in the first plated through hole 210, 212, and forming, through the insulative material 240, 245, a second conductive material 220, 230 for providing electrical communication carrying signals or power.
Alternatively, the second conductive material 220,230 may otherwise be formed by forming a through hole in the pre-made piece which may consist of an insulative material 240, 245 or may include a conductive coating 212 over the outer wall of insulative piece. In the case of the pre-made piece consisting of an insulative material 240, 245, the pre-made piece is prepared for fitting into the through hole 210, 215 as above. In the case of the pre-made piece overcoated by a conductive material 212, the pre-made piece is prepared for fitting into the through hole 210, 215 as above. When the pre-made piece is being processed into a tubular shape, the inner wall the second conductive material 220, 230 is not necessarily formed coaxially with the surface of the pre-made piece in either case, in this way, a certain process tolerance is considered, enhancing the efficiency of the process.
Furthermore, a first conductive material layer 211 is disposed between the buildup insulating layer and the core insulating layer, for providing electrical communication of conductive materials between adjacent first plated through holes. a second conductive material layer 221, 231 is disposed between the buildup insulating layer and the core insulating layer, for providing electrical communication carrying signals or power. A third plated through hole 222, 232 extends through the buildup insulating layer and has electrical communication with the third conductive material layer, for providing electrical communication carrying signals or power.
Some embodiments of multi-conductor through hole structures on the surface of a core insulating layer will be described with reference to
Referring to
Referring further to
Furthermore, in either of embodiment of
Referring further to
Several embodiments of
In another embodiment of the present invention, A circuit package comprises the chip according to the embodiment of
S710: Forming a first through hole through a first insulating layer.
S720: Forming a first conductor layer in the first through hole.
S730: Forming a second a second insulating layer in the first conductor layer.
S740: Forming a second insulative layer in the first conductor layer.
In the embodiment of the present invention, the second insulative layer can have an inner wall and outer wall, with the inner wall of the second insulative layer being in contact with the second conductor layer and the outer wall of the second insulative layer being in contact with the first conductive layer. Accordingly, a short distance between the first conductor layer and second conductor layer is realized as compared to the structure of two separate plated through holes, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface, the coaxial structure of first plated through hole and the second conductive material significantly reduces the area needed for ground and signal/power routing.
S810: Forming a first through hole through a first insulating layer.
S820: Forming a first conductor layer on a wall of the first through hole.
S830: Forming a second insulating layer on an inside wall of the first conductor layer.
S840 Forming a second conductor layer within an inside wall of the second insulating layer.
In the embodiment of the present invention, the second insulative layer can have an inner wall and outer wall, with the inner wall of the second insulative layer being in contact with the second conductor layer and the outer wall of the second insulative layer being in contact with the first conductive layer. Accordingly, a short distance between the first conductor layer and second conductor layer is realized as compared to the structure of two separate plated through holes, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface, the coaxial structure of first conductor layer and the second conductor layer significantly reduces the area needed for ground and signal/power routing.
S910: Forming a first through hole through a first insulating layer.
S920: Forming a first conductor layer on a wall of the first through hole.
S930: Forming a second insulating layer within an inside wall of the first conductor layer.
S940: Forming a second through hole through the second insulating layer.
S940 Forming a second conductor layer within the second through hole.
In the embodiment of the present invention, the second insulative layer can have an inner wall and outer wall, with the inner wall of the second insulative layer being in contact with the second conductor layer and the outer wall of the second insulative layer being in contact with the first conductive layer. Accordingly, a short distance between the first conductor layer and second conductor layer is realized as compared to the structure of two separate plated through holes, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface, the coaxial structure of first conductor layer and the second conductor layer significantly reduces the area needed for ground and signal/power routing.
S1010: Forming a first through hole through a first insulating layer.
S1020: Forming a first conductor layer on the wall of the first through hole.
S1030: Forming a pre-made piece including a second insulating layer disposed about a second conductor layer.
S1040: Fitting the pre-made piece within the inside wall of the first conductor layer.
Accordingly, a short distance between the first conductor layer and the second conductor layer is realized as compared to the structure of two separate plated through holes, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface the coaxial structure of the first conductive layer and second conductive layer significantly reduces the area needed for ground and signal/power routing.
S1110: Forming a first through hole through a first insulating layer.
S1120: forming a pre-made piece including a first conductor disposed about an outside wall of a second insulating layer and a second conductor layer disposed within an inside wall of the second insulating layer.
S1130: Fitting the pre-made piece into the first through hole.
Accordingly, a short distance between the first and second conductive material is realized compared to separate structures of two plated through holes, thus low PDN (Power Distribution Network) impedance is realized to maintain power integrity in the circuit. Furthermore, for high bandwidth chips, especially for DDR interface, the coaxial structure of the first and second conductor layers significantly reduces the area needed for signal/power routing.
It should be noted that the embodiment of
Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
