Patent Application
20240153819
This application is based on and claims the benefit of priority from Chinese Patent Application No. 2022113899852, filed on 18 Nov. 2022, the entirety of which is incorporated by reference herein.
The disclosure relates to the technical field of semiconductor manufacturing, and is particularly a substrate manufacturing method, an embedded substrate and a semiconductor.
With the continuous development of electronic industry, the multifunction and miniaturization of electronic products have become development trends. In the field of packaging substrates, embedding devices into a substrate may be conductive to achieving requirements for high integration, multifunction and miniaturization of the electronic products. In the existing technology, for manufacturing a substrate with an embedded device, a cavity is generally manufactured in the substrate first, and then a device to be embedded is adhered in the cavity, and then a dielectric material is laminated to fill the cavity and cover the embedded device. However, in this manufacturing method, the cavity needs to be manufactured first, with a long process flow and a high cost, and it is easy to cause a warping problem during substrate manufacturing. Therefore, there is an urgent need for a new substrate manufacturing method.
The disclosure aims to solve at least one of the technical problems in the existing technology to some extent.
Therefore, one object of an embodiment of the disclosure is to provide a substrate manufacturing method, an embedded substrate and a semiconductor, and the method can reduce substrate warping while completing device embedding.
In order to achieve the object above, a technical solution adopted in an embodiment of the disclosure includes a substrate manufacturing method including: manufacturing a first semi-finished substrate, where the first semi-finished substrate includes a plurality of first circuit layers electrically connected with each other and at least one first dielectric layer; the first circuit layers and the first dielectric layer are arranged in a staggered and laminated manner; and a number a of the first circuit layers and a number b of the first dielectric layer satisfy: a=b+1, a≥2; arranging a viscous material layer on the first circuit layer to form a device adhering area, where a projection area of the viscous material layer in a direction perpendicular to the substrate is smaller than a projection area of a device in the direction perpendicular to the substrate; adhering an embedded device on the device adhering area, where a pin face of the embedded device faces away from the viscous material layer; laminating a second dielectric layer on the first circuit layer, where the second dielectric layer covers the viscous material layer and the embedded device; and manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, where the first conductive pillar extends through the second dielectric layer and is configured for connecting the second circuit layer with the first circuit layer, the second conductive pillar is configured for connecting the embedded device with the second circuit layer.
In addition, the substrate manufacturing method according to the above embodiment in the disclosure may also have the following additional technical features.
Further, in an embodiment of the disclosure, the arranging a viscous material layer on the first circuit layer to form a device adhering area includes: arranging a photo-imagable dielectric (PID) material layer on the first circuit layer or arranging a DAF material layer on the first circuit layer to form the device adhering area.
Further, in an embodiment of the disclosure, the arranging a PID material layer on the first circuit layer includes: arranging the PID material layer on the first circuit layer, where the PID material layer covers the first circuit layer; and performing a photoetching process on the PID material layer to form the device adhering area.
Further, in an embodiment of the disclosure, the manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer includes: drilling the second dielectric layer to form a first through hole and a second through hole, so that the first circuit layer is exposed and a pin of the embedded device is exposed; performing hole filling and electroplating in the first through hole and the second through hole to obtain the first conductive pillar, the second conductive pillar and a second seed layer, where the second seed layer is formed on the second dielectric layer; and performing a photoetching process on the second seed layer to obtain the second circuit layer.
Further, in an embodiment of the disclosure, the arranging a PID material layer on the first circuit layer or arranging a DAF material layer on the first circuit layer includes: laminating the PID material layer on the first circuit layer or coating the DAF material at a preset position of the first circuit layer.
Further, in an embodiment of the disclosure, the manufacturing a first semi-finished substrate includes: laminating an Nth dielectric layer on a surface of an Nth metal layer, and arranging an N+1th metal layer on the Nth dielectric layer; and performing a photoetching process on the Nth metal layer, and performing a photoetching process on the N+1th metal layer to form N+1 first circuit layers, where the N+1 first circuit layers are electrically connected with each other through conductive pillars, where N≥1.
In another aspect, an embodiment of the disclosure further provides an embedded substrate, which is prepared by the substrate manufacturing method according to any one of the embodiments above, and includes: the semi-finished substrate, where the semi-finished substrate includes the plurality of first circuit layers electrically connected with each other and the at least one first dielectric layer; the first circuit layers and the first dielectric layer are arranged in the staggered and laminated manner; and the number a of the first circuit layers and the number b of the first dielectric layers satisfy: a=b+1, a≥2; the viscous material layer arranged between the embedded device and the semi-finished substrate; the embedded device, where the pin face of the embedded device is arranged to face away from the first circuit layer of the semi-finished substrate; the second circuit layer connected with the embedded device and the first circuit layer of the semi-finished substrate; and the second dielectric layer arranged between the semi-finished substrate and the second circuit layer, and covering the embedded device.
Further, in an embodiment of the disclosure, the embedded device includes an active device, or a passive device.
Further, in an embodiment of the disclosure, the viscous material layer includes a PID material layer or a DAF material layer.
In addition, the disclosure further provides a semiconductor, which includes at least one embedded substrate according to any one of the embodiments above.
The advantages and beneficial effects of the disclosure will be given in part in the following description, and will become apparent in part from the following description, or will be learned through the practice of the disclosure.
According to the disclosure, the embedded device may be directly placed in the dielectric layer between the circuit layers, and it is unnecessary to manufacture the cavity to place the embedded device. Moreover, the semi-finished product before embedding the device in the disclosure has a symmetrical structure, so that the warping phenomenon in the manufacturing process can be reduced, and the product yield can be improved.
Embodiments of the disclosure are described in detail hereinafter with reference to the drawings to explain the principles and processes of a substrate manufacturing method, an embedded substrate, and a semiconductor in the embodiments of the disclosure.
With reference to
In S1, a first semi-finished substrate is manufactured, where the first semi-finished substrate includes a plurality of first circuit layers electrically connected with each other and at least one first dielectric layer; the first circuit layers and the first dielectric layer are arranged in a staggered and laminated manner; and a number a of the first circuit layers and a number b of the first dielectric layer satisfy: a=b+1, a≥2.
In this step, the semi-finished substrate may be manufactured in advance, and the semi-finished substrate may include two or more circuit layers and at least one dielectric layer. The first circuit layers and the first dielectric layer may be arranged in the staggered and laminated manner, and the number of the circuit layers is the number of the dielectric layers plus 1, which means that, in a direction perpendicular to the semi-finished substrate, no matter whether the number of the circuit layers in the semi-finished substrate is 2 or N, there is always a circuit layer located on a surface of the semi-finished substrate, and the dielectric layer is always arranged between two circuit layers. By arranging the semi-finished substrate with a symmetrical structure, the warping defect caused by a difference between copper residue rates on two surfaces in a subsequent laminating process can be avoided.
In S2, a viscous material layer is arranged on the first circuit layer to form a device adhering area, where a projection area of the viscous material layer in a direction perpendicular to the substrate is smaller than a projection area of a device in the direction perpendicular to the substrate.
In this step, because the circuit layers are always located on two surfaces of the semi-finished substrate in the direction perpendicular to the substrate, the viscous material layer may be arranged on the circuit layer on any surface, and the projection area of the viscous material layer in the direction perpendicular to the substrate is smaller than the projection area of the device in the direction perpendicular to the substrate, thus forming the device adhering area. In the case that the projection area of the viscous material layer is smaller than the projection area of the device, the viscous material layer may be avoided from overflowing to affect a subsequent process when the device is adhered. The device adhering area may be on any position of the first circuit layer. The viscous material may be configured for fixing an embedded device to avoid the device from shifting in the subsequent process.
In S3, an embedded device is adhered on the device adhering area; and a pin face of the embedded device is arranged to face away from the viscous material layer.
In this step, the embedded device may be adhered on the device adhering area, and the device may include an active or passive device, where the active device may include a chip, a transistor, and the like, and the passive chip may include a resistor, a capacitor, and the like. Because the device has the pin face and a packaging surface, the packaging surface and the pin face of the device are generally arranged opposite to each other, a pin of the device may face away from the first circuit layer during adhering, and the packaging surface is adhered to the viscous material layer. Taking the first circuit layer being upward as an example, the pin of the embedded device should also be upward during adhering.
In S4, a second dielectric layer is laminated on the first circuit layer; and the second dielectric layer covers the viscous material layer and the embedded device.
In this step, after the device is adhered, the second dielectric layer may be laminated on the first circuit layer, and the second dielectric layer may be a dielectric layer made of resin and other materials. The second dielectric layer should completely cover the first dielectric layer, the viscous material layer and the embedded device during laminating, so that a thickness of the second dielectric layer should be greater than a sum of thicknesses of the viscous material layer and the embedded device.
In S5, a first conductive pillar, a second conductive pillar and a second circuit layer are manufactured; the first conductive pillar extends through the second dielectric layer; the first conductive pillar is configured for connecting the second circuit layer and the first circuit layer; and the second conductive pillar is configured for connecting the embedded device with the second circuit layer.
In this step, after laminating the second dielectric layer, the first conductive pillar extending through the second dielectric layer, the second conductive pillar connecting the embedded device and the subsequent circuit layer, and the second circuit layer connecting the semi-finished substrate and the embedded device may be manufactured on the second dielectric layer. During manufacturing, laser drilling may be performed on the second dielectric layer first, then the first conductive pillar and the second conductive pillar are formed by electroplating, a metal layer with a thickness sufficient for manufacturing the second circuit layer is formed by electroplating continuously, and finally, the second circuit layer may be obtained by performing a photoetching process on the metal layer.
Further, the arranging a viscous material layer on the first circuit layer to form the device adhering area may include: arranging a PID material layer on the first circuit layer or arranging a DAF (Die Attach Film) material layer on the first circuit layer to form the device adhering area.
In an embodiment of the disclosure, the viscous material layer may be the PID material layer or the DAF material layer. The PID material layer and the DAF material layer are both a material layer with viscidity, which may be configured for fixing the embedded device to avoid the embedded device from shifting in the subsequent process to affect the product quality. Furthermore, in practical application, the PID material layer is often a thin film covering the whole first circuit layer, therefore when the PID material layer is arranged, it is also necessary to remove areas of the PID layer on the first circuit layer which are not for adhering the device.
Further, the arranging a PID material layer on the first circuit layer may include: arranging the PID material layer on the first circuit layer, where the PID material layer covers the first circuit layer; and performing a photoetching process on the PID material layer to form the device adhering area.
In an embodiment of the disclosure, because the PID material is a thin film sufficient to cover the whole first circuit layer, in order to avoid other areas on the first circuit layer from being electrically isolated by the thin film, it is necessary to remove the PID material layer in a non-device adhering area, and the remaining PID material may be removed by a photoetching process, leaving only the PID material layer in the device adhering area.
Further, the arranging a PID material layer on the first circuit layer or arranging a DAF material layer on the first circuit layer may include: laminating the PID material layer on the first circuit layer or coating the DAF material at a preset position of the first circuit layer.
In an embodiment of the disclosure, the PID material may be arranged on the first circuit layer by laminating, and the DAF material may be arranged at any position of the first circuit layer by coating, thus forming the device adhering area.
Further, the manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer may include:
Specifically, in an embodiment of the disclosure, the second dielectric layer may be drilled first to form a plurality of through holes in the second dielectric layer, the through holes may partially expose the first circuit layer and the pin of the embedded device, and then an electroplating process is performed based on the first circuit layer and the pin of the device. The first conductive pillar extending through the second dielectric layer and the second conductive pillar connecting the subsequent circuit layer and the embedded device are formed in the through holes respectively, then the electroplating is continued until the second seed layer with a thickness sufficient for manufacturing the circuit layer is formed on the second dielectric layer, and finally, the photoetching process is performed on the second seed layer to form the final second circuit layer.
Further, the manufacturing a first semi-finished substrate may include:
In an embodiment of the disclosure, taking the first semi-finished substrate composed of three first circuit layers and two dielectric layers as an example, a first dielectric layer is laminated on a surface of a first metal layer first, a second metal layer is arranged on the first dielectric layer, and then a conductive pillar is arranged to electrically connect the first metal layer with the second metal layer. Subsequently, the first metal layer and the second metal layer are photoetched to form two first circuit layers. Subsequently, a second dielectric layer is laminated on the first circuit layer, a third metal layer is arranged on the second dielectric layer, then a conductive pillar is arranged to electrically connect the first circuit layer with the third metal layer, and finally, the third metal layer is photoetched to form three first circuit layers connected with each other. It should be noted that the number of the circuit layers in the first semi-finished substrate is not limited to two or three, but may also be four or more. When there are more than three circuit layers, one dielectric layer and one metal layer may be laminated on the third circuit layer using the method above, and the metal layer is photoetched to form a new circuit layer.
In addition, with reference to
the semi-finished substrate 101, where the semi-finished substrate 101 may include the plurality of first circuit layers electrically connected with each other and at least one first dielectric layer; and the first circuit layers and the first dielectric layer are arranged in the staggered and laminated manner;
the viscous material layer 102, which may be arranged between the embedded device and the semi-finished substrate, where the viscous material layer 102 may be configured for fixing the device;
the embedded device 103, where the pin face of the embedded device may be arranged to face away from the first circuit layer of the semi-finished substrate;
the second circuit layer 104 which may be connected with the embedded device and the first circuit layer of the semi-finished substrate through the conductive pillar; and
the second dielectric layer which may be arranged between the semi-finished substrate and the second circuit layer, and completely covers the embedded device.
Further, the embedded device may include an active device, or a passive device. A specifically selected device type may be determined according to a function realized by a specific circuit.
Further, the viscous material layer may include a PID material layer or a DAF material layer. The PID material may completely cover all areas of the first circuit layer during laminating, and a part of the PID layer only used for adhering the device can be obtained after subsequent machining, while the DAF may be coated on the circuit layer, so that fixed-point coating can be realized.
In addition, an embodiment of the disclosure further provides a semiconductor. The semiconductor in the embodiment may be obtained by connecting two or more embedded substrates in the embodiment above with each other, or may be obtained by externally connecting a variety of different devices or circuit layer structures based on the embedded substrate in the embodiment above. The semiconductor can improve warping and product quality, and has a simple structure.
The substrate manufacturing method of the disclosure is described hereinafter with reference to the drawings.
With reference to diagrams a to f in
With reference to diagrams a to e in
All the contents in the above method embodiments are applicable to the apparatus embodiments, the specific functions realized by the apparatus embodiments are the same as those realized by the method embodiments above, and the beneficial effects achieved by the apparatus embodiments are the same as those achieved by the method embodiments above.
In the foregoing description, the explanation with reference to the terms “an implementation/embodiment”, “another implementation/embodiment” or “some implementations/embodiments”, etc. means that specific features, structures, materials or characteristics described in connection with the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. In the description, the illustrative expressions of the above-mentioned terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in any suitable manner.
Although the embodiments of the present disclosure have been shown and described, it can be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and objectives of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.
The above is a detailed description of the preferred implementation of the present disclosure, but the present disclosure is not limited to the embodiments described above. Those of ordinary skill in the art can also make various equivalent modifications or replacements without departing from the gist of the present disclosure, and these equivalent modifications or replacements are all included in the scope defined by the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022113899852 | Nov 2022 | CN | national |
