DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a cross-sectional view of a conventional COF package.
FIG. 2 shows partially a top view of a substrate of the conventional COF package.
FIG. 3 shows partially a top view of a semiconductor packaging substrate with heat-dissipating dummy patterns according to the preferred embodiment of the present invention.
FIG. 4 shows partially a cross-sectional view of the semiconductor packaging substrate with heat-dissipating dummy patterns according to the preferred embodiment of the present invention.
DETAIL DESCRIPTION OF THE INVENTION
Please refer to the attached drawings, the present invention will be described by means of embodiment(s) below.
According to the first embodiment of the present invention, as shown in FIG. 3 and FIG. 4, a semiconductor packaging substrate 200 with heat-dissipating dummy patterns includes a dielectric layer 210, a plurality of leads 220, at least a dummy pattern 230 and a plurality of heat-conducting bars 240 where the leads 220 are formed on the dielectric layer 210 and the leads 220 include at least a high-power lead 221. In the present embodiment, the high-power leads 221 may be electrical-power leads or high-frequency leads; moreover, the width of the high-power lead 221 is larger than or equal to that of the other leads 220. In this embodiment, the substrate 200 is a flexible film which can be implemented in COF or TCP, and the dielectric layer 210 is, for example, of polyimide or the like to provide good bending flexibility and good electrical isolation.
As shown in FIG. 3, the dummy pattern 230 is formed on the dielectric layer 210 and close to the high-power lead 221. Preferably, the dummy pattern 230 is disposed at the input side 201 of the substrate 200, which provides a larger area to configure heat-dissipating patterns compared to the output side (not shown) of the substrate 200. The dummy pattern 230 occupies the leadless area of the dielectric layer 210 and supplies no electrical functions.
The heat-conducting bars 240 thermally couple the high-power leads 221 to the dummy pattern 230 so that the dummy pattern 230 is not directly connected to the high-power leads 221. The widths of the heat-conducting bars 240 can be equal to that of the leads 220.
Preferably, the high-power leads 221 has a concave 222 to enhance the flexibility as well as the stress-buffering capability and to avoid broken leads and interface delamination between the high-power lead 221 and the dielectric layer 210. The dummy pattern 230 is accommodated in the concave 222 to dissipate the heat generated from the high-power leads 221 through the heat-conducting bars 240 such that it can enhance heat dissipation of the high-power leads 221 without affecting the stress-buffering capability. In the present embodiment, the widths of the heat-conducting bars 240 cannot be larger than that of the high-power leads 221 so that any impact on the stress-buffering capability can be avoided.
As shown in FIG. 4, the leads 220 including the high-power leads 221, the dummy pattern 230 and the heat-conducting bars 240 are made of the same metal layer to reduce the cost of disposing the dummy pattern 230 and to keep the flexibility of the substrate 200. In the present embodiment, the semiconductor packaging substrate 200 further comprises a solder mask 250 formed over the dielectric layer 210 to partially cover the leads 220 including the high-power leads 221 and the heat-conducting bars 240 to avoid the breaks of the heat-conducting bars 240 and to prevent the electrical shorts among the leads 220, the high-power leads 221, and the heat-conducting bars 240 due to contaminations. In this embodiment, the dummy patterns 230 are fully covered by the solder mask 250. In different embodiment, the dummy patterns 230 may be partially exposed from the solder mask 250. Normally the solder mask 250 has an opening 251 corresponding to the die-attaching area to expose the inner ends of the leads 220 including the high-power leads 221 to bond with a plurality of bumps on a chip, not shown in the figure.
Therefore, when the semiconductor packaging substrate 200 is implemented in a semiconductor package, the heat generated from the high-power leads 221 will be conducted to the dummy patterns 230 through the heat-conducting bars 240. The heat-dissipating efficiency is effectively enhanced by developing another heat dissipating path without increasing the dimension or the thickness of the semiconductor packaging substrate 200.
The above description of embodiments of this invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.
Patent Application
20080088039
