Substrates having voltage switchable dielectric materials

Information

  • Patent Grant
  • 8399773
  • Patent Number
    8,399,773
  • Date Filed
    Wednesday, January 27, 2010
    14 years ago
  • Date Issued
    Tuesday, March 19, 2013
    11 years ago
Abstract
Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include molding a substrate having a VSDM layer into a first shape.
Description
BACKGROUND

1. Technical Field


The present invention relates to designing and fabricating objects that incorporate voltage switchable dielectric materials.


2. Description of Related Art


A printed circuit board, printed wiring board, integrated circuit (IC) package, or similar substrate (hereinafter, PCB) may be used to assemble and connect electronic components. A PCB typically includes a dielectric material and one or more conductive leads to provide electrical conductivity among various attached components, chips, and the like. In some cases, metallic leads may be included (e.g., as a layer of Cu which is subsequently etched) to provide electrical connectivity.


A typical PCB may be fabricated from reinforcements (e.g., glass fibers) that have been pre-impregnated with a matrix (e.g., a polymer resin). A matrix may be combined with (e.g. infiltrated into) the reinforcement while substantially liquid. Handling of the pre-impregnated material may be enhanced by subjecting the matrix to a partial cure (e.g., a B-stage cure) to at least partially solidify the matrix, which may at a later stage be fully cured to a C-stage. A PCB may be fabricated from one or more layers of pre-impregnated material.


A pre-impregnated material is often described as a “prepreg.” Prepreg is typically available as a sheet or roll of material, and may be characterized by specifications such as grain (associated with “length” in the roll direction) and fill (associated with “width” in the roll direction). Prepreg may be characterized by various other specifications, such as dimensions (e.g., uncured thickness, cured thickness, and the like), reinforcement material (e.g., glass fibers having a diameter), weave pattern (e.g., of the fibers), matrix composition (e.g., resin composition, % matrix, fillers, and the like), curing protocols, and the like. A type of prepreg may be characterized by a “style,” which may summarize one or many parameters describing the prepreg. A style may include a description of the reinforcement type (e.g., woven glass), strand size, weave configuration, density, and the like. Exemplary standard styles include 106, 1080, 2313, 2116, 7628, and the like.


PCB fabrication may include choosing one or more layers of prepreg, stacking the layers, and curing the stacked layers (often with pressure) to form a solid substrate. Vias and/or leads may be incorporated on and/or within a PCB. Prepreg often shrinks during curing, typically in a predictable fashion, and expected shrinkage may be incorporated into a PCB specification. Many prepreg materials are anisotropic, particularly with respect to dimensional changes (e.g., during curing). Dimensional changes may be different in the grain direction than in another direction (e.g., the fill direction).


Many prepreg materials are characterized with one or more specifications for “artwork compensation,” which may describe an expected shrinkage during curing. Specifications for artwork compensation are often sufficiently controlled and predictable that they may be incorporated into the PCB design. The artwork compensation specification for a PCB fabricated from a stack of prepregs may often be calculated from the individual prepreg specifications, orientations, and stacking order of the prepreg layers.


A substrate, particularly a thin substrate, may be warped, bent, or otherwise deformed by various processes. In some cases, a substrate may be inadvertently deformed during processing (e.g., during curing of a PCB). A substrate may be warped by external forces. A substrate may be warped by internal elastic forces (e.g., a thermal expansion mismatch between materials).


Viewed in cross-section (i.e., viewing parallel to the plane of a PCB), a PCB may be characterized by a centerline. Typical PCB stacks are designed to be mechanically “balanced” with respect to the centerline, such that forces (e.g., induced during curing and/or cooling from high temperature) above the centerline are cancelled or otherwise opposed by equivalent forces below the centerline. For example, a prepreg layer with a first grain orientation and a first distance above the centerline may be balanced by an equivalent layer having the same grain orientation located the same distance below the centerline. Balancing is often achieved by creating a symmetrical prepreg stack with respect to the centerline. In some cases, the centerline may represent a line of mirror symmetry (at least with respect to mechanical and/or thermal properties), with layers above the centerline being balanced by corresponding “mirror” layers below the centerline.


Various electrical and electronic components may benefit from surge protection, such as protection against electrostatic discharge (ESD) and other electrical events. ESD protection may include incorporating a voltage switchable dielectric material (VSDM). A VSDM may behave as an insulator at a low voltage, and a conductor at a higher voltage. A VSDM may be characterized by a so-called “switching voltage” between these states of low and high conductivity. A VSDM may provide a shunt to ground that protects a circuit and/or component against voltages above the switching voltage by allowing currents at these voltages to pass to ground through the VSDM, rather than through the device being protected.


Many VSDM materials are polymer-based, and may include filled polymers. Processing a VSDM layer on a PCB may cause warping, which may be undesirable. Controlling dimensional changes (e.g., maintaining planarity) may improve the processing of devices incorporating a VSDM, and particularly a layer of VSDM on a thin substrate (whose dimensions may be altered by stress in the VSDM).



FIGS. 1A and 1B illustrate an exemplary unbalanced substrate (e.g., an unbalanced PCB). An unbalanced PCB 100 may be characterized by a centerline 110. A first portion 120 of the PCB (above centerline 120) may not be balanced by a corresponding second portion 130 of the PCB (below centerline 110). In some cases, imbalance may not be manifest until subsequent processing (e.g., curing the PCB and/or cooling from a curing temperature above room temperature). In the example shown in FIG. 1B, PCB 102 has been processed. In processed PCB 102, first portion 122 may have a higher shrinkage (e.g., during curing or cooling) than second portion 132, resulting in warpage of the processed PCB 102.


Voltage switchable dielectric materials may have thermal, elastic, plastic, viscous, and other properties that are different than those of typical prepreg layers. Incorporating a VSDM into a prepreg stack may result in an unbalanced substrate. During various processing steps, imbalance in a substrate may be manifest as loss of dimensional control (e.g., warpage of a PCB).


SUMMARY OF THE INVENTION

Various aspects provide for the incorporation of a voltage switchable dielectric material into a substrate in a manner that results in the substrate meeting various specifications, including dimensionality specifications. In some embodiments, a method for designing a PCB to meet a specification may comprise choosing a first design for a PCB comprising one or more prepreg layers. A first region comprising a VSDM may be incorporated into the first design to create an ESD-protected design. A balance region may be identified, whose incorporation into the ESD-protected design is expected or predicted to balance an imbalance induced by the incorporation of the first region. The balance region may be incorporated into the ESD-protected design to create a balanced, ESD-protected design.


Some designs may be substantially planar (e.g., sufficiently planar to meet a planarity specification or perform in a desired manner). Some designs include a centerline. Certain embodiments include a prepreg stack that does not display mirror symmetry with respect to a centerline associated with the prepreg stack. Some aspects include a balanced, ESD-protected PCB (and or PCB design) that does not have mirror symmetry with respect to a centerline associated with the ESD-protected design.


A first region incorporating a VSDM may be disposed on the same side of the centerline as a balance region. The first region may be on the opposite side of the balance region. The balance region may be on the same side as the first region and opposite side of the centerline. In some cases, a balance region may be disposed a greater distance from the centerline than the first region.


Incorporating a balance region may include adding or subtracting a prepreg layer from a prepreg stack. Incorporating a balance region may include adding a first and subtracting a second prepreg layer from a prepreg stack. In some cases, a balance region comprises a plurality of separate regions. An added prepreg layer may be a different style, thickness, grain orientation, resin content, reinforcement, weave, and/or different in other ways. An added prepreg layer may be the same as another prepreg layer already in a prepreg stack.


Incorporating a balance region may include adding another material to the substrate (e.g., other than another prepreg layer). A balance region may comprise a polymer, a ceramic, a metal, and/or composites thereof. A balance region may include a filled polymer, and may include a second VSDM material. In some cases, a material incorporated into a balance region may be chosen to have similar thermal, elastic, mechanical, or other properties similar to those of the first region incorporating the VSDM.


In some cases, a PCB design may be characterized by an artwork compensation specification, which may be an integrated or averaged value of the artwork compensation specifications of the components (e.g., prepreg layers) from which the PCB is fabricated. In some cases, a balance region may include a material having a larger artwork compensation specification than that of the first design. In certain cases, a balance region may include a material having a larger artwork compensation specification than those of the individual prepreg layers. A balance region may include a material having a larger coefficient of thermal expansion (CTE) than that of the first region and/or the stackup associated with the first design. In certain cases, a balance region may include a material having a larger CTE than those of the individual prepreg layers. A balance region may include a material having a CTE that substantially matches that of the first region. A balance region may include a material having a shrinkage percentage (e.g., a strain associated with shrinkage or expansion due to curing) that substantially matches that of the first region. In some embodiments, a balance region comprises a second VSDM having similar properties and opposite location (in the stack) as compared to the VSDM in the first region.


A printed circuit board may include one or more prepreg layers, and may be characterized by a lack of mirror symmetry associated with a centerline. In some examples, an ESD-protected PCB may include a VSDM. An ESD-protected PCB may be characterized by a lack of mirror symmetry with respect to a centerline associated with the ESD-protected PCB and/or a centerline associated with the one or more prepreg layers.


An ESD-protected PCB may have one or more dimensionality specifications within an industry-defined specification (e.g., IEEE, IEC, IPC, ISO, and the like). Certain ESD-protected substrates (e.g., an ESD-protected PCB) may be characterized by a flatness within a tolerance such as an IPC (Association Connecting Electronics Industries) 4101A specification.


Certain aspects provide for molding a substrate comprising a VSDM. In exemplary embodiments, a flexible substrate such as a carrier foil (e.g., a thin polymer, metal, or composite substrate) is provided. A VSDM may be coated on at least a portion of the carrier foil. The coated carrier foil may be formed into a shape (e.g., using a mold). A mold may include planar, parallel plates. A mold may include other shapes, such as a cylinder, sphere, ellipsoid, and the like. A coated substrate may be processed (e.g., cured) while molded. In some cases, curing a coated substrate while in the mold may result in a demolded, cured, coated substrate “springing back” to a shape other than that of the mold. A cylindrically molded substrate (e.g., with the VSDM facing outward) may be cured, cooled and demolded to yield a substantially flat, coated, substrate. A cylinder used for molding may have a diameter between 0.25 and 20 inches, between 0.5 and 10 inches, between 1 and 8 inches, and between 2 and 5 inches.





BRIEF DESCRIPTION OF THE DRAWINGS


FIGS. 1A and 1B illustrate an exemplary unbalanced substrate (e.g., an unbalanced PCB).



FIGS. 2A and 2B schematically illustrate a balanced substrate incorporating a VSDM, according to some embodiments.



FIGS. 3A, 3B, and 3C illustrate steps and structures associated with designing balanced, ESD-protected substrates, according to some embodiments.



FIGS. 4A, 4B, and 4C schematically illustrate several different balance regions, according to some embodiments.



FIG. 5 illustrates an incorporation of a balance region into a PCB design, according to some embodiments.



FIG. 6 illustrates an incorporation of a balance region into a PCB design, according to some embodiments.



FIG. 7 illustrates an incorporation of a balance region into a PCB design, according to some embodiments.



FIGS. 8 and 9 illustrate a method and associated structures, according to some embodiments.





DETAILED DESCRIPTION OF THE INVENTION

Various aspects provide for incorporating a VSDM into a substrate to create an ESD-protected substrate. In some cases, a VSDM is incorporated in a manner that results in the ESD-protected substrate meeting one or more specifications (e.g., thickness, planarity, and the like) for various subsequent processes or applications. Various aspects provide for designing a substrate (e.g., a PCB) incorporating a VSDM, and adjusting one or more aspects of the substrate to design a balanced, ESD-protected substrate. Certain embodiments include an ESD-protected substrate (e.g., incorporating a VSDM) that is mechanically and/or elastically balanced, but may not display a structural symmetry (e.g., mirror symmetry) with respect to a centerline through the substrate.


In some embodiments, a specification for a PCB is received, a VSDM is incorporated, and a balance region is incorporated into the design of the PCB to accommodate the incorporation of the VSDM while meeting the specification. Incorporating a balance region may include modifying the structure of the PCB (e.g., an order of a prepreg stackup). Incorporating a balance region may include modifying the components of the PCB (e.g., adding a polymer layer). Incorporating a balance region may include modifying the processing protocol (e.g., ramp rate, dwell time, pressure, and/or temperature associated with curing). Incorporating a balance region may include using forms, shapes, molds, and the like to mold the substrate/VSDM (or PCB) into a shape (e.g., during curing).


A VSDM may be applied as a layer to a carrier foil, which may be a polymer, a metal, a ceramic, a composite, and the like. A VSDM may be applied to a wafer, package, printed circuit board (PCB), printed wiring board (PWB), and the like. For the purposes of this specification, PCB may generally describe a substrate into which a VSDM may be incorporated.



FIGS. 2A and 2B schematically illustrate a balanced substrate incorporating a VSDM, according to some embodiments. Balanced PCB 200 includes a first region 210 incorporating a VSDM. In this example, first region 210 includes a VSDM disposed as a substantially planar layer, which in some cases may be between 0.2 and 5 mils thick, or between 1 and 3 mils thick. A first region may include a VSDM disposed in other geometries (e.g., lines, traces, and other volumes).


A balance region may include a portion of the substrate whose incorporation into the design balances one or more forces induced or associated with the VSDM (e.g., during subsequent processing). A balance region may include one or more additional layers of prepreg. A balance region may include another material (e.g., a polymer, a filled polymer, a VSDM, a resin layer, a reinforcement layer, and the like). A balance region may be characterized by the removal of a layer from the design. A balance region may be planar, and may include shapes other than planer.


In some embodiments, a balance region may be associated with a PCB stackup. Many typical PCB stackups (not incorporating a VSDM) are balanced. A PCB stackup incorporating a balance region may appear “imbalanced” with respect to a centerline, particularly when the inclusion of the VSDM is not accounted for (i.e., the PCB stack, ex-VSDM, may appear unbalanced). Concomitant incorporation of a first region comprising a VSDM and a balance region may result in a balanced PCB design, notwithstanding an apparent imbalance in the PCB stack ex-VSDM. Balanced PCB 200 may include a balance region 220.


In the example shown in FIGS. 2A and 2B, first region 210 may include a VSDM having a larger coefficient of thermal expansion (CTE) than that of other portions of the substrate other than balance region 220. Balance region 220 may have a similar (or the same) CTE as that of first region 210. In this example, first region 210 is disposed above centerline 230, and balance region 220 is disposed below (on the other side of) centerline 230. When first region 210 and balance region 220 have the same CTE, they may be disposed the same distance from centerline 230. When balance region 220 has a smaller CTE than that of first region 210, it may be disposed farther from centerline 230 (and vice versa).



FIG. 2B is a schematic illustration of a processed PCB. In this example, PCB 200 may be processed to form processed PCB 202. Processing may include heating, exposing to light, depositing, etching, ashing, pressing, curing, cutting, engraving, drilling, plating, soldering re-flowing, and the like. Processing may include attaching one or more components, such as resistors, capacitors, inductors, and the like. Processing may include attaching a chip, a package, a system-in-package (SIP), system-on-chip (SOC), and the like.


Processed PCB 202 may meet one or more specifications, such as thickness, flatness, size, thermal properties, dielectric properties, and the like. Some specifications may be standardized, (e.g., by a standards-setting organization), such as ISO, IEEE, IEC, IPC, JEDEC and the like. In some embodiments, a substrate (which may incorporate a VSDM layer) may meet a flatness standard, such as IPC-4101A



FIGS. 3A, 3B, and 3C illustrate steps and structures associated with designing balanced, ESD-protected substrates, according to some embodiments. A substrate designed for an application may be defined by one or more specifications. In this example, a first substrate design 300 may be a PCB, and may include one or more prepreg layers 310. In some cases, a prepreg stackup may be specified, which may result in a design that includes a centerline 320. In some cases, external properties (e.g., a desired thickness 312) may be specificed.



FIG. 3B schematically illustrates a design (that may be unbalanced) for an ESD-protected substrate. ESD-protected substrate design 302 includes a first region 330 that includes a VSDM. A VSDM may (inter alia) protect various circuits attached to the substrate. Protection may include protection against spurious electrical events, such as electrostatic discharge (ESD). For the purposes of this specification, a substrate incorporating a VSDM may be described as an ESD-protected substrate.



FIG. 3C illustrates a balanced, ESD-protected substrate design. In this example, a balanced ESD-protected substrate design 304 includes a first region 330 having a VSDM and a balance region 340. Balance region 340 may “balance” or otherwise counteract various undesirable effects associated with the incorporation of first region 330. Representative, non-limiting effects may include warpage induced by curing the VSDM, dimensional changes associated with CTE mismatch between the first region and other portions of the substrate, and the like. Balanced, ESD-protected substrate design 304 may not display mirror symmetry with respect to centerline 320.


A design may be modified to incorporate a balance region by calculating or otherwise estimating the effects of incorporation of the first region (e.g., the VSDM) on subsequent processing steps. For example, a shrinkage associated with curing of a VSDM may be measured on a test coupon. For a given thickness of VSDM (incorporated into a PCB design), VSDM properties, and associated process of the other materials in the PCB (e.g., prepreg), an expected effect may be calculated (e.g., using a rule of mixtures law and associated geometrical factors). In the example shown in FIG. 3C, the effect of incorporating a first region 330 (e.g., having a first curing shrinkage or first CTE) located a first distance 332 from centerline 320, may be calculated using the stackup geometry and associated properties of the stackup materials. Using computer simulation of one or more possible modifications to the unbalanced design, a type of layer having an appropriate combination of balance region parameters may be chosen that results in a balanced ESD-protected design. For example, designs having layers of different CTE values, thicknesses, distances 342, curing shrinkages, and the like may be simulated (e.g., using Finite Element Modeling of the design to predict properties), and a combination resulting in a balanced ESD-protected substrate may be selected. In some cases, a large number of pseudorandomly selected designs may be simulated (e.g., using Monte-Carlo simulation) and those resulting in the best match to desired properties may be selected.


In an exemplary calculation, a first design may include a first prepreg stackup. A planar first region incorporating a VSDM may be incorporated into the design. In some cases, a thickness, location, switching voltage, shape, and other properties of the first region may be at least partially determined by desired electrical properties (e.g., location of vias, lines, chips, and the like). An expected result of the incorporation may be calculated based on properties of the first region and properties of the prepreg stackup. Exemplary expected results include an expected warpage associated with curing the VSDM or expected warpage associated with cooling of a cured substrate from a higher temperature to room temperature. A balance region may be identified by simulating the addition, subtraction, (and/or both) of additional prepreg layers (and the corresponding effect on final properties). A “goodness of fit” parameter may be maximized such that a simulation is chosen that is most likely to result in desired properties. For example, a plurality of randomly selected additions/subtractions of prepreg layers may be simulated, and those that are most expected to result in a flat substrate after curing and cooling may be chosen. In some embodiments, desired properties (e.g., elastic moduli, curing shrinkage, CTE, thickness, location) of a balance region may be solved for analytically, and an appropriate material having such properties may be chosen and designed into the appropriate location or locations.



FIGS. 4A, 4B, and 4C schematically illustrate several different balance regions, according to some embodiments. FIG. 4A illustrates a balanced, ESD-protected design for a PCB 400. PCB 400 includes a first region 410 having a VSDM, located on a first side of a centerline 420. A balance region 430 may be at least partially disposed on the same side of the centerline as first region 410. Exemplary balance region 430 may be characterized by a curing shrinkage lower than that of various prepreg layers. Exemplary balance region 430 may have a higher, lower, or similar elastic modulus than that of various prepreg layers.



FIG. 4B illustrates a balanced, ESD-protected design for a PCB 402. PCB 402 includes a first region 410, having a VSDM, located on a first side of a centerline 420. In this example, balance region 440 is partially disposed on an opposite side of the centerline and partially disposed on the same side of the centerline as first region 410.



FIG. 4C illustrates a balanced, ESD-protected design for a PCB 404. PCB 404 includes a first region 410, having a VSDM, located on a first side of a centerline 420. In this example, substantially the entire PCB stackup has been redesigned (e.g., replaced with different prepreg layers) to balance the incorporation of first region 410. Balanced, ESD-protected substrates 400, 402, and 404 may not display mirror symmetry with respect to centerline 420.



FIG. 5 illustrates an incorporation of a balance region into a PCB design, according to some embodiments. FIG. 5 illustrates an exemplary incorporation that includes adding a prepreg layer. In this example an ESD-protected substrate 500 may include a first region 510 having a VSDM. In this example, the substrate includes a stack of four style-2113 prepreg layers, with the first region disposed as shown. ESD-protected substrate 500 may be unbalanced.


The design for ESD-protected substrate 500 may be modified to create a design for a balanced, ESD-protected substrate 502. In this example, balanced ESD-protected substrate 502 includes a balance region comprising an additional layer 520 of style 106 prepreg, inserted on the opposite side of the centerline (with respect to first region 510). In this example, additional layer 520 is inserted between the two layers of style 2113 prepreg, opposite the first region 510.


Certain embodiments include adjusting a type associated with a balance region (e.g., a type of prepreg layer). A type may be a multivariable descriptor of one or more (and in some cases, many) characteristics of a material such as a prepreg layer. Type may include a style and/or other parameters characterizing a layer, such as reinforcement (e.g., E-glass), resin type (e.g., epoxy), additional resins (e.g., multistage resins), halogen concentration, curative type, resin content, catalyst, resin filler type and loading, Tg, CTE, permittivity, loss, dielectric constant, modulus, and the like. In some cases, a type may include a standard characteristic (e.g., a style) modified and annotated to further define characteristics (e.g., a halogen-free, two-stage resin of style 106 having a high Tg). Choosing a type may include choosing appropriate prepreg parameters (e.g., resin composition, resin content, filler composition, filler content, curing kinetics, and the like).


Balanced ESD-protected PCB 502 may not display mirror symmetry with respect to the centerline 530, which may be located at a mid-point of the substrate (including the first region 510) or a mid-point of the PCB-stack (not including the first region 510). In some embodiments, the removal of one or more layers of prepreg, to rebalance an imbalanced PCB, may be described as the incorporation of a balance region.



FIG. 6 illustrates an incorporation of a balance region into a PCB design, according to some embodiments. In this exemplary incorporation, a first prepreg layer is removed and a second prepreg layer is added to a design. ESD-protected PCB 600 includes a first region 610 comprising a VSDM. Excluding the first region 610, the design includes four prepreg layers, layered in styles 7628-2113-centerline-2113-7628. First layer 610 is disposed between the upper 7628 and 2113 prepreg layers. The design for ESD-protected PCB 600 may be unbalanced.


Balanced ESD-protected PCB 602 includes a different prepreg stacking than that of ESD-protected PCB 600. An aspect of this difference may be described as a difference in prepreg layers on the opposite side of first region 610. In this example, the opposite layer of style 7628 prepreg has been swapped for two layers of style 2113 prepreg, resulting in a balanced, ESD-protected PCB. Balanced ESD-protected PCB 602 may not display mirror symmetry with respect to the centerline 630, which may be located at a mid-point of the substrate (including the first region 610) or a mid-point of the PCB-stack (not including the first region 610).



FIG. 7 illustrates an incorporation of a balance region into a PCB design, according to some embodiments. ESD-protected PCB 700 includes a first region 710 comprising a VSDM. Excluding the first region 710, the design includes four prepreg layers, layered in styles 7628-2116-centerline-2116-7628. First layer 710 is disposed between the upper 7628 and 2116 prepreg layers. The design for ESD-protected PCB 700 may be unbalanced.


Balanced ESD-protected PCB 702 includes a different prepreg stacking than that of ESD-protected PCB 700. Differences include an addition of a prepreg layer on the same side as first region 710, a swapping of prepreg layers on the opposite side of the centerline, and a change in grain orientation of prepreg layers.


In this example, an additional prepreg layer style 106 is added between first region 710 and adjacent prepreg layer style 2116. On the opposite side of the centerline, the styles 2116 and 7628 prepreg layers have been replaced with styles 1080, 2313, 1080′, and 2313′ in a stacking as shown. In this example, styles 1080 and 1080′ have different grain orientations, and styles 2313 and 2313′ have different grain orientations. Balanced ESD-protected PCB 702 may not display mirror symmetry with respect to the centerline 730, which may be located at a mid-point of the substrate (including the first region 710) or a mid-point of the PCB-stack (not including the first region 710).



FIGS. 8 and 9 illustrate a method and associated structures, according to some embodiments. FIG. 8 illustrates a method for processing a substrate comprising a VSDM. FIG. 9 illustrates exemplary associated structures.


A carrier foil 900 is provided in step 800. In step 810, a VSDM 910 may be applied to (e.g., coated on) at least a portion of the carrier foil 900. In step 820, the coated carrier foil may be shaped or formed using a mold 920. In some embodiments, an optional drying step may be performed on the coated carrier foil to dry and/or partially cure the VSDM. Molding may include the use of pressure 922. Pressure may be applied via an external component (e.g., mold 920). Pressure may be applied via internally-generated elastic forces. For example, a coated carrier foil may be wrapped around a cylinder. For situations in which the carrier foil has a much higher elastic modulus than that of the VSDM, the VSDM may be constrained to (and sheared by) the shape and size of the carrier foil. A mold may be any shape, including flat (e.g., planar, parallel plates), cylindrical, spherical, hyperbolic, ellipsoidal, parabolic, angled, and other shapes.


In step 830, the coated carrier foil is processed. In some cases, processing may include heating the coated carrier foil to a temperature, which may be performed in an oven 930. In some cases, pressure 922 may be maintained during processing. Processing may include curing, drying, post-cure treatments, exposure to light (e.g, ultraviolet light), vibration, ultrasonication, application of pressure or other forces, bending, stretching, clamping, and the like. In some embodiments, a coated carrier foil may be wrapped around a cylinder (e.g., with the VSDM facing outward), and the wrapped cylinder may be placed in an oven and heated to a curing temperature associated with the VSDM. A residual contraction of the cured VSDM/carrier foil composite (e.g., upon cooling and demolding) may yield a substantially planar carrier foil having a cured VSDM layer thereon.


Some embodiments include adjusting a formulation of a VSDM, which may include changing an epoxy (e.g., type, ratio), curative agent (e.g., type, ratio to epoxy or resin), and/or the addition of other additives to improve balance. Exemplary epoxies include Epon 828, GP611, Polybd, and the like. Exemplary curative agents include Dicyandiamide, Diaminodiphenylsulfone, Nadic methyl anhydrides, and the like.


A first region having a VSDM may consist of the VSDM. A first region may comprise a VSDM and another substance (or gaps, holes, and the like). A first region may be uniform (e.g., planar). A first region may include discrete elements (e.g., disks, lines, wires, and the like).


Some embodiments include sensors to sense various parameters (e.g., thickness, strain, temperature, stress, viscosity, concentration, depth, length, width, thickness, number of layers, coefficient of thermal expansion (CTE), switching voltage and/or voltage density (between insulating and conducting), trigger voltage, clamp voltage, off-state current passage, dielectric constant, time, date, and other characteristics). Various apparatus may monitor various sensors, and systems may be actuated by automated controls (solenoid, pneumatic, piezoelectric, and the like). Some embodiments include a computer readable storage medium coupled to a processor and memory. Executable instructions stored on the computer readable storage medium may be executed by the processor to perform various methods described herein. Sensors and actuators may be coupled to the processor, providing input and receiving instructions associated with various methods. Certain instructions provide for closed-loop control of various parameters via coupled sensors providing input and coupled actuators receiving instructions to adjust parameters. Certain embodiments include materials. Various embodiments include telephones (e.g., cell phones), USB-devices (e.g., a USB-storage device), personal digital assistants, laptop computers, netbook computers, tablet PC computers and the like.


The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.

Claims
  • 1. A printed circuit board having: one or more prepreg lavers;a first region including a voltage switchable dielectric material; anda flatness within one or more IPC standards for flatness; a balance region that offsets an imbalance in the printed circuit board associated with the first region.
  • 2. The printed circuit board of claim 1, wherein at least one standard includes a specification associated with IPC-4101A.
  • 3. The printed circuit board of claim 1, wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the stacking of the prepreg layers.
  • 4. The printed circuit board of claim 1, wherein a stacking of the prepreg layers is not characterized by mirror symmetry with respect to a centerline associated with the printed circuit board.
  • 5. The printed circuit board of claim 1, wherein any of the first region and balance region is substantially planar.
  • 6. The printed circuit board of claim 1, wherein the first region and at least a portion of the balance region are on opposite sides of a centerline of the printed circuit board.
  • 7. The printed circuit board of claim 6, wherein the first region and the portion of the balance region are the same distance from the centerline.
  • 8. The printed circuit board of claim 6, wherein the portion of the balance region is a greater distance from the centerline than the first region.
  • 9. The printed circuit board of claim 1, wherein the first region and at least a portion of the balance region are on the same side of a centerline.
  • 10. The printed circuit board of claim 1, wherein at least a portion of the balance region is a smaller or larger distance from a centerline than the first region.
  • 11. The printed circuit board of claim 1, wherein the first region is characterized by a first thermal expansion coefficient, and the balance region is characterized by a second thermal expansion coefficient.
  • 12. The printed circuit board of claim 1, wherein the balance region includes at least one prepreg layer.
  • 13. The printed circuit board of claim 12, wherein first and second prepreg layers are on the same side of a centerline.
  • 14. The printed circuit board of claim 12, wherein first and second prepreg layers are on opposite sides of a centerline.
  • 15. The printed circuit board of claim 12, wherein a first prepreg layer has a higher resin content than a second prepreg layer.
  • 16. The printed circuit board of claim 12, wherein a first prepreg layer has a larger artwork compensation specification than that of a second prepreg layer.
  • 17. The printed circuit board of claim 12, wherein each of a first and a second prepreg layer is characterized by an artwork compensation specification, and a difference between the artwork compensation specifications is greater than 0.0001 inches per inch of length in a grain direction associated with the respective prepreg layers.
  • 18. The printed circuit board of claim 12, wherein a first prepreg layer has a smaller diameter reinforcement than that of a second prepreg layer.
  • 19. The printed circuit board of claim 12, wherein at least a portion of a reinforcement associated with a first prepreg layer is of a different composition, size, or weave than that associated with a second prepreg layer.
  • 20. The printed circuit board of claim 12, wherein at least one prepreg layer includes a style 106 prepreg layer.
  • 21. The printed circuit board of claim 12, wherein first and second prepreg layers have different thicknesses.
  • 22. The printed circuit board of claim 12, wherein first and second prepreg layers have different basis weights.
  • 23. The printed circuit board of claim 12, wherein the balance region includes a polymer.
  • 24. The printed circuit board of claim 23, wherein the polymer includes a filled polymer.
  • 25. The printed circuit board of claim 24, wherein the filled polymer includes a second voltage switchable dielectric material.
CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of U.S. provisional patent application No. 61/147,730, filed Jan. 27, 2009 and entitled “Techniques for Reducing Warpage in the Application of VSD Material to Core and Substrate,” which is incorporated by reference herein.

US Referenced Citations (262)
Number Name Date Kind
3347724 Schneble, Jr. et al. Oct 1967 A
3685026 Wakabayashi et al. Aug 1972 A
3685028 Wakabayashi et al. Aug 1972 A
3723635 Smith Mar 1973 A
3808576 Castonguay et al. Apr 1974 A
3926916 Mastrangelo Dec 1975 A
3977957 Kosowsky et al. Aug 1976 A
4113899 Henry et al. Sep 1978 A
4133735 Afromowitz et al. Jan 1979 A
4252692 Taylor et al. Feb 1981 A
4269672 Inoue May 1981 A
4331948 Malinaric et al. May 1982 A
4359414 Mastrangelo Nov 1982 A
4405432 Kosowsky Sep 1983 A
4439809 Weight et al. Mar 1984 A
4506285 Einzinger et al. Mar 1985 A
4591411 Reimann May 1986 A
4642160 Burgess Feb 1987 A
4702860 Kinderov et al. Oct 1987 A
4714952 Takekawa et al. Dec 1987 A
4726877 Fryd et al. Feb 1988 A
4726991 Hyatt et al. Feb 1988 A
4732636 Varker Mar 1988 A
4799128 Chen Jan 1989 A
4888574 Rice et al. Dec 1989 A
4892776 Rice Jan 1990 A
4918033 Bartha et al. Apr 1990 A
4928199 Diaz et al. May 1990 A
4935584 Boggs Jun 1990 A
4977357 Shrier Dec 1990 A
4992333 Hyatt Feb 1991 A
4996945 Dix, Jr. Mar 1991 A
5068634 Shrier Nov 1991 A
5092032 Murakami Mar 1992 A
5095626 Kitamura et al. Mar 1992 A
5099380 Childers et al. Mar 1992 A
5142263 Childers et al. Aug 1992 A
5148355 Lowe et al. Sep 1992 A
5167778 Kaneko et al. Dec 1992 A
5183698 Stephenson et al. Feb 1993 A
5189387 Childers et al. Feb 1993 A
5246388 Collins et al. Sep 1993 A
5248517 Shrier et al. Sep 1993 A
5252195 Kobayashi et al. Oct 1993 A
5260848 Childers Nov 1993 A
5262754 Collins Nov 1993 A
5278535 Xu et al. Jan 1994 A
5282312 DiStefano et al. Feb 1994 A
5294374 Martinez et al. Mar 1994 A
5295297 Kitamura et al. Mar 1994 A
5300208 Angelopoulos et al. Apr 1994 A
5317801 Tanaka et al. Jun 1994 A
5340641 Xu Aug 1994 A
5347258 Howard et al. Sep 1994 A
5350621 Yuhas et al. Sep 1994 A
5354712 Ho et al. Oct 1994 A
5367764 DiStefano et al. Nov 1994 A
5378858 Bruckner et al. Jan 1995 A
5380679 Kano Jan 1995 A
5393597 Childers et al. Feb 1995 A
5403208 Felcman et al. Apr 1995 A
5404637 Kawakami Apr 1995 A
5413694 Dixon et al. May 1995 A
5416662 Kurasawa et al. May 1995 A
5440075 Kawakita et al. Aug 1995 A
5444593 Allina Aug 1995 A
5464658 Yuhas et al. Nov 1995 A
5476471 Shifrin et al. Dec 1995 A
5481795 Hatakeyama et al. Jan 1996 A
5483407 Anastasio et al. Jan 1996 A
5487218 Bhatt et al. Jan 1996 A
5493146 Pramanik et al. Feb 1996 A
5501350 Yoshida et al. Mar 1996 A
5502889 Casson et al. Apr 1996 A
5510629 Karpovich et al. Apr 1996 A
5550400 Takagi et al. Aug 1996 A
5557136 Gordon et al. Sep 1996 A
5571608 Swamy Nov 1996 A
5654564 Mohsen Aug 1997 A
5669381 Hyatt Sep 1997 A
5685070 Alpaugh et al. Nov 1997 A
5708298 Masayuki et al. Jan 1998 A
5714794 Tsuyama et al. Feb 1998 A
5734188 Murata et al. Mar 1998 A
5744759 Ameen et al. Apr 1998 A
5781395 Hyatt Jul 1998 A
5802714 Kobayashi et al. Sep 1998 A
5807509 Shrier et al. Sep 1998 A
5808351 Nathan et al. Sep 1998 A
5834160 Ferry et al. Nov 1998 A
5834824 Shepherd et al. Nov 1998 A
5834893 Bulovic et al. Nov 1998 A
5848467 Khandros et al. Dec 1998 A
5856910 Yurchenko et al. Jan 1999 A
5865934 Yamamoto et al. Feb 1999 A
5869869 Hively Feb 1999 A
5874902 Heinrich et al. Feb 1999 A
5888630 Sylvester et al. Mar 1999 A
5906042 Lan et al. May 1999 A
5910685 Watanabe et al. Jun 1999 A
5926951 Khandros et al. Jul 1999 A
5940683 Holm et al. Aug 1999 A
5946555 Crumly et al. Aug 1999 A
5955762 Hively Sep 1999 A
5956612 Elliott et al. Sep 1999 A
5962815 Lan et al. Oct 1999 A
5970321 Hively Oct 1999 A
5972192 Dubin et al. Oct 1999 A
5977489 Crotzer et al. Nov 1999 A
6013358 Winnett et al. Jan 2000 A
6023028 Neuhalfen Feb 2000 B2
6064094 Intrater et al. May 2000 A
6108184 Minervini et al. Aug 2000 B2
6114672 Iwasaki Sep 2000 A
6130459 Intrater Oct 2000 A
6160695 Winnett et al. Dec 2000 B2
6172590 Shrier et al. Jan 2001 B1
6180241 Suhir Jan 2001 B1
6184280 Shibuta Feb 2001 B1
6191928 Rector et al. Feb 2001 B1
6198392 Hahn et al. Mar 2001 B1
6211554 Whitney et al. Apr 2001 B1
6239687 Shrier et al. May 2001 B1
6251513 Rector et al. Jun 2001 B1
6310752 Shrier et al. Oct 2001 B1
6316734 Yang Nov 2001 B1
6340789 Petritsch et al. Jan 2002 B1
6351011 Whitney et al. Feb 2002 B1
6373719 Behling et al. Apr 2002 B1
6407411 Wojnarowski Jun 2002 B1
6433394 Intrater Aug 2002 B1
6448900 Chen Sep 2002 B1
6455916 Robinson Sep 2002 B1
6468593 Iazawa Oct 2002 B1
6512458 Kobayashi et al. Jan 2003 B1
6534422 Ichikawa et al. Mar 2003 B1
6542065 Shrier et al. Apr 2003 B2
6549114 Whitney et al. Apr 2003 B2
6570765 Behling et al. May 2003 B2
6593597 Sheu Jul 2003 B2
6621172 Nakayama Sep 2003 B2
6628498 Whitney et al. Sep 2003 B2
6642297 Hyatt et al. Nov 2003 B1
6657532 Shrier et al. Dec 2003 B1
6677183 Sakaguchi et al. Jan 2004 B2
6693508 Whitney et al. Feb 2004 B2
6709944 Durocher et al. Mar 2004 B1
6741217 Toncich et al. May 2004 B2
6797145 Kosowsky Sep 2004 B2
6869664 Vasoya et al. Mar 2005 B2
6882051 Majumdar et al. Apr 2005 B2
6903175 Gore et al. Jun 2005 B2
6911676 Yoo Jun 2005 B2
6916872 Yadav et al. Jul 2005 B2
6981319 Shrier Jan 2006 B2
7034652 Whitney et al. Apr 2006 B2
7049926 Shrier et al. May 2006 B2
7053468 Lee May 2006 B2
7064353 Bhat Jun 2006 B2
7067840 Klauk Jun 2006 B2
7075103 Yan et al. Jul 2006 B2
7095933 Barth Aug 2006 B2
7132697 Weimer et al. Nov 2006 B2
7132922 Harris et al. Nov 2006 B2
7141184 Chacko et al. Nov 2006 B2
7173288 Lee et al. Feb 2007 B2
7183891 Harris et al. Feb 2007 B2
7202770 Harris et al. Apr 2007 B2
7205613 Fjelstad et al. Apr 2007 B2
7218492 Shrier May 2007 B2
7253504 Zhai et al. Aug 2007 B1
7258819 Harris, IV Aug 2007 B2
7279724 Collins et al. Oct 2007 B2
7320762 Greuter et al. Jan 2008 B2
7341824 Sexton Mar 2008 B2
7417194 Shrier Aug 2008 B2
7446030 Kosowsky Nov 2008 B2
7488625 Knall Feb 2009 B2
7492504 Chopra et al. Feb 2009 B2
7528467 Lee May 2009 B2
7535462 Spath et al. May 2009 B2
7567416 Kim et al. Jul 2009 B2
7585434 Morita Sep 2009 B2
7593203 Dudnikov, Jr. et al. Sep 2009 B2
7595105 Yan et al. Sep 2009 B2
7609141 Harris Oct 2009 B2
7692313 Fan Apr 2010 B2
7825491 Kosowsky Nov 2010 B2
7872251 Kosowsky et al. Jan 2011 B2
7923844 Kosowsky Apr 2011 B2
8008767 Wada et al. Aug 2011 B2
8156640 Dudnikov et al. Apr 2012 B2
20020004258 Nakayama et al. Jan 2002 A1
20020050912 Shrier et al. May 2002 A1
20020061363 Halas et al. May 2002 A1
20030010960 Greuter et al. Jan 2003 A1
20030025587 Whitney et al. Feb 2003 A1
20030079910 Kosowsky May 2003 A1
20030151029 Hsu Aug 2003 A1
20030218851 Harris et al. Nov 2003 A1
20040000725 Lee Jan 2004 A1
20040062041 Cross et al. Apr 2004 A1
20040063839 Kawate et al. Apr 2004 A1
20040095658 Buretea et al. May 2004 A1
20040154828 Moller et al. Aug 2004 A1
20040160300 Shrier Aug 2004 A1
20040201941 Harris Oct 2004 A1
20040211942 Clark et al. Oct 2004 A1
20040241894 Nagai et al. Dec 2004 A1
20040262583 Lee Dec 2004 A1
20050026334 Knall Feb 2005 A1
20050039949 Kosowsky Feb 2005 A1
20050057867 Harris Mar 2005 A1
20050083163 Shrier Apr 2005 A1
20050106098 Tsang et al. May 2005 A1
20050121653 Chacko Jun 2005 A1
20050184387 Collins et al. Aug 2005 A1
20050218380 Gramespacher et al. Oct 2005 A1
20050255631 Bureau et al. Nov 2005 A1
20050274455 Extrand Dec 2005 A1
20050274956 Bhat Dec 2005 A1
20050275070 Hollingsworth Dec 2005 A1
20060060880 Lee et al. Mar 2006 A1
20060142455 Agarwal Jun 2006 A1
20060152334 Maercklein et al. Jul 2006 A1
20060166474 Vereecken et al. Jul 2006 A1
20060167139 Nelson et al. Jul 2006 A1
20060181826 Dudnikov, Jr. et al. Aug 2006 A1
20060181827 Dudnikov, Jr. et al. Aug 2006 A1
20060193093 Bertin Aug 2006 A1
20060199390 Dudnikov, Jr. et al. Sep 2006 A1
20060211837 Ko et al. Sep 2006 A1
20060214156 Pan et al. Sep 2006 A1
20060234127 Kim Oct 2006 A1
20060291127 Kim et al. Dec 2006 A1
20070114640 Kosowsky May 2007 A1
20070116976 Tan et al. May 2007 A1
20070123625 Dorade et al. May 2007 A1
20070139848 Harris et al. Jun 2007 A1
20070146941 Harris et al. Jun 2007 A1
20070208243 Gabriel et al. Sep 2007 A1
20070241458 Ding et al. Oct 2007 A1
20080045770 Sigmund et al. Feb 2008 A1
20080047930 Blanchet et al. Feb 2008 A1
20080073114 Kosowsky et al. Mar 2008 A1
20080144355 Boeve et al. Jun 2008 A1
20080217717 Pfister et al. Sep 2008 A1
20080278873 Leduc et al. Nov 2008 A1
20080295955 Cawse et al. Dec 2008 A1
20090044970 Kosowsky Feb 2009 A1
20090146319 Onda et al. Jun 2009 A1
20090309074 Chen et al. Dec 2009 A1
20100038119 Kosowsky Feb 2010 A1
20100038121 Kosowsky Feb 2010 A1
20100040896 Kosowsky Feb 2010 A1
20100044079 Kosowsky Feb 2010 A1
20100044080 Kosowsky Feb 2010 A1
20100078201 Yoshizaki et al. Apr 2010 A1
20100243302 Kosowsky et al. Sep 2010 A1
20100270588 Kosowsky et al. Oct 2010 A1
20110061230 Kosowsky Mar 2011 A1
20110062388 Kosowsky et al. Mar 2011 A1
Foreign Referenced Citations (28)
Number Date Country
3040784 May 1982 DE
10115333 Jan 2002 DE
102004049053 May 2005 DE
102006047377 Apr 2008 DE
0790758 Aug 1997 EP
1003229 May 2000 EP
1245586 Oct 2002 EP
1542240 Jun 2005 EP
1580809 Sep 2005 EP
1990834 Nov 2008 EP
56091464 Jul 1981 JP
63 195275 Aug 1988 JP
2000062076 Feb 2000 JP
WO 8906589 Jul 1989 WO
WO8906859 Jul 1989 WO
WO9602922 Feb 1996 WO
WO9602924 Feb 1996 WO
WO9726665 Jul 1997 WO
WO9823018 May 1998 WO
WO9924992 May 1999 WO
WO02103085 Dec 2002 WO
WO 2005100426 Oct 2005 WO
WO2006130366 Dec 2006 WO
WO2007062170 May 2007 WO
WO2007062171 May 2007 WO
WO2008016858 Feb 2008 WO
WO2008016859 Feb 2008 WO
WO2008153584 Dec 2008 WO
Non-Patent Literature Citations (22)
Entry
U.S. Appl. No. 12/714,354, Kosowsky, filed Feb. 26, 2010.
U.S. Appl. No. 12/714,358, Kosowsky, filed Feb. 26, 2010.
U.S. Appl. No. 12/703,674, Kosowsky, filed Feb. 10, 2010.
U.S. Appl. No. 12/703,701, Kosowsky, filed Feb. 10, 2010.
U.S. Appl. No. 12/703,723, Kosowsky, filed Feb. 10, 2010.
U.S. Appl. No. 12/832,022, Kosowsky, filed Jul. 7, 2010.
U.S. Appl. No. 12/833,023, Kosowsky, filed Jul. 7, 2010.
U.S. Appl. No. 12/832,040, Kosowsky, et al., filed Jul. 7, 2010.
U.S. Appl. No. 12/834,273, Kosowsky, et al., filed Jul. 12, 2010.
U.S. Appl. No. 12/834,296, Kosowsky, et al., filed Jul. 12, 2010.
Breton et al., “Mechanical properties of multiwall carbon nanotubes/epoxy composites: influence of network morphology,” Carbon Elsevier UK, vol. 42, No. 5-6, pp. 1027-1030 (2004).
Celzard, A., et al., “Conduction Mechanisms in Some Graphite-polymer Composites: The Effect of a Direct-current Electric Field”, Journal of Physics: Condensed Matter, 9 (1997) pp. 2225-2237.
Facchetti, Antonio, “Semiconductors for Organic Transistors”, Materials Today, vol. 10, No. 3, pp. 28-37.
Granstrom et al., “laminated fabrication of polymeric photovoltaic diodes,” Nature, vol. 395, pp. 257-260 (1998).
Guo et al., “Block Copolymer Modified Novolac Epoxy Resin,” Polymer Physics, vol. 41, No. 17, pp. 1994-2003 (2003).
Levinson et al. “The Physics of Metal Oxide Varistors,” J. App. Phys. 46 (3): 1332-1341 (1975).
Modine, F.A. and Hyatt, H.M. “New Varistor Material”, Journal of Applied Physics, 64 (8), Oct. 15, 1988, pp. 4229-4232.
Onoda et al., “Photoinduced Charge Transfer of Conducting Polymer Compositions,” IEICE Trans. Electronics, vol. E81-C(7), pp. 1051-1056 (1998).
Raffaelle et al., “Nanomaterial Development for Polymeric Solar Cells,” IEEE 4th World Conf on Photovoltaic energy Conversion, pp. 186-189 (2006).
Reese, Colin and Bao, Zhenan, “Organic Single-Crystal Field-Effect Transistors”, Materials Today, vol. 10, No. 3, pp. 20-27.
Saunders et al., “Nanoparticle-polymer photovoltaic cells,” Adv. Colloid Int. Sci., vol. 138, No. 1, pp. 1-23 (2007).
Wikipedia article for “Fullerene chemistry” as originally published on Apr. 8, 2010. http://en.wikipedia.org/wiki/Fullerene—chemistry.
Related Publications (1)
Number Date Country
20100187006 A1 Jul 2010 US
Provisional Applications (1)
Number Date Country
61147730 Jan 2009 US