Patent Grant
8609494
1. Field of the Invention
This application relates to a semiconductor device and a fabrication method therefor.
2. Description of the Related Art
High integration of a semiconductor integrated circuit and an integrated circuit especially using an MOS transistor has been enhanced.
Miniaturization has been developed to a nano region of a Metal-Oxide-Semiconductor (MOS) transistor used in an integrated circuit with high integration of the semiconductor integrated circuit. When the miniaturization of the MOS transistor progressed, control of leakage current is difficult. Furthermore, there was a problem that it cannot make an occupation area of a circuit easily small in order to secure of needed amount of current value. In order to solve such a problem, it is proposed as Surrounding Gate Transistor (SGT) having a structure where a source, a gate, and a drain are disposed in a vertical direction for a substrate, and the gate surrounds a columnar semiconductor layer (for example, refer to Japanese Unexamined Patent Application H2-71556).
In an MOS transistor, it is known that a compound layer formed of a compound of metal and silicon is provided on a highly doped silicon layer acting as a gate electrode, a source, and a drain. Lower-resistivity for the highly doped silicon layer can be achieved by forming a thick metal-silicon compound layer on the highly doped silicon layer. Also in SGT, the lower-resistivity for the highly doped silicon layer acting as a gate electrode, a source, and a drain can achieved by forming the thick metal-silicon compound layer on the highly doped silicon layer acting as a gate electrode, a source, and a drain.
However, if the thick metal-silicon compound layer is formed on the highly doped silicon layer of the upper part of a columnar silicon layer, the metal-silicon compound layer may be formed in a spike shape. If the metal-silicon compound layer is formed in a spike shape, the spike-shaped metal-silicon compound layer reaches not only the highly doped silicon layer formed in the upper part of the columnar silicon layer but a channel region under this highly doped silicon layer. Accordingly, it becomes difficult for the SGT to operate as a transistor.
The above-mentioned phenomenon is avoidable by thickening the highly doped silicon layer formed in the upper part of the columnar silicon layer. That is, what is necessary is just to thickly form the highly doped silicon layer more than the metal-silicon compound layer formed in a spike shape. However, since the electrical resistance of the highly doped silicon layer is proportional to the length, the electrical resistance of the highly doped silicon layer will increase if the highly doped silicon layer formed in the columnar silicon layer upper part is thickened. Therefore, it becomes difficult to achieve the low-resistivity for the highly doped silicon layer.
Moreover, there is a phenomenon that the thickness of the formed metal-silicon compound layer becomes thick as the diameter of the columnar silicon layer becomes small in the case that the metal-silicon compound layer is formed on the highly doped silicon layer of the upper part of the columnar silicon layer. If the diameter of the columnar silicon layer becomes small and the thickness of the metal-silicon compound layer formed on the columnar silicon layer becomes thick, the metal-silicon compound layer will come to be formed in the joint part between the highly doped silicon layer and channel region which are formed in the upper part of the columnar silicon layer. This causes leakage current.
The above-mentioned phenomenon is avoidable by thickening the highly doped silicon layer formed on the upper part of the columnar silicon layer. That is, what is necessary is just to form the highly doped silicon layer more thickly than the metal-silicon compound layer formed which becomes thick as the diameter of the columnar silicon layer becomes small. However, since the electrical resistance of the highly doped silicon layer is proportional to the length as above-mentioned, if the highly doped silicon layer formed in the upper part of the columnar silicon layer is thickened, the electrical resistance of the highly doped silicon layer increases and then it is difficult to achieve the low-resistivity.
Usually, in a MOS transistor, the metal-silicon compound layer formed on the highly doped silicon layer acting as a gate electrode, a source, and a drain is formed in the same processing step. Also in an SGT, the metal-silicon compound layer formed on the highly doped silicon layer acting as a gate electrode, a source, and a drain is formed in the same processing step as well as the MOS transistor. Therefore, in the SGT, when forming a thick metal-silicon compound layer in either of the highly doped silicon layers acting as a gate electrode, source, and drain, a metal-silicon compound layer will be formed in all the highly doped silicon layers acting as a gate electrode, source, and drain. As above-mentioned, when the metal-silicon compound layer is formed on the columnar semiconductor layer, the metal-silicon compound layer is formed in a spike shape. Therefore, the highly doped silicon layer formed in the upper part of the columnar silicon layer must be formed thickly so as to avoid that this spike shape metal-silicon compound layer reaches channel regions. As a result, the electrical resistance of this highly doped silicon layer will increase.
In the gate electrode of SGT, the same material as the material which forms the gate electrode often performs gate wiring. Therefore, the low-resistivity for the gate electrode and gate wiring is achieved by forming the metal-silicon compound layer thickly at the gate electrode and gate wiring. Accordingly, the high-speed operation of SGT becomes enabling. Also, in the SGT, it often wires using a planar silicon layer disposed under the columnar silicon layer. Therefore, the low-resistivity for this planar silicon layer is achieved by forming the metal-silicon compound layer thickly into the same layer as the planar silicon layer, thereby enabling the high-speed operation of SGT. On the other hand, since the highly doped silicon layer of the upper part of the columnar silicon layer of SGT connects to electric contact directly, it is difficult to wire with this highly doped silicon layer of the upper part of the columnar silicon layer. Therefore, the metal-silicon compound layer is formed between the electric contact and the highly doped silicon layer. Since current flows into the thickness direction of this metal-silicon compound layer, the low-resistivity for the highly doped silicon layer of the upper part of the columnar silicon layer is achieved corresponding to the thickness of the metal-silicon compound layer. As mentioned above, in order to thickly form the metal-silicon compound layer at the upper part of the columnar silicon layer, there is no other way but to thickly form the highly doped silicon layer formed in the upper part of the columnar silicon layer. However, since the electrical resistance of the highly doped silicon layer is proportional to the length, the electrical resistance of the highly doped silicon layer will increase if the highly doped silicon layer is thickly formed. As a result, it is difficult to achieve the low-resistivity for the highly doped silicon layer lower. Also, parasitic capacitance occurred between multilayer interconnections with the miniaturization of SGT as well as the MOS transistor, thereby there was also a problem that the operating speed of transistor is dropped.
This application is made in view of the above-mentioned situation, and the object is to provide a semiconductor device having satisfactory characteristics and having achieved miniaturization and, a fabrication method for such semiconductor device.
In order to achieve the above object, a semiconductor device according to a first aspect of the present invention comprises:
a first planar semiconductor layer;
a first columnar semiconductor layer formed on the first planar semiconductor layer;
a first highly doped semiconductor layer formed in a lower region of the first columnar semiconductor layer and the first planar semiconductor layer;
a second highly doped semiconductor layer formed in an upper region of the first columnar semiconductor layer and having a conductivity type same as a conductivity type of the first highly doped semiconductor layer;
a first gate insulating film formed so as to surround the first columnar semiconductor layer on a sidewall of the first columnar semiconductor layer between the first highly doped semiconductor layer and the second highly doped semiconductor layer;
a first gate electrode formed so as to surround the first gate insulating film on the first gate insulating film;
a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
a first insulating film sidewall formed so as to contact a top surface of the first gate electrode and an upper sidewall of the first columnar semiconductor layer, and to surround the upper region of the first columnar semiconductor layer;
a second metal-semiconductor compound layer formed in the same layer as the first planar semiconductor layer so as to contact the first highly doped semiconductor layer; and
a first electric contact formed on the second highly doped semiconductor layer, wherein
the first electric contact and the second highly doped semiconductor layer are connected directly and
the first gate electrode includes a first metal-semiconductor compound layer.
Preferably, further comprising a fifth metal-semiconductor compound layer formed between the first electric contact and the second highly doped semiconductor layer, wherein
the metal of the fifth metal-semiconductor compound is a different type of metal than the metal of the first metal-semiconductor compound layer and the metal of the second metal-semiconductor compound layer.
Preferably, the first gate electrode further comprises a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer.
In order to achieve the above object, a semiconductor device according to a second aspect of the present invention comprises a first transistor and a second transistor,
the first transistor comprising:
a first planar semiconductor layer;
a first columnar semiconductor layer formed on the first planar semiconductor layer;
a first highly doped semiconductor layer of a second-conductivity type formed in the lower region of the first columnar semiconductor layer and the first planar semiconductor layer;
a second highly doped semiconductor layer of the second-conductivity type formed in the upper region of the 1st columnar semiconductor layer;
a first gate insulating film formed so as to surround the first columnar semiconductor layer on a sidewall of the first columnar semiconductor layer between the first highly doped semiconductor layer and the second highly doped semiconductor layer;
a first gate electrode formed so as to surround the first gate insulating film on the first gate insulating film;
a first insulating film formed between the first gate electrode and the first planar semiconductor layer;
a first insulating film sidewall formed so as to contact to a top surface of the first gate electrode and an upper sidewall of the first columnar semiconductor layer and to surround the upper region of the first columnar semiconductor layer;
a second metal-semiconductor compound layer formed in the same layer as the first planar semiconductor layer so as to contact to the first highly doped semiconductor layer; and a first electric contact formed on the second highly doped semiconductor layer, and
the second transistor comprising:
a second planar semiconductor layer;
a second columnar semiconductor layer formed on the second planar semiconductor layer;
a third highly doped semiconductor layer of a first conductivity type formed in a lower region of the second columnar semiconductor layer and the second planar semiconductor layer;
a fourth highly doped semiconductor layer of the first conductivity type formed in an upper region of the second columnar semiconductor layer;
a second gate insulating film formed so as to surround the second columnar semiconductor layer on a sidewall of the second columnar semiconductor layer between the third highly doped semiconductor layer and the fourth highly doped semiconductor layer;
a second gate electrode formed so as to surround the second gate insulating film on the second gate insulating film;
a second insulating film formed between the second gate electrode and the second planar semiconductor layer;
a second insulating film sidewall formed so as to contact to a top surface of the second gate electrode and an upper sidewall of the second columnar semiconductor layer, and to surround the upper region of the second columnar semiconductor layer;
a fourth metal-semiconductor compound layer formed in the same layer as the second planar semiconductor layer so as to contact the third highly doped semiconductor layer; and
a second electric contact formed on the fourth highly doped semiconductor layer, wherein
the first electric contact and the second highly doped semiconductor layer are connected directly,
the second electric contact and the fourth highly doped semiconductor layer are connected directly,
the first gate electrode includes a first metal-semiconductor compound layer, and
the second gate electrode includes a third metal-semiconductor compound layer.
Preferably, further comprising:
a fifth metal-semiconductor compound layer formed between the first electric contact and the second highly doped semiconductor layer;
a sixth metal-semiconductor compound layer formed between the second electric contact and the fourth highly doped semiconductor layer, wherein
the metal of the fifth metal-semiconductor compound is a different type of metal than the metal of the first metal-semiconductor compound and the metal of the second metal-semiconductor compound, and
the metal of the sixth metal-semiconductor compound is a different type of metal than the metal of the third metal-semiconductor compound and the metal of the fourth metal-semiconductor compound.
Preferably, further comprising:
a first metal film formed between the first gate insulating film and the first metal-semiconductor compound layer; and
a second metal film formed between the second gate insulating film and the third metal-semiconductor compound layer.
Preferably, the first gate insulating film and the first metal film are formed from materials for configuring the first transistor to be an enhancement type, and
the second gate insulating film and the second metal film are formed from materials for configuring the second transistor to be an enhancement type.
In order to achieve the above object, a fabrication method for a semiconductor device according to a third aspect of the present invention being a method for fabricating the semiconductor device mentioned above, the fabrication method of aforesaid semiconductor device comprises the step of:
preparing a structure including: the first planar semiconductor layer; the first columnar semiconductor layer formed on the first planar semiconductor layer, a hard mask being formed in a top surface of the first columnar semiconductor layer; the first highly doped semiconductor layer formed in a lower region of the first planar semiconductor layer and the first columnar semiconductor layer; and a third insulating film formed on the hard mask and the first planar semiconductor layer;
forming a fourth insulating film, a third metal film, and a first semiconductor layer in this sequence on the structure;
etching the first semiconductor film to remain the first semiconductor film in a shape of a sidewall on a sidewall of the first columnar semiconductor layer;
etching the third metal film to remain the sidewall of the first columnar semiconductor layer in a shape of the sidewall;
etching the fourth insulating film to remain the sidewall of the first columnar semiconductor layer in a shape of the sidewall;
forming a second semiconductor layer on results of the step of etching the fourth insulating film;
forming a third semiconductor layer so that results of the step of forming the second semiconductor layer are embedded,
planarizing the second semiconductor layer, the third semiconductor layer and the first semiconductor layer and etching back so that an upper region of the third metal film is exposed;
etching the third metal film made remaining in the shape of the sidewall and the fourth insulating film made remaining in the shape of the sidewall so as to expose an upper sidewall of the first columnar semiconductor layer, and then forming the first metal film and the first gate insulating film;
forming a second highly doped semiconductor layer having a conductivity type same as the first highly doped semiconductor layer in the upper region of the first columnar semiconductor layer;
forming an oxide film and a nitride film sequentially on results of the step of forming the second highly doped semiconductor layer;
etching the oxide film and the nitride film so that the oxide film and the nitride film remain in a shape of the sidewall on the upper sidewall of the first columnar semiconductor layer and the sidewall of the hard mask, and then forming the first insulating film sidewall;
etching the first semiconductor layer, the second semiconductor layer and the third semiconductor layer to remain at least a part of the first semiconductor layer and the second semiconductor layer so as to surround the first metal film on the first metal film sidewall;
etching to remove the third insulating film exposed in the step of etching the semiconductor layer and exposing the first planar semiconductor layer;
by depositing and then annealing a metal on results of the step of exposing the first planar semiconductor layer, making react the deposited metal with a semiconductor included in the first planar semiconductor layer, and making react the deposited metal with a semiconductor included in the first semiconductor layer and the second semiconductor layer made to remain on the first metal film; and
by removing an unreacted metal in the step of making react the metal and the semiconductor, forming the second metal-semiconductor compound layer in the first planar semiconductor layer, and forming the first metal-semiconductor compound layer in the first gate electrode.
Preferably, further comprising the step of directly forming the first electric contact on the second highly doped semiconductor layer formed in the upper part of the first columnar semiconductor layer.
According to the present invention, the semiconductor device and the fabrication method for such semiconductor device having satisfactory characteristics and achieving the miniaturization can be provided.
With reference to
First of all, the NMOS-SGT of the first embodiment will be explained. A first planar silicon layer 212 is formed on a silicon dioxide film 101, and a first columnar silicon layer 208 is formed on the first planar silicon layer 212.
A first n+ type silicon layer 113 is formed in a lower region of the first columnar silicon layer 208 and a region of the first planar silicon layer 212 located under the first columnar silicon layer 208, and a second n+ type silicon layer 144 is formed in an upper region of the first columnar silicon layer 208. In this embodiment, the first n+ type silicon layer 113 functions as a source diffusion layer, and the second n+ type silicon layer 144 functions as a drain diffused layer. Moreover, a part between the source diffusion layer and the drain diffused layer functions as a channel region. The region of the first columnar silicon layer 208 between the first n+ type silicon layer 113 and the second n+ type silicon layer 144 which function as this channel region is a first silicon layer 114.
A first gate insulating film 140 is formed in the side surface of the first columnar silicon layer 208 so that the channel region may be surrounded. That is, the first gate insulating film 140 is formed so that the first silicon layer 114 is surrounded. The first gate insulating film 140 is composed of an oxide film, a nitride film, or a high dielectric film, for example. Furthermore, a first metal film 138 is formed on the first gate insulating film 140, and a first metal-silicon compound layer 159a (hereinafter, referred to as first compound layer) is formed in the sidewall of the first metal film 138. The first metal film 138 is a film including titanium nitride or tantalum nitride, for example. Also, the first metal-silicon compound layer 159a is formed of the compound of metal and silicon, and this metal is Ni, Co, or the like.
The first metal film 138 and first metal-silicon compound layer 159a compose a first gate electrode 210.
In this embodiment, a channel is formed in the first silicon layer 114 by applying voltage to the first gate electrode 210 at the time of operation.
A first insulating film 129a is formed between the first gate electrode 210 and the first planar silicon layer 212. Furthermore, a first insulating film sidewall 223 is formed in the upper sidewall of the first columnar silicon layer 208 so that the upper region of the first columnar silicon layer 208 is surrounded, and the first insulating film sidewall 223 contacts with the top surface of the first gate electrode 210. Also, the first insulating film sidewall 223 is composed of a nitride film 150 and an oxide film 152.
Furthermore, a second metal-silicon compound layer 160 is formed in the first planar silicon layer 212.
The second metal-silicon compound layer 160 is formed of the compound of metal and silicon, and this metal is Ni, Co or the like.
The second metal-silicon compound layer 160 is formed to contact with the first n+ type silicon layer 113, and functions as a wiring layer for providing power supply potential to the first n+ type silicon layer 113.
An electric contact 216 is formed on the first columnar silicon layer 208. In addition, the electric contact 216 is composed of a barrier metal layer 182 and metal layers 183 and 184. The electric contact 216 is directly formed on the second n+ type silicon layer 144. Accordingly, the electric contact 216 and the second n+ type silicon layer 144 are connected directly. In this embodiment, the electric contact 216 is contacted with the second n+ type silicon layer 144.
The barrier metal layer 182 is formed of metal, such as titanium or tantalum. The second n+ type silicon layer 144 is connected to an output wiring 220 via the electric contact 216. The output wiring 220 is composed of a barrier metal layer 198, a metal layer 199, and a barrier metal layer 200.
A seventh metal-silicon compound layer 159c is formed in a part of the side surface of the first metal-silicon compound layer 159a. In addition, a material which composes the seventh metal-silicon compound layer 159c is the same material as the first metal-silicon compound layer 159a. The seventh metal-silicon compound layer 159c functions as a gate wiring 218. An electric contact 215 is formed on the seventh metal-silicon compound layer 159c. The electric contact 215 is composed of a barrier metal layer 179 and metal layers 180 and 181. Furthermore, the electric contact 215 is connected to an input wiring 221 composed of a barrier metal layer 201, a metal layer 202, and a barrier metal layer 203. At the time of operation, input voltage is provided to the first gate electrode 210 via the electric contact 215 so that a channel is formed in the first silicon layer 114.
Also, an electric contact 217 is formed on the second metal-silicon compound layer 160. The electric contact 217 is composed of a barrier metal layer 185 and metal layer 186 and 187, and is connected to a power source wiring 222. The power source wiring 222 is composed of a barrier metal layer 204, a metal layer 205, and a barrier metal layer 206. Power supply potential is provided to both of the first n+ type silicon layer 113 and second metal-silicon compound layer 160 via the electric contact 217 at the time of operation.
The NMOS-SGT is formed according to such a configuration.
As mentioned above, in the NMOS-SGT according to this embodiment, the thick first, seventh and second metal-silicon compound layers 159a, 159c, and 160 are formed in the gate electrode 210, the gate wiring 218 and planar silicon layer 212. By such a structure of the SGT, the low-resistivity for the gate electrode 210 and planar silicon layer 212 is achieved, thereby enabling high-speed operation.
Furthermore, in the NMOS-SGT according to this embodiment, the electric contact 216 is directly disposed on the second n+ type silicon layer 144 comprising the highly doped silicon layer of the upper part of the columnar silicon layer 208. That is, since the metal-silicon compound layer is not formed between the electric contact 216 and the second n+ type silicon layer 144, the spike-shaped metal-silicon compound layer which may cause occurrence of leakage current is not formed. Even if the diameter of the columnar silicon layer is formed small for the purpose of high integration of the semiconductor device, the phenomenon in which the metal-silicon compound layer formed on the columnar silicon layer becomes still thicker is not occurred, either. Therefore, the above leakage current is not occurred. Also, since it is not necessary to thickly form the second n+ type silicon layer 144 comprising the highly doped silicon layer in order to suppress the occurrence of this leakage current, increase of the electrical resistance by the second n+ type silicon layer 144 is also avoidable.
According to the configuration mentioned above, the low-resistivity and the miniaturization for the semiconductor device are achievable.
Also, the parasitic capacitance between the gate electrode 210 and the planar silicon layer 212 can be reduced with the first insulating film 129a. Accordingly, the reduction of operating speed with the miniaturization of SGT is avoidable.
Next, PMOS-SGT according to this embodiment will be explained. A second planar silicon layer 211 is formed on a silicon dioxide film 101, and a second columnar silicon layer 207 is formed on the second planar silicon layer 211, as well as the NMOS-SGT mentioned above.
A first p+ type silicon layer 119 is formed in a lower region of the second columnar silicon layer 207 and a region of the second planar silicon layer 211 located under the second columnar silicon layer 207, and a second p+ type silicon layer 146 is formed in an upper region of the second columnar silicon layer 207. In this embodiment, the first p+ type silicon layer 119 functions as a source diffusion layer, and the second p+ type silicon layer 146 functions as a drain diffused layer. Also, a part between the source region and a drain region functions as a channel region. The region of the second columnar silicon layer 207 between the first p+ type silicon layer 119 and the second p+ type silicon layer 146 which function as this channel region is a second silicon layer 120.
A second gate insulating film 139 is formed in the side surface of the second columnar silicon layer 207 so that the channel region is surrounded. That is, the second gate insulating film 139 is formed in the side surface of the second silicon layer 120 so that the second silicon layer 114 is surrounded. The second gate insulating film 139 is composed of an oxide film, a nitride film, or a high dielectric film, for example. Also, a second metal film 137 is formed in the perimeter of the second gate insulating film 139. The second metal film 137 is a film including titanium nitride or tantalum nitride, for example. Also, a third metal-silicon compound layer 159b is formed in the perimeter of the second metal film 137. A material which composes the third metal-silicon compound layer 159b is the same material as that of the first metal-silicon compound layer 159a and that of the seventh metal-silicon layer 159c. The second gate electrode 209 is composed of the second metal film 137 and the third metal-silicon compound layer 159b. A seventh metal-silicon compound layer 159c formed between the first gate electrode 210 and the second gate electrode 209 functions as a gate wiring 218, and provides input potential to the second and first gate electrodes 209 and 210 at the time of operation.
In this embodiment, a channel is formed in a region of the second silicon layer 120 by applying voltage to the second gate electrode 209.
A second insulating film 129b is formed between the second gate electrode 209 and the second planar silicon layer 211. Furthermore, a second insulating film sidewall 224 is formed in the upper sidewall of the second columnar silicon layer 207, and the second insulating film sidewall 224 contacts with the top surface of the second gate electrode 209. The second insulating film sidewall 224 is composed of an oxide film 151 and a nitride film 149.
Also, a fourth metal-silicon compound layer 158 is formed in the second planar silicon layer 211 so as to contact with the first p+ type silicon layer 119. The fourth metal-silicon compound layer 158 is formed of the compound of metal and silicon, and this metal is Ni, Co or the like.
An electric contact 214 is formed on the second columnar silicon layer 207. In addition, the electric contact 214 is composed of a barrier metal layer 176 and metal layers 177 and 178. Also, the electric contact 214 is directly formed on the second p+ type silicon layer 146. Accordingly, the electric contact 214 and the second p+ type silicon layer 146 are connected directly. In this embodiment, the electric contact 214 is contacted with the second p+ type silicon layer 146.
The barrier metal layer 176 is formed of metal, such as titanium or tantalum. The second p+ type silicon layer 146 is connected to an output wiring 220 via the electric contact 214. The output of PMOS-SGT is outputted to the output wiring 220.
Also, as mentioned above, an electric contact 215 formed on the seventh metal-silicon compound layer 159c is connected to an input wiring 221, and the potential for forming a channel in the second silicon layer 120 is applied to the second gate electrode 209 from the input wiring 221. Furthermore, the gate electrodes 210 and 209 are connected by the gate wiring 218.
Also, an electric contact 213 is formed on the fourth metal-silicon compound layer 158. The electric contact 213 is composed of a barrier metal layer 173 and metal layers 174 and 175. The electric contact 213 is connected to the power source wiring 219 in order to input power supply potential into PMOS-SGT. The power source wiring 219 is composed of a barrier metal layer 195, a metal layer 196, and a barrier metal layer 197.
The PMOS-SGT is formed according to such a configuration.
Furthermore, an oxide film 126 is formed between the first planar silicon layer 212 and the second planar silicon layer 211 of adjoining PMOS-SGT, and a first insulating film 129a and a second insulating film 129b extends on the oxide film 126. Also, each transistor is separated by a nitride film 161 and an interlayer insulating film 162.
An inverter provided with the NMOS-SGT and PMOS-SGT is formed according to such a configuration.
In this embodiment, the first metal-silicon compound layer 159a, third metal-silicon compound layer 159b, and seventh metal-silicon compound layer 159c are formed in the same processing step by using the same material in one piece. Also, the first insulating film 129a and second insulating film 129b are formed in the same processing step by using the same material in one piece.
In the inverter according to this embodiment, the first gate insulating film 140 and first metal film 138 are formed by using a material which applies the NMOS-SGT an enhancement type, and the second gate insulating film 139 and second metal film 137 are formed by using a material which applies the PMOS-SGT an enhancement type. Therefore, the short circuit conduction current which flows at the time of operation of this inverter can be reduced.
Hereinafter, an example of a fabrication method for forming the inverter provided with the SGT of the first embodiment of this application will be explained with reference to
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Next, annealing is performed to activate the implanted impurity (arsenic). Accordingly, as shown in
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Next, annealing is performed to activate the implanted impurity (boron). Accordingly, as shown in
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Next, the oxide film 126a and oxide films 124 and 125 are etched, and as shown in
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The insulating film 129c becomes first and second insulating films 129a and 129b in the following processing step, and the first and second insulating films 129a and 129b can reduce parasitic capacitances between the gate electrode and the planar silicon layer.
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Next, the insulating film 132 is etched. As shown in
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In the case of using a high dielectric film for the gate insulating films 139 and 140, this high dielectric film may act as a source of the metal contamination. By forming the polysilicon film 141, the gate insulating film 139a and metal film 137a are covered with the columnar silicon layer 207, polysilicon films 135 and 141, insulating film 129c, and hard mask 106. Also, the gate insulating film 140a and metal film 138a are covered with the columnar silicon layer 208, the polysilicon films 136 and 141, insulating film 129c, and hard mask 107. That is, the gate insulating films 139a and 140a and metal films 137a and 138a acting as the contamination sources are covered with the columnar silicon layers 207 and 208, the polysilicon films 135, 136, and 141, insulating film 129c, and hard masks 106 and 107, and therefore the metal contamination due to a metal included in the gate insulating films 139a and 140a and metal films 137a and 138a can be suppressed.
After the metal film has been thickly formed and etched to remain in the sidewall shape, and then the gate insulating film has been etched, the polysilicon films is formed, thereby forming the structure in which the gate insulating films and metal films are covered with the columnar silicon layers, polysilicon films, insulating film, and hard masks.
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The sum of a film thicknesses of the nitride film 149 and oxide film 151, which are made to remain in the sidewall shape, will correspond to a film thickness of the gate electrodes afterward, and therefore by adjusting the deposition thicknesses and etching conditions of the oxide and nitride films 147 and 148, the gate electrodes having a desired thickness can be formed.
Also, the sum of a film thickness of the insulating film side walls 223 and 224 and a radius of the columnar silicon layers 207 and 208 is preferably larger than an outer circumferential radius of a cylinder formed by the gate insulating films 139 and 140 and metal films 137 and 138. Since the sum of the film thickness of the insulating film side walls 223 and 224 and radius of the columnar silicon layers 207 and 208 is larger than the outer circumferential radius of the cylinder formed by the gate insulating films 139 and 140 and metal films 137 and 138, metal films 137 and 138 are covered with the polysilicon film after gate etching, and therefore the metal contamination can be suppressed.
Further, on the basis of this processing step, the upper surfaces of the columnar silicon layers 207 and 208 have a structure covered with the hard masks 106 and 107 and insulating film sidewalls 223 and 224, respectively. The structure eliminates the formation of a metal-semiconductor compound on the surfaces of the columnar silicon layers 207 and 208. Still further, since the upper surfaces of the columnar silicon layers 207 and 208 have the structure covered with the hard masks 106 and 107 and insulating film sidewalls 223 and 224, the n+ type silicon layer and p+ type silicon layer are formed before the polysilicon is etched and the gate electrode is formed as explained using
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The gate electrode 209 is composed of the metal film 137 and polysilicon films 154 and 155 which react to metal to form a metal silicon compound in the following process, and the gate electrode 210 is composed of the metal film 138 and polysilicon films 156 and 157 which react to metal to form a metal silicon compound in the following processing step. The gate wiring 218 which connects between the gate electrode 209 and gate electrodes 210 is composed of the polysilicon films 154, 155, 142, 156 and 157 which react to metal to form a metal silicon compound in the following processing step. In addition, the polysilicon film 154 and 157 is a part which remained after the etching of the polysilicon films 135 and 136, and the polysilicon films 155 and 156 are a part which remained after the etching of the polysilicon film 141. Since the sum of the film thickness of the insulating film side walls 223 and 224 and radius of the columnar silicon layers 207 and 208 is larger than the outer circumferential radius of the cylinder formed by the gate insulating films 139 and 140 and metal films 137 and 138, the metal films 137 and 138 are covered with the polysilicon films 154, 155, 142, 156 and 157 after the gate etching, and therefore the metal contamination can be suppressed.
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A metal such as Ni or Co is sputtered on the results of the above-mentioned processing step and then subjected to heat treatment to thereby react the gate electrode polysilicon films 154 and 155, the gate electrode polysilicon films 154, 155, 142, 156, and 157, and planar silicon layer with the sputtered metal. Then, an unreacted metal film is removed by a sulfuric acid/hydrogen peroxide mixed solution or ammonia/hydrogen peroxide mixed solution. Accordingly, as shown in
On the other hand, the upper surfaces of the columnar silicon layers 207 and 208 have the structure covered with the hard masks 106 and 107 and insulating film sidewalls 224 and 223, and therefore in this processing step, any metal-silicon compound layer is not formed on the upper surfaces of the columnar silicon layers 207 and 208.
Between the metal-silicon compound layer 159 and the metal films 137 and 138, a polysilicon film may be present. Also, under the fourth metal-silicon compound layer 158, the p+ type silicon layer 119 may be present, and under the second metal-silicon compound layer 160, the first n+ type silicon layer 113 may be present.
A nitride film 161 is formed on the results of the above-mentioned processing step, and an interlayer insulating film 162 is formed so that the results in which the nitride film 161 is formed may be embedded. Next, as shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
As shown in
According to the above processes, the semiconductor device according to this embodiment is formed.
According to the fabrication method of this embodiment, the electric contacts 214 and 216 can be directly formed on the columnar silicon layers 207 and 208. Therefore, a thick metal semiconducting compound which may cause occurrence of leakage current is not formed on the columnar silicon layers 207 and 208. Also, since it is not necessary to thickly form the second n+ type silicon layer 144 and the p+ type silicon layer 146 comprising the highly doped silicon layers in order to suppress the occurrence of this leakage current, increase of the electrical resistance by the second n+ type silicon layer 144 and the p+ type silicon layer 146 of the highly doped silicon layers 144 and 146 is also avoidable.
Still Also, since the thick metal-silicon compound layers 158 to 160 can be formed in the gate electrodes 209 and 210 and the planar silicon layers 211 and 212 of the lower part of the columnar silicon layers 207 and 208, the low-resistivity of the gate electrodes 209 and 210 and planar silicon layers 211 and 212 can be achieved. Accordingly, the high-speed operation of SGT becomes enabling.
Also, since the first insulating film 129a and second insulating film 129b are formed between the gate electrodes 209 and 210 and the planar silicon layers 211 and 212, the parasitic capacitance between the gate electrode and the planar semiconductor layer can be reduced.
According to the configuration mentioned above, the low-resistivity and the miniaturization of the semiconductor device are achievable.
Although the fabrication method of the above-mentioned embodiment was explained using the inverter provided with the NMOS-SGT and PMOS-SGT, it can fabricate NMOS-SGT, PMOS-SGT, or a plurality of SGT(s) by the similar process.
In the above-mentioned embodiment, the case where the electric contact is contacted to the second highly doped silicon layer on the columnar semiconductor layer was explained. However, the fifth and sixth metal-silicon compound layers formed in the interface between the electric contact and the second highly doped silicon layer from a compound of a metal of the barrier metal layer and a semiconductor may be formed by making the metal of the barrier metal layer react to the silicon of the upper part of the columnar silicon layer when forming electric contact on a columnar silicon layer directly. In this case, since the fifth and sixth metal-silicon compound layers are thinly formed compared with the first to fourth and seventh metal-silicon compound layers, a problem of leakage current mentioned above is not occurred. Also, a metal included in the fifth and sixth metal-silicon compound layers is a metal which forms the barrier metal layer, and differs from the metal included in the first to fourth and seventh metal-silicon compound layers. In addition, the fifth and sixth metal-silicon compound layers may be formed or may not be formed depending on the material of the barrier metal layer.
In the above-mentioned embodiment, although the case where the gate electrode includes the metal film was explained, it is not necessary to include the metal film if it can function as a gate electrode.
In the above-mentioned embodiment, although the transistor of the enhancement type by which the channel is formed in the region of the first silicon layer 114 and second silicon layer 120 by applying voltage to the first gate electrode 210 and second gate electrode 209 was explained, the transistor may be a depression type.
In the above-mentioned embodiment, although the example which uses silicon is shown as the semiconductor, it also enables to use germanium, a compound semiconductor, etc. if the formation of the SGT enables.
As for material(s) for forming the metal layer, the insulating film, etc. in the above-mentioned embodiment, well-known material(s) can be also used suitably.
The substance name(s) mentioned above is exemplifying and therefore the present invention is not limited to this example.
Moreover, the present invention, to the extent that it does not deviate from the broad spirit and parameters of the present invention, may have various embodiments and modifications. In addition, the above described embodiment is provided to explain one embodiment of the present invention, but does not restrict the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-132488 | Jun 2010 | JP | national |
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| Number | Date | Country | |
|---|---|---|---|
| 20130252413 A1 | Sep 2013 | US |
| Number | Date | Country | |
|---|---|---|---|
| 61352961 | Jun 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13113482 | May 2011 | US |
| Child | 13895956 | US |
