Claims
- 1. A clock control circuit for a semiconductor device, comprising:
a clock enable control circuit receiving an external clock signal and an external clock enable signal, the clock enable circuit generating an internal clock enable signal, the-internal clock enable signal becoming active upon a transition of the external clock signal following the external clock enable signal becoming active, the internal clock enable signal becoming inactive upon a transition of the external clock signal following the external clock enable signal becoming inactive; and a clock gate coupled to the clock enable control circuit, the clock gate receiving the external clock signal and the internal clock enable signal, the clock gate generating at an output an internal clock signal from the external clock signal when the internal clock enable signal is active.
- 2. The clock control circuit of claim 1 wherein the clock enable control circuit causes the internal clock enable signal to become active on the trailing edge of the external clock signal following the external clock enable signal becoming active so that the external clock signal is thereafter coupled through the clock gate.
- 3. The clock control circuit of claim 1 wherein the clock enable control circuit causes the internal clock enable signal to become inactive responsive to the leading edge of the external clock signal following the external clock enable signal becoming inactive.
- 4. The clock control signal of claim 1 wherein the clock enable control circuit comprises:
an enableable buffer having a input signal input receiving the external clock signal and an enable input coupled to the external clock enable signal, the buffer being enabled responsive to the external clock enable signal becoming active thereby coupling the external clock enable signal to the output of the buffer; a first flip-flop having a data input coupled to the external clock enable signal and a clock input coupled to the output of the buffer so that an output of the first flip-flop changes state responsive to a transition of the external clock signal to a first of two logic levels following the external clock enable signal becoming active; and a second flip flop having a data input coupled to the output of the first flip flop and a clock input coupled to the output of the buffer so that an output of the second flip-flop changes state responsive to a transition of the external clock signal to a second of two logic levels following the external clock enable signal becoming active, the internal clock enable signal being generated from an output of the second flip-flop.
- 5. The clock control signal of claim 1, further comprising a pulse stretching circuit having an input coupled to the output of the clock gate, the pulse stretching circuit generating a pulse at its output that has at least a minimum duration responsive to each transition of the internal clock signal to a first of two logic levels.
- 6. The clock control signal of claim 5 wherein the pulse stretching circuit comprises:
a flip-flop having a set input and a reset input, the set input receiving the internal clock signal to set the flip-flop responsive to each transition of the internal clock signal to the first of two logic levels; and a delay circuit having an input receiving the internal clock signal and generating a delayed internal clock signal at an output a delay time after receiving the internal clock signal, the output of the delay circuit being coupled to the reset input of the flip-flop to reset the flip-flop responsive to each transition of the delayed internal clock signal to the first logic level so that an output of the flip-flop remains stable for at least the duration of the delay time responsive to each transition of the internal clock signal.
- 7. A method of generating an internal clock signal from an external clock signal and an external clock enable signal, the method comprising:
generating an internal clock enable signal upon a transition of the external clock signal following a transition of the external clock enable signal to a first logic level; terminating the internal clock enable signal upon a transition of the external clock signal following a transition of the external clock enable signal to a second logic level; and generating an internal clock signal from the external clock signal when the internal clock enable signal is being generated.
- 8. The method of claim 7 wherein the step of generating the internal clock enable signal comprises initiating the internal clock enable signal at the trailing edge of the external clock signal following the external clock enable signal transitioning to its first logic level.
- 9. The method of claim 7 wherein the step of terminating the internal clock enable signal comprises terminating the internal clock enable signal responsive to the leading edge of the external clock signal following the external clock enable signal transitioning to its second logic level.
- 10. The method of claim 7 wherein the method further comprises the step of generating a pulse having at least a minimum duration responsive to each transition of the internal clock signal to a predetermined logic level.
- 11. A semiconductor circuit device operable based on a clock signal and an internal signal, the semiconductor circuit device comprising:
a sample and hold circuit that receives and passes an external signal to an output terminal before an active clock pulse is applied to the semiconductor circuit device; logic circuitry coupled to the output terminal of the input latch and passing the external signal to an output terminal, the logic circuitry having gate delays; and a gate circuit coupled to receive the clock signal and coupled to the output terminal of the logic circuitry for receiving the external signal, the gate circuit providing the internal signal at an output when both the active clock pulse and the external signal are provided at inputs of the gate circuit.
- 12. The semiconductor circuit device of claim 11 wherein the external signal is an external command signal, wherein the external command signal is provided to the gate circuit before the active clock pulse is provided thereto, and wherein the internal signal is an internal command signal.
- 13. The semiconductor circuit device of claim 11 wherein the sample and hold circuit is an input latch coupled to receive the clock signal, and wherein the input latch passes the external signal before receiving the active clock pulse, and latches the external signal after receiving the active clock pulse.
- 14. The semiconductor circuit device of claim 11, further comprising an input buffer coupled to the sample and hold for receiving the external signal, and wherein the gate circuit is a NAND gate.
- 15. The semiconductor circuit device of claim 11 wherein the external and internal signals are external and internal address signals, respectively.
- 16. A method of providing an internal signal to a semiconductor circuit device, the semiconductor circuit device operable based on an active high pulse of a clock signal and the internal signal, the method comprising the steps of:
sampling an external signal; passing the external signal through a series of logic gates and incurring signal delays therefrom, before receiving the active high pulse of the clock signal; receiving the active high pulse of the clock signal; holding the external signal when the active high pulse of the clock signal is received; and validating the external signal as the internal signal when the active high pulse of the clock signal is received, and after passing the external signal through the logic gates.
- 17. The method of claim 16 wherein the step of receiving the external signal receives an external command signal, and wherein the step of validating the external signal validates the external command signal as an internal command signal.
- 18. The method of claim 16 wherein the step of receiving the external signal receives an external address signal, and wherein the step of validating the external signal validates the external address signal as an internal address signal.
- 19. A semiconductor memory device having at least two banks of memory arrays formed on a die, the device comprising:
a first memory array bank approximately centrally positioned on the die, the first array bank having first and second sets of sub-arrays corresponding to first and second sets of data paths, respectively; a second memory array bank having first and second sets of sub-arrays corresponding to the first and second sets of data paths, respectively, the first set of sub-arrays of the second memory array being positioned on a first side of the first array bank and adjacent to the first set of sub-arrays of the first array bank, and the second set of sub-arrays of the second memory array being positioned on a second side of the first array bank, opposite the first side, and adjacent to the second set of sub-arrays of the first array bank; and first and second sets of data pads positioned at a periphery of the die, the first set of pads being coupled to, and positioned adjacent, the first sets of sub-arrays of the first and second array banks, and the second set of pads being coupled to, and positioned adjacent, the second set of sub-arrays for the first and second array banks.
- 20. The device of claim 19 wherein the first array bank includes at least one row decoder shared, and positioned between, the first and second sub-arrays.
- 21. The device of claim 19 wherein the first and second sets of pad are coupled to the first and second sets of sub-arrays of the first and second array banks through a plurality of data paths, wherein the die is substantially square shaped, and wherein the datapaths are of approximately equal length relative to the size of the first and second array banks.
- 22. The device of claim 19 wherein the first and second sets of pad are coupled to the first and second sets of sub-arrays of the first and second array banks through a plurality of data paths, and wherein the datapaths are of approximately equal length.
- 23. The device of claim 19 wherein the first and second sub-arrays of the first and second array banks each include at least two columns of memory cells coupled to two input/output lines, wherein the two input/output lines are selectively coupled to a single data line based on a select signal, the single data line being coupled to one of the pads.
- 24. A data input/output circuit for a semiconductor memory device having at least first and second columns of memory cells, the circuit comprising:
first and second input/output lines coupled to the first and second columns, respectively; an input/output terminal; a single data line coupled to the input/output terminal; and a selection circuit for selecting one of the first or second input/output lines to the single data line responsive to a selection signal.
- 25. The circuit of claim 24, further comprising a die having the circuit formed thereon, and wherein the input/output terminal is a pad formed on the die, and wherein the selection circuit includes first and second pass gates coupled between the first and second input/output lines, respectively, and the single data line.
- 26. The circuit of claim 24, further comprising a die having the circuit formed thereon, and wherein the first and second columns form part of a substantially rectangular memory array having first and second row decoders positioned at opposite first and second sides of the memory array and first and second sets of sense amplifiers positioned at opposite third and fourth sides of the memory array, and wherein the selection circuit is positioned at a corner space between one of the first and second row decoders and one of the first and second sets of sense amplifiers.
- 27. The circuit of claim 24, further comprising a plurality of input/output terminals, and a terminal selection circuit coupled between the single data line and the plurality of input/output terminals, the terminal selection circuit selectively coupling the single data line to one of the plurality of input/output terminals responsive to a terminal select signal.
- 28. An automatic precharge circuit for a semiconductor memory device, the memory device having a plurality of memory cells arranged in a plurality of rows and columns, the memory device capable of rapidly writing data to the memory cells in response to a selected write command, the automatic precharge circuit comprising:
a first register circuit that receives the selected write command and a clock signal and outputs a receives automatic precharge command signal at least two clock cycles after receiving the selected write command signal; and a precharge circuit coupled to the row lines and the register circuit to precharge at least one row line in response to the automatic precharge signal.
- 29. The automatic precharge circuit of claim 28, further comprising:
a second register circuit that receives a clock signal and a write complete signal that indicates a completion of the rapid writing of data to the memory cells, the second register outputting the write complete signal at least one clock cycle after receiving the write complete signal; and a gate circuit coupled to receive the write complete signal and the automatic precharge signal and only outputting the automatic precharge signal when both of the write complete and automatic precharge signals are received.
- 30. A method of automatically precharging row lines in a semiconductor memory device, the method comprising the steps of:
generating a clock signal having clock cycles; receiving a write command; receiving a burst write command with automatic precharge after receiving the write command; waiting at least two clock cycles; generating an automatic precharge signal after waiting at least two clock cycles; and initiating automatic precharge of a selected row line in response to the automatic precharge signal.
- 31. The method of automatically precharging of claim 30, further comprising the steps of:
generating a burst write complete signal at least one clock cycle after receiving the burst write command; delaying the burst write complete signal at least one clock cycle; and generating the automatic precharge signal responsive to the burst complete signal.
- 32. Input circuitry for address signals input to a memory device having a plurality of addressable memory cells, the memory device operable based on a clock signal having high and law portions during each cycle, the input circuitry comprising:
an input latch coupled to receive at least one bit of an address byte during the low portion of each cycle of the clock signal, and the at least one bit therein during the high portion of each cycle of the clock signal; and address circuitry coupled to the input latch and receiving the at least one bit during the high portion of the clock signal.
- 33. The input circuitry of claim 32, further comprising an input switch coupled to an input of the input latch and coupled to receive and selectively pass at least one bit of an externally generated or an internally generated address.
- 34. A memory device, comprising:
an array of memory cells arranged in rows and columns; an external address circuit for receiving an external address corresponding to a row and a column of the memory array; a column counter for sequentially generating a series of internal addresses corresponding to a sequence of columns in the memory array; an address control circuit receiving the external address and the internal address, the address control circuit accessing columns of the memory array according to the external address responsive to a first control signal and accessing columns of the memory array according to the internal address responsive to a second control signal; and a redundant column selection circuit, the redundant column selection circuit comprising:
a first comparison circuit comparing the external address to a record of defective columns and generating an external address defect signal if the external address matches an address of a defective column in the array; a second comparison circuit comparing the internal address to a record of defective columns and generating an internal address defect signal if the internal address matches an address of a defective column in the array; and a redundant column control circuit substituting a redundant column for a defective column responsive to the first and second control signal so that the comparison of the external and internal addresses to the addresses of defective columns occurs before the address control circuit determines whether the columns of the memory array will be accessed according to the external address responsive to a first control signal or the internal address responsive to a second control signal.
- 35. The memory device of claim 34 wherein the first and second comparison circuits include respective records of defective columns in the memory array.
- 36. The memory device of claim 34 wherein the first and second comparison circuits each include a plurality of column match circuits each of which corresponds to a respective column specified by a plurality of low order bits of a memory address, each column match circuit including a record of high order bits of the a memory address, the high order bits in combination with the low order bits specifying an address in the memory array having a defective column.
- 37. In a memory device storing data in an array of rows and columns, a method of accessing the memory device according to either an externally generated address or an internally generated address, comprising:
comparing the external address to a record of defective columns and determining if the external address matches an address of a defective column in the array; comparing the internal address to a record of defective columns and determining if the internal address matches an address of a defective column in the array; after comparing the external and internal addresses to the record of defective columns, determining whether a column of the memory device array will be accessed according to the external address or according to the internal address; and if the column of the memory device array is to be accessed according to the external address, substituting a redundant column for the column of the memory device array to be accessed according to the external address if a determination has been made that the external address matches an address of a defective column in the array; and if the column of the memory device array is to be accessed according to the internal address, substituting a redundant column for the column of the memory device array to be accessed according to the internal address if a determination has been made that the internal address matches an address of a defective column in the array.
- 38. In a memory device storing data in an array of rows and columns, the array including a plurality of I/O lines selectively coupled to either respective sense amps responsive to a global column signal or to a respective data write driver responsive to an I/O select signal, a method of biasing the I/O lines before the I/O lines are coupled to either the sense amps or the data write drivers, the method comprising:
prior to accessing the memory array, determining whether the access with be a read access or a write access; if the access is determined to be a read access, biasing at least some of the I/O lines to a bias voltage for a first period of time; and if the access is determined to be a write access, biasing at least some of the I/O lines to a bias voltage for a second period of time that is shorter than the first period of time.
- 39. The memory device of claim 38 wherein the access to the memory array is to a selected column of the array, and wherein the step of biasing at least some of the I/O lines comprises biasing the I/O lines prior to connecting the I/O lines to the selected column.
- 40. A memory device, comprising:
an array of memory cells having a plurality of memory cells arranged in rows and columns, a plurality of sense amps selectively outputting data on a respective digit line for each column, a data path circuit coupled to a respective data bus line, each of the data path circuits including a data write driver adapted to receive data from its respective data bus line, and a plurality of I/O lines selectively coupled to either a respective digit line responsive to a global column signal or to a respective data write driver circuit responsive to an I/O select signal; a row decoder receiving a row address, the row decoder selectively enabling a row of memory cells in the array corresponding to the row address; a column decoder receiving a column address, the column decoder selectively enabling a column of memory cells in the array corresponding to the column address; a controller circuit generating a plurality of control signals including the global column signals when data is to be transferred from respective digit lines to an I/O line, and an I/O select signal when data is to be transferred from respective data write driver to an I/O line; and an I/O pull-up circuit coupled to each of the I/O lines, the I/O pull-up circuit receiving read and write control signals, the I/O pull-up circuit applying a bias voltage to the I/O line prior to coupling the I/O line to one of the sense amps responsive to a global column signal or to one of the data write drivers responsive to an I/O select signal, the I/O pull-up circuit applying the bias voltage to the I/O line for a first period responsive to the read control signal and for a second period responsive to the write control signal, the first period being longer than the second period.
- 41. The memory device of claim 40 wherein said pull-up circuit comprises:
a first delay circuit adapted to generate a first delayed signal responsive to a clock signal, the first delay circuit generating the first delayed signal at the expiration of the first period after the clock signal; a second delay circuit adapted to generate a second delayed signal responsive to a clock signal, the second delay circuit generating the second delayed signal at the expiration of the second period after the clock signal; a logic circuit having at least two inputs one of which is coupled to the clock signal, the logic circuit having an output causing the I/O pull-up circuit to apply the bias voltage to the I/O line; a multiplexer receiving the write and read signals, the multiplexer being coupled between the first and second delay circuits and the logic circuit to apply the first delayed signal to the other input of the logic circuit responsive to the read signal and to apply the second delayed signal to the other input of the logic circuit responsive to the write signal.
- 42. In a memory device having first and second banks of memory cells, the memory cells in each bank being addressable by row and column lines in response to first and second access commands during first and second access periods, a control circuit comprising:
a first latch that receives a first special function signal associated with the first bank during the first period; a second latch that receives a second special function signal associated with the second bank during the second period; an output circuit coupled to receive the first and second special function signals and provide first and second write per bit signals in response thereto; and a write circuit coupled to receive the first and second write per bit signals to write to a selected portion of the first or second banks in response to the write per bit signal during the first and second periods.
- 43. The control circuit of claim 42 wherein the first and second latches each include:
first and second input logic circuits that receive the first and second access commands and the first and second special function signals, and output the first and second special function signals, first and second flip-flops that store the first and second special function signals therein, and first and second output logic circuits that receive the stored first and second special function signals and a bank select signal, the first and second output logic circuits outputting the first and second special function signals in response to first and second values of the bank select signal, all respectively.
- 44. The control circuit of claim 42 wherein the output circuit includes a logic gate coupled to receive and output both of the first and second write per bit signals, and an output register for storing the first and second write per bit signals during the first and second periods, and
wherein the write circuit is coupled to receive the first and second write per bit signals from the output register during the first and second periods, all respectively.
- 45. In a memory device having a plurality of memory cells, the memory device operable based on a clock signal supplied thereto, a data output circuit comprising:
a clock circuit coupled to receive the clock signal and outputting an enable signal in response thereto; a data sense amplifier coupled to the clock circuit and to the plurality of memory cells and sensing a data signal from at least one of the memory cells in response to the enable signal; and an output circuit coupled to data sense amplifier for receiving the sensed data signal and providing the data signal to an output terminal.
- 46. The data output circuit of claim 45, further comprising a latch circuit coupled to receive the enable and data signals, the latch circuit latching the data signal therein in response to the enable signal.
- 47. In a memory device having a plurality of memory cells, a data output driver circuit comprising:
first and second driver circuits coupled to a data output terminal, the first driver circuit responsive to a high drive signal to provide a high value to the output terminal, and the second driver circuit responsive to a low drive signal to provide a low value to the output terminal; a logic circuit coupled to receive a data signal from at least one of the memory cells, the logic circuit providing the high drive signal to the first driver circuit if the data signal has the high value, and providing the low drive signal to the second driver circuit if the data signal has the low value; and a control circuit coupled to the first and second driver circuits and coupled to receive the data signal, the control circuit deactivating the first driver circuit if the data signal has the low value and before the logic circuit provides the low drive signal to the second driver circuit, and deactivating the second driver circuit if the data signal has the high value and before the logic circuit provides the high drive signal to the first driver circuit.
- 48. The data output driver circuit of claim 47 wherein the control circuit is coupled upstream of the logic circuit and between the plurality of memory cells and the logic circuit.
- 49. The data output driver circuit of claim 47 wherein the first and second output driver circuits are pull-up and pull-down driver transistors coupled to high and low voltage supplies, all respectively.
- 50. The data output driver circuit of claim 47, further comprising a capacitor coupled between the logic circuit and a first voltage supply so as to provide a time delay between receipt of the data signal and output of the low or high drive signal.
- 51. The data output driver circuit of claim 47, further comprising an output register coupled to the plurality of memory cells, control circuit and logic circuit, and positioned between the plurality of memory cells, and the control and logic circuits, and
wherein the logic circuit includes first and second logic gates that receive at a first terminal the data signal and a complement of the data signal from the output register, respectively, and receive at a second input terminal a data present signal, and wherein the first logic gate provides one of the low or high drive signals when both the data signal and the data present signal are substantially simultaneously received.
- 52. The data output driver circuit of claim 47, further comprising an output register coupled between the control and logic circuits and the first and second output driver circuits, and wherein the output register stores the low or high drive signal therein.
- 53. In a semiconductor memory device having an array of memory cells having multiple row and column lines and a plurality of output terminals, the row lines being coupled to the output terminals, the memory device capable of being coupled to receive a power supply signal, a power source comprising:
first and second power pump circuits coupled to receive the power supply signal and provide a power supply boosted above the power supply signal, the first power pump circuit being coupled to the multiple row lines and configured to provide the boosted power thereto, and the second power pump circuit being coupled to the plurality of output terminals and configured to provide the boosted power thereto; and an intercoupling circuit coupled to the power monitoring circuit and between the first and second power pump circuits, the intercoupling circuit permitting the boosted power provided by one of the first and second to be provided to the other of the first and second power pump circuits.
- 54. The power source of claim 53 wherein the first and second power pump circuits are voltage pump circuits, and wherein the intercoupling circuit is a transistor having first and second terminals coupled to the first and second voltage pump circuits, respectively, and having a control terminal coupled to receive a decoupling signal to decouple the first and second voltage pump circuits .
- 55. The power source of claim 53, further comprising:
a power monitoring circuit coupled to at least one of the row lines and output terminals to monitor the boosted power supplied thereto, and output a monitor signal if the boosted power supplied thereto falls below a predetermined value; and wherein the intercoupling circuit permits the boosted power provided by one of the first and second to be provided to the other of the first and second power pump circuits in response to the monitor signal.
- 56. The power source of claim 53 wherein the intercoupling circuit includes a plurality of switch elements and a plurality of transistors each having a control terminal coupled to receive an enable signal and having first and second terminals coupled to the first and second voltage pump circuits, wherein each transistor has a different maximum power throughput value, and wherein each of the plurality of switch elements are coupled between a one of the plurality of transistors and the power monitoring circuit to selectively permit each transistor to be coupled to the power monitoring circuit.
- 57. The power source of claim 53 wherein at least one of the first and second power pump circuits includes a disable terminal configured to disable the one first and second power pump circuit in response to a preselected signal provided thereto, the other of the first and second power pump circuits providing the boosted power to both the row lines and output terminals through the intercoupling circuit in response thereto.
- 58. The power source of claim 53 wherein the first and second power pump circuits are voltage pump circuits, and wherein the intercoupling circuit is a switch element capable of selectively coupling the first voltage pump circuit to the second voltage pump circuit.
- 59. The power source of claim 53 wherein the intercoupling circuit is a switch element capable of selectively coupling the first voltage pump circuit to the second voltage pump circuit, wherein at least one of the first and second power pump circuits includes a disable terminal configured to disable the one first and second power pump circuit in response to a preselected signal provided thereto, the other of the first and second power pump circuits providing the boosted power to both the row lines and output terminals through the switch element in response thereto.
- 60. A computer system, comprising:
an input device; an output device; an address bus; a data bus; a set of control lines; a memory controller coupled to the address and data buses and the set of control lines; a processor coupled to the input and output devices, and to the address and data buses and the set of control lines; and a memory device coupled to the memory controller through the address and data buses and the set of control lines, the memory device comprising:
an array of memory cells; first and second driver circuits coupled to a data output terminal, the first driver circuit responsive to a high drive signal to provide a high value to the output terminal, and the second driver circuit responsive to a low drive signal to provide a low value to the output terminal; a logic circuit coupled to receive a data signal from at least one of the memory cells, the logic circuit providing the high drive signal to the first driver circuit if the data signal has the high value, and providing the low drive signal to the second driver circuit if the data signal has the low value; and a control circuit coupled to the first and second driver circuits and coupled to receive the data signal, the control circuit deactivating the first driver circuit if the data signal has the low value and before the logic circuit provides the low drive signal to the second driver circuit, and deactivating the second driver circuit if the data signal has the high value and before the logic circuit provides the high drive signal to the first driver circuit.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No. 60/045,102, filed Apr. 25, 1997.
Provisional Applications (1)
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Number |
Date |
Country |
|
60045102 |
Apr 1997 |
US |
Divisions (1)
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Number |
Date |
Country |
Parent |
09066035 |
Apr 1998 |
US |
Child |
09572820 |
May 2000 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09572820 |
May 2000 |
US |
Child |
10345765 |
Jan 2003 |
US |