Patent Application
20070145104
Flip chips, including “Controlled Collapse Chip Connection” (C4) technology, may offer a proven standard interconnect technology for a number of applications including, for example, microprocessors and portable/mobile applications. To address these and additional potential applications, there is a desire to decrease bump pitch for high I/O and high power chips. The push for reduced bump pitch may result in corresponding decreases in via size opening, bump size, bump height, etc. To adequately address many potential applications, an understanding of IC package design and processing, including an understanding of materials and process flows may be needed.
Reliability of a flip chip may be impacted by the construction of the solder bumps and other assembly factors, including understanding and controlling the systems and methods to create the solder bumps. Variations in a bumping process or aspects thereof may result in a failure and/or reduced reliability of a flip chip device.
FIGS. 4 is an exemplary illustration of a system, according to some embodiments hereof.
The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
Some embodiments hereof provide a manufacturing process for producing a flip chip package. In some embodiments, the flip chip is formed using a wafer substrate that has a conductive solder bump formed in an opening in solder resist material disposed on a surface of the substrate. In a process of forming the solder bump, a mask material is removed after a reflow process of solder, in accordance with some embodiments herein.
Removing the mask material after the reflow of the solder may provide solder bumps that have an improved consistency in features such as height, as compared to solder bumps creating using a bumping process wherein the mask material is removed prior to the solder reflow process. In some embodiments, removal of the mask material after the reflow process eliminates or reduces mask lift-off of solder during the manufacturing process.
Referring to
At operation 105, a solder reflow process is performed. Solder located in an opening formed through both a solder resist material disposed on a substrate and a mask material disposed on top of the solder resist material is reflowed. The reflow of the solder may be accomplished by subjecting the solder to temperatures sufficient to reflow the solder. In some embodiments, the opening may be a solder resist opening.
It should be appreciated that the temperature needed to reflow the solder may vary, depending for example on the chemical composition of the solder. Those skilled in the relevant arts should appreciate this aspect of IC manufacturing. Accordingly, a discussion of specific solder materials and corresponding reflow temperatures are not included herein.
Proceeding to operation 110 of process 100, the mask material is removed. It is noted that the mask material is removed after the reflow of the solder. Thus, the solder bump is formed prior to a removal of the mask material. In this manner, process 100 reduces or avoids lifting-off solder during the removal of the mask material. By controlling the quantity of solder provided for the reflow process and removing the mask material after the reflow of the solder, the consistency or uniformity of the solder bumps formed by process 100 may be maintained.
At operation 205, a wafer including a substrate having solder resist material on a first surface of the substrate is created, obtained, or otherwise provided for use in process 200. The substrate may be produced or formed using any number of methods and techniques of IC (integrated circuit) manufacturing processes that result in a substrate suitable and compatible with the various aspects and embodiments herein.
In some embodiments, substrate 305 may include a single or multilayer dielectric material. The dielectric material may be selected to include any number of materials compatible with and suitable for IC manufacturing processes, not limited to those explicitly discussed herein. Furthermore, those skilled in the art are familiar with the range of substrate materials compatible with the various embodiments herein. In some embodiments, substrate 305 may include build-up layers of ABF (Ajinomoto Build-Up Film) or other organic film layer.
At 210, the substrate is processed to apply a mask material on top of the solder resist material. The wafer is processed through an IC manufacturing flow, conventional or otherwise, to pattern mask material on top of the solder resist material. The bi-layer of solder resist material and mask material is applied to at least a portion of a surface of the substrate. That is, the bi-layer of solder resist material and mask material may be selectively applied to the substrate in a desired pattern. The pattern of application for the bi-layer may be varied depending on a particular IC manufacturing flow, application, and use for wafer 300.
At operation 215, an opening is created through both the solder resist material and the mask material. The opening may be removed using a number of chemical and/or mechanical methods and techniques. In some embodiments, a laser projection patterning (LPP) technique may be used to drill through the solder resist material and the mask material. According to some LPP techniques, a laser beam at a predetermined wavelength may be used to irradiate the solder resist material and the mask material to ablate therethrough to a desired depth. In some embodiments, the desired depth corresponds to a depth that extends down through the solder resist material and the mask material to a solder bump pad (e.g., a bump site).
Referring to
In some embodiments, opening 320 may extend down through both solder resist material 310 and mask material 315 to an under bump metallization (UBM) layer (not shown) and/or other material.
At operation 220, as illustrated in
At operation 225, as illustrated in
At operation 230, as illustrated ion
In some embodiments herein, removal of mask material after the reflow process to create solder bump provides facilitates a mechanism for providing consistent or uniform solder bumps. By controlling the size of the opening, the amount of solder placed in the opening, and removing mask material after the reflow process, the amount of solder subjected to the reflow process may be consistently maintained. Thus, consistent or uniform solder bumps may be provided in accordance with some of the embodiments herein.
In some embodiments, the height of the solder bumps created in accordance with some embodiments herein may vary about 5 micrometers (μm) or less.
In some embodiments herein, the opening created through both the solder resist material and the mask material is done substantially at the same time. For example, the opening through both the solder resist material and the mask material may be made using a single laser beam in a LPP process. Other methods, techniques, and processes may be used to create the opening through both the solder resist material and the mask material. In this manner, alignment of the opening through the solder resist material and the opening through the mask material may coincide. That is, the opening through both the solder resist material and the mask material may be coincident through the different materials.
In some embodiments, the opening through both of the solder resist and mask materials may be made at the same time to achieve alignment of the opening through the various layers (e.g., solder resist material, mask material) of the opening. In some embodiments, an alignment tolerance of about 5 um or less may be achieved by making the opening through the various layers at the same time.
In some embodiments herein, the mask material is not constructed of a photosensitive material. For example, in some embodiments herein the mask material is removed using a laser beam. Accordingly, the mask material need not be photosensitive to effectuate an etching processing that depends on the photosensitivity of the mask material.
In some embodiments herein, the mask material (e.g., 315) is a disposable mask material. As such, a cost savings may be realized by some of the methods, apparatuses, and systems herein. For example, the mask material may not have certain properties needed in other IC manufacturing processes such as, for example, photosensitivity, etc. Disposable mask materials compatible with some embodiments herein may include, for example, dry film resist.
In some embodiments, IC device 420 is placed in contact with solder bumps 415. IC device 420 may contact solder bumps 415 at conductive connectors, pads, and traces (not shown) to provide electrical connectivity between IC device 420 and substrate 405, through solder bumps 415. In some embodiments, an apparatus, system, and device may include solder bumps 420 created by removing a mask material (not shown) (e.g., a disposable mask material) previously disposed on top of solder resist material 410 and subsequently removed therefrom after a reflow process used to create solder bumps 420.
It should be appreciated that the drawings herein are illustrative of various aspects of the embodiments herein, not exhaustive of the present disclosure. For example,
The several embodiments described herein are solely for the purpose of illustration. Persons in the art will recognize from this description that other embodiments may be practiced with modifications and alterations limited only by the claims.
