Patent Application
20060250731
Static electricity or static charge is the accumulated electric charge of an object that is typically an electric potential stored in the surface of the object that will discharge when presented with a conductive path to another object or ground. This electrostatic discharge (ESD) may create a transient voltage that, in turn, induces a transient current that may exceed maximum capacity thresholds for typical electronic circuits, thus, causing irreparable damage to sensitive electronic circuits and any associated components. Hence, this is the reason why printed circuit boards are always packaged and handled with anti-static plastic coverings. Additionally, typical electronic circuits include some form of ESD protection devices dealing with high-level transients.
Typically, an ESD protection device 120 is designed to appear as an open circuit when low-voltage, low-current, steady-state signals are present at the protected node 130. Conversely, the ESD protection device 120 is designed to appear to be a short circuit when high-voltage, high-current, transient signals are present on the protected node 130. As such, when operating normally, signals at the protected node 130 may propagate normally as though the ESD protection device 120 is not part of the overall circuit 100. When a threshold (either voltage or current) is exceeded, however, the ESD protection device 120 is “activated” and diverts high-level, transient signals away from the protected component 110 through the current-shunt node 131 and eventually to point in the circuit 100 capable of handling the excessive transient signals, such as ground or a battery.
For example, an ESD event may cause a high-level transient voltage (typically as much as 16 kV) that will eventually cause damage to the protected component 110. However, the current that may be induced at the protected node 130 as a result of the 16kV ESD causes the ESD protection device 120 to trigger thus, diverting the high currents through the ESD protection device 120 to the current-shunt node 131 which may typically be a ground node. Thus, the unsafe currents are dissipated before having a chance to cause damage to the protected component 110.
Various types of ESD protection devices 120 are known in the art. Examples of such devices include diode clamps to ground, diode clamps to battery, and various networks of ESD protection that utilize resistor-diode clamps and active core-shunt clamps. In each of theses cases, however, these ESD protection devices are fabricated as part of an integrated circuit (IC) and require extensive die area to be realized because of the nature of the components, i.e., diodes, resistors, etc. When dealing with limited space in an IC, die area becomes an issue such that the ESD protection scheme may suffer for lack of available space on the IC. Furthermore, these ESD devices are typically only realized on the top surface of the IC, thus requiring extensive signal routing for optimal ESD protection.
In another past solution, the above-described ESD protection devices can be realized as surface-mount technology (SMT) devices. That is, the implementations of these ESD protection devices are mounted to the PCB and require pin-outs and/or pads on the PCB to interface with other components of the PCB. However, PCB space is again an issue as each additional SMT device requires at least one pin-out or pad to pass electrical signals to and from the PCB. Furthermore, SMT devices are more expensive and increase the size of the package surrounding the PCB because of the additional space off chip required by the SMT devices. Signal routing in the PCB also remains a problem.
In yet another solution of the past, an ESD protection scheme may be realized through a “gasket layer” that may be fabricated along with the PCB. The gasket layer provides matrix-connected paths for ESD currents between various signal points and a respective ground path, battery path, or other signal path. However, the gasket layer, having two conductive layers, must be used strictly for ESD protection due to signals being routed using both conductive layers of the gasket layer. Thus, not only is the additional layer completely used for only ESD protection, it may not be used for other purposes, such as routing of battery or ground signals. Furthermore, the routing paths for ESD currents is longer and, thus, more inductive and resistive than what is ideally desired.
Each of the above solutions of the past require additional area in precious board or die space and are, thus, undesirable as a means of providing ESD protection to PCBs and associated electrical components. Furthermore, the routing paths for each of the above solutions remains longer than is desirable which adds complexity, resistance, and inductance to the discharge paths. Additionally, longer routing paths, increased board or die space, and additional layers all add to the cost of product design and fabrication. A more optimal solution with shorter discharge paths for ESD currents in a PCB is desirable.
An embodiment of the invention is directed to an electronic circuit for protecting electronic components from electrostatic discharge. A PCB or an IC may include an electrostatic discharge protection layer having a first and second conductive layer separated by a semi-conductive dielectric layer. Further, the PCB or IC may include a protected node electrically coupled to the first conductive layer and a current-shunt node electrically coupled to the second conductive layer, such that a signal at the protected node that is below a threshold magnitude propagates through the protected node in a normal operating path and a signal at the protected node that exceeds a threshold magnitude is diverted to propagate through the semi-conductive dielectric layer to the current-shunt node in a current-shunt path. In this manner, existing layers of a PCB or IC may be used for both ESD protection and other functions, such as ground planes or battery plane by isolating the specific sections of the layer for its intended use.
Utilizing existing layers in a PCB or IC to realize an ESD protection scheme is advantageous for a number of reasons. For one, no additional layers need to be fabricated for the sole purpose of providing ESD protection. Furthermore, signal routing and signal paths become less complicated and intrusive as typically the ground plane and the battery plane are often prevalent throughout all areas of the PCB or IC. As a result, the circuitry of the PCB or IC becomes less complicated which results in less labor-intensive design and fabrication and smaller PCBs and/or ICs. Both of these advantages, in turn, result in cheaper fabrication and design, as well. Depending on the particular routing of the ESD scheme, a more robust dissipation region may be realized within the PCB or IC because of the nature of the semi-conductive dielectric material and its proximity to several ground nodes. Finally, space and money is saved by not having any SMT devices required as part of an ESD protection scheme.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The following discussion is presented to enable a person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the present invention. The present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.
In this embodiment, layer 3210c and layer 4210d may be fabricated to have a semi-conductive dielectric 212 between them. The semi-conductive dielectric 212 may be a polymer-based formulation or polymeric solution designed to have specific electrical characteristics that provide ESD protection capabilities. The semi-conductive dielectric 212 is formulated to be sensitive to high-level transient signals such that an ESD surge event or other similar transient disturbance will invoke the conductive nature of the semi-conductive dielectric 212. When not is an ESD event situation, the semi-conductive dielectric 212 remains non-conductive. Collectively, layer 3210c, layer 4210d, and the semi-conductive dielectric 212 may be referred to as the ESD protection device layer 215.
In the ESD protection device layer 215, there may be several active regions, such as active region 245, wherein layer 3210c and layer 4210d overlap. An active region 245 may pass high-current, transient signals but block low-level, steady state signals. Each active region 245 serves as an ESD protection device between a protected node 240, and a current-shunt node 241.
In the embodiment of
Each signal node 220 and 221 may be connected to each layer 210a-210f through respective vias 230 and 231. Thus, a signal at the first signal node 220 may be routed to any other layer 210a-210f through the first via 230. Likewise, a signal at the second signal node 221 may be routed to any other layer 210a-210f through the second via 231. As a result, a routing path for either signal at either signal node 220 and 221 may be provided to the ESD protection layer 215 as shown in
For example, the first signal node 220 is electrically coupled to the first via 230 which provides an electrical coupling to each layer 210a-210f. However, only one other layer (layer 3210c) is fabricated to carry the signal beyond the via 230. Thus, as shown, any signal at the first signal node 220 will also be present at the protected node on layer 3210c. If the signal is a normal signal (i.e., not a high-current transient) then the signal does not propagate through the active region 245. However, if the signal is a high-current transient, then the signal does pass through the active region 245 to the current-shunt node 241. The high-current transient may then pass to the second via 231 and eventually to the second signal node 221. The second signal node 221 may typically be a circuit node capable of handling high-current transients, such as a ground terminal and the like. A specific example of a signal pin-to-ground ESD protection scheme is shown below in
Since different sections of each layer may be isolated during fabrication, layer 3210c and layer 4210d may also be fabricated for dual use. That is, in one section, an isolated signal path may be used to route a shunt-current path from a protected node, i.e. an active region 245. However, other sections of either layer may be used as a ground plane or a battery plane for routing these often used signals to many other points in the PCB 200. Thus, as shown in
Utilizing existing layers in a PCB 200 to realize an ESD protection scheme is advantageous for a number of reasons. For one, no additional layers need to be fabricated for the sole purpose of providing ESD protection. Furthermore, signal routing and signal paths become less complicated and intrusive as typically the ground plane (layer 4210d, for example) and the battery plane (layer 3, 210c, for example) are often prevalent throughout all areas of the PCB 200. As a result, the circuitry of the PCB becomes less complicated which results in less labor-intensive design and fabrication and smaller PCBs 200. Both of the advantages, in turn, result in cheaper PCB fabrication and design, as well. Depending on the particular routing of the ESD scheme, a more robust dissipation region may be realized within the PCB because of the nature of the semi-conductive dielectric material 212 and its proximity to several ground nodes. Finally, space and money is saved by not having any SMT devices required as part of an ESD protection scheme.
Using the example shown in
In the ESD protection device layer 315, there may be several active regions, such as active region 345, wherein layer 3310c and layer 4310d overlap. As described previously, an active region 345 may pass high-current transient signals but block low-level, steady state signals. Each active region 345 serves as an ESD protection device between a protected node 340, and a current-shunt node 341.
In the embodiment of
Further,
Similarly,
In the ESD protection device layer 415, there may be several active regions, such as active region 445, wherein layer 3410c and layer 4410d overlap. As described previously, an active region 445 may pass high-current, transient signals but block low-level, steady state signals. Each active region 445 serves as an ESD protection device between a protected node 440, and a current-shunt node 441.
In the embodiment of
Further,
Using a battery plane, a ground plane, and other signal nodes, virtually any two combinations of signal points in a PCB or electronic circuit in general may be encompassed in an ESD protection scheme to provide a shunt-current path through an active region. Providing a single routing path through an active region is referred to as a first stage ESD protection path. More elaborate ESD protection schemes may provide a second stage of ESD protection for several, if not all, possible signal node combinations as well.
In realizing a two-stage ESD protection scheme, and PCB, such as PCB 500, may include two ESD protection layers instead of one as was depicted previously. As can be seen, the PCB 500 in
The embodiment shown in
In another embodiment, the invention may be practiced in an IC having one or more ESD protection layers disposed therein during IC fabrication. Generally speaking, the above-described aspects of the invention with respect to a PCB, apply equally to an embodiment realized in an IC. One skilled in the art understands that an ESD protection scheme formed in accordance with the present invention may be realized in a PCB or an IC as several concepts apply equally to both implementations. As such, the PCB 500 of
Thus, similar to a PCB embodiment described, the IC 500 in
Either of these ESD protection layers 515 and 516 may be fabricated as part of the IC 500, although these layers 515 and 516 may not typically be located at the top and bottom of the die. Thus, during a fabrication process, a single ESD protection layer (for example, layer 515) may be fabricated during a final step in a fabrication process. Further, one skilled in the art understands that although
As briefly mentioned above,
The embodiment shown in
Similarly, the electronic system depicted in
Also similarly, the electronic system depicted in
Furthermore, additional ESD routing paths may be realized both on and off-board for additional electronic components (not shown). Although shown as off-board in
In one embodiment, a PCB having an ESD protection scheme according to various embodiments of the invention may be realized in a radio frequency (RF) PCB application. As such, various electronic components associated with an RF application may be protected by an ESD scheme such that excessive ESD signals are diverted away from sensitive electronic components in the RF electronic circuit. For example, an RF amplifier is particularly sensitive to high-level transients. Thus, an RF amplifier may be realized either on-board or electrically coupled with a PCB that includes a current-shunt path for diverting these potentially damaging ESD currents away from the RF amplifier. Other components that may be protected from ESD using a PCB having ESD protection scheme include front-end modules, duplexer filters, RF point filters, etc. Of course, virtually any application requiring protection from ESD signals may be implemented in conjunction with a PCB fabricated according to various embodiments of the invention.
In another embodiment, a PCB having an ESD protection scheme according to various embodiments of the invention may be realized in a millimeter-wave PCB application. As such, various electronic components associated with a millimeter-wave application may be protected by an ESD scheme such that excessive ESD signals are diverted away from sensitive electronic components in the millimeter-wave electronic circuit. For example, a monolithic microwave integrated circuit (MMIC) may be particularly sensitive to high-level transients. Thus, an MMIC may be realized either on-board or electrically coupled with a PCB that includes a current-shunt path for diverting these potentially damaging ESD currents away from the MMIC.
While the invention is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the invention to the specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the invention.
