Patent Application
20060118233
1. Field of the Invention
The subject invention relates to a system and method for forming high resolution electronic circuits on a substrate. In particular, the present invention directs itself to a processing system utilizing a source of radiant energy for the formation of a series of channels in a substrate. More particularly, the invention directs itself to a computer controlled system allowing a user to create a pre-defined series of channels in a substrate, the series having a user-selectable set of depths and dimensions.
Additionally, the present invention directs itself to a processing method including the steps of: forming at least one channel in a substrate with a focused energy beam, cleaning the substrate to remove residue from the channel-forming step, filling the channels with an electrically conductive paste, and heating the substrate in order to cure the electrically conductive paste. More particularly, the invention directs itself to a method of fabricating electronic circuits on a substrate where the channel-forming step allows for the creation of patterns for the electronic circuitry of variable size, shape, and depth on or in the substrate.
2. Prior Art
Methods for forming electronic circuitry on substrates are well-known in the art. In general, such prior art methods include a building process wherein thin layers of dielectric and electrically conductive material are sequentially formed on a base substrate using conventional semiconductor processing techniques. Dielectric layers are typically formed by the sequential steps of spin-coating the dielectric material, curing, pattern-etching with a plasma etch process to form via apertures, and filling the apertures through electroplating or sputtering. The metal layers are typically formed by sequential steps of sputtering a thin chromium layer (for adhesion to the dielectric layer), sputtering an initial copper layer over the chromium layer, defining the electrical traces by either additive or subtractive methods, and removing the excess copper and chromium between the electrical traces.
Typical additive methods use a thin initial copper layer (seed layer), then form a photo resist layer over the thin copper layer and pattern it to remove photo resist where the signal traces are to be located, and thereafter plate a much thicker copper layer into the photo resist pattern. Typical subtractive methods use a thick initial copper layer, then form a photo resist layer over the thick copper layer and pattern it in order to remove photo resist in areas where there are signal traces. Thereafter, exposed copper is etched away. The aforementioned building process involves numerous steps and is a relatively expensive procedure. A defect in the formation of one layer may ruin the entire substrate. Current trends in the industry are biased toward increasing the density of signal lines and vias. This, in turn, increases cost of the building process and further increases the chance of a defect occurring.
Planar conductor patterns on plastic or other substrate materials are often used for interconnection of electronic components. In particular, plastic flex circuits have found broad application in the interconnection of semiconductor chips and small passive electronic components in miniature electronic devices. Similar approaches are used in the packaging of semiconductor integrated circuits to redistribute electronic connections to comply with the requirements of particular applications. The applications also include medical devices for implantable sensors and associated drug delivery telemetry to sensors for Unmanned Aerial Vehicles (UAVs).
Plastic substrate materials offer the desirable characteristics of mechanical flexibility, low cost, and lightweight. However, nearly all plastic materials exhibit irreversible damage when subjected to processing temperatures above 400° C. As a consequence, conductor patterns on plastic substrates are normally produced by photolithographic patterning and etching of a metal film deposited at low temperatures over the entire substrate surface or by stencil printing of polymer-based conductive inks. Both of these approaches have significant drawbacks. Etching is a subtractive process that requires more than eight process steps, poorly utilizes conductor materials, and generates a waste stream of process chemicals. Stencil printing of polymers or other materials is limited in the spatial resolution of printed features and the corresponding density of conductive lines.
Pastes that can be applied to ceramic substrates by stenciling processes and that cure at temperatures in the range of 800° C. are well-known in the prior art. Due to their high curing temperatures, they are not applicable to polymer substrates. Recent advances in materials technology, however, now allow for production of metallic powders with well-controlled particulate dimensions in the micron range. Metallic precursor compounds that cure at low temperatures by decomposing to form metal species and volatile gases also have been identified. When mixed with appropriate solvents, surfactants, and adhesion promoters, these materials can be used to manufacture pastes that cure at temperatures of less than 250° C. to form high-quality electrical conductors.
It is a purpose of the subject invention to provide a method for creating electrical circuitry on a substrate which reduces manufacturing costs and defects and, thusly, enables board manufacturers to keep up with the demands of the semiconductor and circuitry industries.
Filling laser-drilled via holes with conductive pastes that can be cured at low temperatures provides an approach to electrical connection of the top and bottom surfaces of a substrate or between conductor arrays on different levels of a multi-substrate laminated stack. Since the same laser tool and filling process can be used for production of both channels and through holes, planar conductor arrays on the surface of the substrate and conductive vias through it can be fabricated in a single sequence of operations.
One such prior art method of forming electrical circuitry on a substrate is shown in U.S. Pat. No. 4,417,393. This reference is directed to a method of fabricating high density electronic circuits having very narrow conductors. Although this reference describes the use of standard thick film materials, the reference does not address the issue of thermal compatibility of the filler material and the substrate. The prior art includes several attempts to address the challenge of conductor or via fabrication on low-temperature substrates. Additionally, this reference describes the use of a laser to mill fine lines and holes in the substrate which are then filled with conductive materials to produce planar conductor arrays and vias. Although the reference describes the use of standard thick film materials, it does not address the issue of thermal compatibility of the filler material and the substrate.
U.S. Pat. No. 4,763,403 is directed to a method of making an electronic component. This reference teaches the use of conductive epoxy paste for the interconnection of conductor patterns.
U.S. Pat. No. 6,163,957 describes a similar technique for production of vias using laser-drilled holes in a substrate covered by an auxiliary film. In both of these references, the conductor pattern is formed through a photo-lithographic process. The reference directs itself to the creation of channels through direct application of radiant energy.
Another such prior art method of forming electrical circuitry on a substrate is shown in U.S. Pat. No. 5,666,722. This reference is directed to a method of manufacturing printed circuit boards. This system teaches the fabrication of planar conductor arrays through vapor or plasma deposition of metals onto a substrate containing laser cut channels followed by the abrasion of the substrate surface. This approach provides high spatial resolution and eliminates the use of photo-lithographic etching, but is wasteful of applied metallic material and may require additional processing steps to achieve desired conductor thickness.
U.S. Pat. No. 5,091,339 is directed to trenching techniques for forming vias and channels in multilayer electrical interconnects. This system teaches the use of channel and hole patterns formed by plasma or laser etching through multiple masks with subsequent filling by conductive materials. The system does not utilize the formation of channels formed through direct application of radiant energy to the substrate surface.
U.S. Pat. No. 4,912,844 describes the use of a punch to produce cavities and grooves in a suitable deformable substrate. This reference teaches the use of a punch tool in order to press cavities and grooves into deformable electrically insulating substrates laminated by metallic foil to produce cavities and grooves in the laminated surface. Removal of material on the unindented portion of the laminated substrate surface by mechanical or etching techniques then results in formation of a conductor array pattern. This approach is wasteful of conductive material and may be applied only to selected substrate materials.
Additionally, U.S. Pat. No. 4,336,320 teaches the filling of photolithographically defined channels with thick film conductor paste and U.S. Pat. No. 4,508,753 teaches the filling of a pattern engraved in an applied insulating coating with conductive paste to fabricate conductor patterns on high-temperature substrates.
The prior art includes several attempts to address the challenge of conductor or via fabrication on low-temperature substrates. U.S. Pat. No. 4,763,403 describes the use of conductive epoxy paste for interconnection of conductor patterns. U.S. Pat. No. 6,263,957 describes a similar technique for production of vias using laser-drilled holes in a substrate covered by an auxiliary film. In both of these references, the conductor pattern is formed through photolithographic processes. Additionally, U.S. Pat. No. 5,666,722 teaches the fabrication of planar conductor arrays by vapor or plasma deposition of metals onto a substrate containing laser cut channels followed by abrasion of the substrate surface. This approach provides high spatial resolution and eliminates the use of photolithographic etching, but it is wasteful of applied metallic material and may require additional process steps to achieve desired conductor thickness.
U.S. Pat. No. 5,091,339 describes the use of channel and hole patterns formed by plasma or laser etching through multiple masks with subsequent filling by conductive material. U.S. Pat. No. 4,912,844 describes use of a punch to produce cavities and grooves in a suitable deformable substrate and the provision of conductive material in the grooves to produce conductor arrays. This reference teaches the use of a punch tool to press cavities and grooves into deformable electrically insulating substrates laminated by metallic foil to produce cavities and grooves in the laminated surface. Further, the reference provides for the removal of material on the unindented portion of the laminated substrate surface by mechanical or etching techniques, resulting in the formation of a conductor array pattern. This approach is wasteful of conductive material, may be applied only to selected substrate materials, and requires fabrication of punching or embossing tools which are costly and subject to wear.
In the prior art, laser processing has been used to produce small via holes in plastic electronic substrates, as shown in U.S. Pat. No. 4,959,119. Electroplating of the inner surfaces of these holes is a low-temperature technique commonly used to provide an electrically conducting path or via between the two sides of the substrate. U.S. Pat. No. 5,422,190 has described use of thick film conductive pastes to fill via holes in electronic substrates that can be fired at temperatures exceeding 700° C., which are needed to cure these thick film pastes. However, substrates that are damaged by exposure to these temperatures cannot be used in combination with the thick film pastes, such as those described in U.S. Pat. No. 5,422,190.
None of the prior art provides for a combination of steps as herein presented comprising a method for forming electronic circuits on a substrate which allows for a maximum of efficiency and cost effectiveness with a minimum of defects. None of the prior art methods include the combined steps of laser milling an uncoated surface of a substrate to form a series of channels having user-defined depths and dimensions.
The present invention provides for a system and method for creating high resolution electronic circuits on a substrate. The method includes the steps of forming at least one channel in a substrate with a focused energy beam, cleaning the substrate to remove residue from the formation step, filling the channels with an electrically conductive paste, and heating the substrate in order to cure the electrically conductive paste. The system for implementing the method for creating high resolution electronic circuits on a substrate includes a source of radiant energy and a focusing means for directing a focused energy beam onto the surface of a substrate. The substrate is mounted on a translatable table, which allows for the formation of channels having user-defined depths and thicknesses.
It is a principle objective of the subject system and method of forming high resolution electronic circuits on a substrate to provide an efficient process for creating electrical circuitry on a substrate material.
It is a further objective of the subject system and method for forming high resolution electronic circuits on a substrate to provide a system and method where channels are formed in the substrate material having user-defined depths and thicknesses.
It is a further objective of the subject invention to provide a system and method of forming high resolution electronic circuits on a substrate where the electrically conductive material is heated in order to shape the material, increase the material's strength and remove impurities from the electrically conductive material.
It is an important objective of the present invention to provide a system and method for forming high resolution electronic circuits on a substrate which include user-defined and user-selectable depths and dimensions of the channels formed in the substrate by the focused energy beam.
Referring now to
The source of radiant energy 34 may be a laser, a source of noncoherent light, an electron beam generator, or any other suitable means for generating radiant energy. In the preferred embodiment of the invention, the source of radiant energy 34 is a diode-pumped, solid-state neodymium laser, such as a neodymium vanadate laser. In order to effectively ablate the surface of substrate 12, it is preferred that the output of the laser 34 be frequency-tripled or frequency-quadrupled in order to produce wavelengths shorter than 360 nm. The source of radiant energy 34 is utilized for the production of optical, or other focused energy for the ablation of channels or via patterns in substrate 12.
Substrate 12 may be a glass, a polyimide film, or any other suitable substrate composition. One such substrate composition which may be used for substrate layer 12 is a polyimide film known as KAPTON®, which is produced by DuPont High Performance Materials of Circleville, Ohio. KAPTON® polyimide films are dielectric films which retain their physical properties over a wide temperature range. They have been used in field applications where the environmental temperatures were as low as −269° C. and as high as 400° C. Polyimide materials are preferred for substrate 12 because polyimides exhibit high optical absorption in the wavelength range of frequency-converted laser emissions. Additionally, the substrate 12 may be formed from a dielectric material such as MICROLAM®, manufactured by W.L. Gore & Associates of Newark, Del. Further, the polymer materials used to form the substrate 12 may also be in the form of liquid crystal polymer.
The source of radiant energy 34 generates an unfocused energy beam 14 which, as shown in
In order to achieve high processing speeds, the source of radiant energy 34 should be capable of producing several watts of average power at pulse repetition rates greater than 50 kHz. Focusing means 16 is employed for rapid and precision controlled movement of the point at which the focused or imaged laser beam 18 impinges on the surface of substrate 12. The radiation generated by the radiant energy source 34 is normally operated in a q-switched pulse mode.
Unfocused energy beam 14 is reflected from mirror 28 to second mirror 28′. Second mirror 28′ is, similarly, driven by a galvanometer scanner 30′ in order to properly direct the beam. The unfocused energy beam is then reflected from second mirror 28′ through optical lens 26. Lens 26 is preferably an “F-theta” or telecentric objective lens. The optical lens 26 illustrated in
Once the energy beam passes through lens 26, the focused energy beam 18 then impinges upon the surface of substrate 12. Mirrors 28 and 28′, and their respective drive means 30 and 30′ are utilized in order to scan the focused energy beam 18 across the surface of substrate 12 along a pre-selected path.
A computer control means (not shown) may be in electrical communication with the drive means 30 and 30′ in order to allow a user to selectively enter a beam path. The control means may be either set automatically, for creating a set of desired paths, or the system may be operated manually.
As shown in
The computer control means may also be in electrical communication with the translation stage 36 in order to control the translation of the substrate 12. Control of translation stage 36 may either follow pre-set patterns or be manually operated by the user.
Operation of laser 34 at power levels high enough to produce ablation or vaporization of the substrate material while the focused energy beam 18 is rapidly scanned across the surface of substrate 12 provides a means for fabrication of patterns of channels and holes of controlled depth in substrate 12. Each laser pulse 18 removes a layer of material of less than a few microns thickness from the illuminated region of the substrate 12. The depth and shape of ablated channel and hole structures may thereby be defined by controlling the number of pulses delivered to each illuminated region as beam 18 is scanned over it.
It has been found that laser beams with a Gaussian or near-Gaussian intensity profile yield groove bottoms and sidewalls having optimal smoothness. Consistent, smooth conductor surfaces are particularly desirable for high-frequency (>400 MHz) applications.
The depth and shape of the ablated channel and hole structures is defined by controlling the number of pulses, and the pulse rate, delivered to each illuminated region as the beam is scanned over it. Use of the scanned laser beam, rather than laser projection of a fixed mask pattern onto the substrate, allows the channel and hole patterns to be easily changed by modification of the system control software. With computer control, the pulsed output of the laser is synchronized with the motion of the translation stages and galvanometer system to achieve uniform overlap of laser pulses and smooth surfaces of ablated features.
In an alternative embodiment, a circular aperture (not shown) may be added to focusing means 16. It has been found that clipping the lower intensity “wings” of the energy beam by means of a circular aperture sized to transmit roughly 80% of the beam's energy offers a good compromise between smooth machined surfaces and sharper line definition.
The path of the laser beam 18 may be determined and optimized using a CAD, or similar, program before downloading the sequence into the galvanometer scanners 30 and 30′. Laser pulsing is carefully synchronized with the beam motion in order to permit consistent depth control. Unintended overlapping of pulses, dwell during acceleration and deceleration of the beam, overshooting and undershooting of the beam, and other inaccuracies can result in unacceptable variation in channel depth. The step of laser ablation is preferably accomplished using a laser operating at wavelengths shorter than 400 nm. Preferably, the laser is a frequency-converted solid state laser.
Following laser patterning, the substrate 12 is cleaned in order to remove any residue or debris left over from the ablation and vaporization of substrate material. The cleaning of the laser ablation debris from substrate 12 may be performed by sonication in a liquid. Where cleaning is performed by sonication in a liquid, the cleaning process is followed by drying the substrate 12 in an oven to remove the remaining liquid.
The channels 20 are then filled with a low-temperature electrically conductive paste material. One such suitable material is PARMOD® PRA-311 silver paste, made by Parelec, Inc. of Rocky Hill, N.J. PARMOD® silver pastes and inks are disclosed in U.S. Pat. Nos. 5,882,722; 6,036,889; 6,143,356; and, 6,379,745.
The material used to fill channels 20 may be an electrically conductive paste or slurry material. The electrically conductive paste or slurry material 24, in the preferred embodiment, is formed of metallic particles and metallic precursor compounds. In the preferred embodiment, the metallic particles each have an average diameter of 5 micrometers and the metallic precursor compounds are chosen to include materials which convert to solid-phase electrically conductive materials at temperatures of less than 350° C. Further, the conductive filler material may include liquid solvents. The liquid solvents may, preferably, include dipropylene glycol methyl ether added at a 1.1 weight percentage. Additionally, the conductive filler material may include compounds promoting adhesion of the solid phase conductive material, produced in the final heating stage of the substrate to convert the conductive paste filler material to a solid phase conductive material, to the substrate 12. These adhesion-promoting compounds may be diamines.
The physical characteristics and chemical composition of conductive pastes used to fill the laser-produced channels and holes strongly influence the degree to which the cured conductive material allows for low curing temperatures, low conductor resistivity, line widths and feature sizes on a small scale, strong adhesion between the conductive materials and the polymer substrate, solderability, and the production of smooth conductor surfaces for efficient high frequency performance. In order to determine a suitable conductive paste material, several experiments were performed utilizing different conductive materials.
Test patterns were fabricated for these experimental tests using a 355 nm pulsed laser to produce arrays of channels having widths ranging between 15 microns and 1000 microns, formed in polyimide substrates. Channel patterns were filled with candidate conductive paste materials, cured at elevated temperatures, and evaluated for electrical conductivity, mechanical adhesion, and shrinkage. Because desired feature sizes are typically in the micron range, dimensions of the particulates in the conductive pastes were limited to less than or equal to 5 micron average particle size. Results of the experiments performed with various candidate materials are summarized in the examples below:
Experiment 1:
The first material tested was a silver thick film formulated for use on ceramic substrates. Channels in several test polymer substrates were filled with the silver thick film using a doctor blade technique. A number of test substrates were baked in an oven at temperatures between 200° C. and 300° C. for twenty minutes in order to explore the curing temperature of the material. Electrical conductivity measurements were taken of the test substrates. These tests demonstrated that the material did not become significantly conductive at temperatures below 300° C.
Experiment 2:
The second material tested was composed of silver flake and silver neodecanoate in neodecanoic acid with a 6 to 1 ratio of silver flake to silver neodecanoate. Channels in several test substrates were filled with the second material using a doctor blade technique. After heating the substrate to 95° C. for one minute in a soft bake cycle, any material remaining on the flat portion of the substrate surface was removed by abrasion. Test substrates were then baked at temperatures between 150° C. and 300° C. for twenty minutes in order to explore the curing temperature of the material. These tests demonstrated that the material became conductive at a cure temperature of approximately 200° C. and exhibited resistivity of approximately six times that of bulk silver. However, it was observed that the cured conductors exhibited a large amount of shrinkage and poor adhesion to the polyimide substrate.
Experiment 3:
The third material tested was similar to the second material, however, dipropylene glycol methyl ether was added at a 1.1 weight percent. Channels in several test substrates were filled with the material using a doctor blade technique. After heating the substrate to 95° C. for one minute in a soft bake cycle, any material remaining on the flat portion of the substrate surface was removed by abrasion. Test substrates were then baked at temperatures between 150° C. and 300° C. for twenty minutes in order to explore the curing temperature of the material. These tests demonstrated that the material became conductive at a cure temperature of approximately 150° C. and exhibited resistivity of approximately six times that of bulk silver. Adhesion of the conductive material to the substrate was greatly improved with respect to the second material, and the conductor pattern adhered well to the substrate. Solderability of the material, using SnPb solder, was found to be unacceptable for semi-conductor device applications.
Experiment 4:
A fourth material, formed of Parmod® silver ink PRA-311, was utilized. This material is similar to the third material, but with the addition of diamine adhesion-promoting compounds. Channels in several test substrates were filled with the material using a doctor blade technique. After heating the substrate to 95° C. for one minute in a soft bake cycle, any material remaining on the flat portion of the substrate surface was removed by abrasion. Test substrates were then baked at temperatures between 150° C. and 300° C. for twenty minutes to explore the curing temperature of the material. These tests demonstrated that the material became conductive at a cure temperature of approximately 150° C. and exhibited resistivity of approximately six times that of bulk silver. The conductor pattern adhered well to the substrate. The solderability of the material, using SnPb solder was found to be unacceptable, but acceptable solderability was demonstrated using SnPbAg solder.
Technical and economic viability of the system is influenced by the emission characteristics of the laser used for channel ablation and the manner in which the laser emission is delivered to the substrate surface. Lasers operating at ultraviolet wavelengths are desirable, since ultraviolet beams can be focused to sizes compatible with fabrication of micron-scale features, and ultraviolet radiation is strongly absorbed by many substrate materials. Operation of the ultraviolet laser source in a pulsed mode with sub-microsecond pulse duration produces clean vaporization of substrate material illuminated by the laser pulse with minimal damage to surrounding regions. The depth of substrate material removed by a single laser pulse is a function of the optical energy density in the illuminated region and typically is on the order of 0.2-0.7 microns. Channels can be produced by overlapping sequential laser pulses on the substrate surface. The depth and surface roughness of such channels is largely a function of the optical energy density at the substrate and the spatial offset of sequential pulses.
The volumetric rate of material removal is roughly proportional to the average optical power delivered to the substrate surface. This rate establishes the throughput of the surface patterning operation. Since high-power lasers typically generate optical power at lower cost, effective use of a high power laser source tends to increase throughput and reduce the cost of components produced by the system. Consequently, commercial viability of the system is influenced by the ability to utilize a high-power laser source. This requires that provisions be made for very high pulse repetition rate operation of the laser and for very high speed, extremely precise relative motion between the laser beam and the substrate.
Using the fourth material (Experiment 4) and a computer-controlled high-speed laser ablation system comprising a 3 Watt, 355 nm frequency-converted Nd:YAG laser, galvanometer-driven beam scanning mirrors, and high-speed stages equipped with a vacuum chuck for mounting planar organic substrates, 3.7 cm×3.7 cm chip-scale packages were fabricated, which were characterized by a top layer containing 1038 solder bump pads, 600 traces of 15-micron width, and total length of 5564 mm, and 819 (40 micron) vias, and by a bottom layer containing 670 (650 micron diameter) solder pads, and 160 traces of 15 micron width and 464 mm total length.
After laser ablation of feature patterns, the substrate was cleaned by sonication in a mild detergent. The top side of the circuit was then filled with Parmod® PRA-311 using a doctor-blade technique and the circuit was soft baked at 95° C. for one minute. After the first soft bake, the doctor-blade technique was used to refill the ablated features on the top side to compensate for shrinkage of the PRA-311 material, and the substrate was again soft baked at 95° C. for one minute. Excess material was then removed from the top surface of the substrate by lapping with a dry abrasive, and the substrate was baked at 150° for twenty minutes.
After filling of the top side of the substrate, the bottom side was filled by a similar method. Adhesion of the conductor pattern to the substrate was tested by applying adhesive tape to the metallized substrate and then pulling the tape away. Metal traces were found to be intact after this test. About 20% of the substrate area was covered with metal, suggesting that alternative photolithographic techniques for defining conducting traces and pads would have utilized approximately five times as much metal for full coverage of the surface and etched away 80% of that in the process of trace and pad definition.
The channels or holes may be filled with a silver conductive paste material including silver flake and silver necadecanoate in neodecanoic acid with a 6 to 1 ratio of silver flake to silver neodecanoate.
The heating and curing of the electrically conductive paste 24 acts to not only cure the material, but shape the conductive paste 24, increase the material's strength and remove impurities from the electrically conductive paste 24. The substrate 12 and electrically conductive paste or slurry 24 are heated to a temperature of less than 250° C., in the preferred embodiment, in order to convert the conductive paste or slurry filler material 24 to solid-phase electrically conductive material. In an alternative embodiment, the substrate may be baked at temperatures less than 100° C. for a period of 1 to 30 minutes. The steps of filling the channels and soft baking of the substrate are sequentially repeated until the channels or holes are completely filled. Excess conductive filler material is then removed from the upper surface of the substrate and the substrate is heated, once again, to temperatures of less than 250° C. in order to convert the conductive paste filler material into a solid phase conductive material.
Although this invention has been described in connection with specific forms and embodiments thereof, it will be appreciated that various modifications other than those discussed above may be resorted to without departing from the spirit or scope of the invention. For example, functionally equivalent elements may be substituted for those specifically shown and described, proportional quantities of the elements shown and described may be varied, and in the formation method steps described, particular steps may be reversed or interposed, all without departing from the spirit or scope of the invention as defined in the appended Claims.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10612904 | Jul 2003 | US |
| Child | 11325519 | Jan 2006 | US |
