The present invention relates generally to semiconductor manufacturing and, more particularly, to fabrication of memory devices.
Conventional semiconductor flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) devices include arrays of cells that can be independently programmed and read. The size of each cell and thereby the memory device are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, a group of the cells must be erased together as a block.
Flash memory devices of this type may include individual memory cells characterized by a vertical stack of a tunnel oxide (e.g., SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate, and a control gate over the interlayer dielectric. The vertical stack may be formed on a crystalline silicon substrate. The substrate may include a channel region positioned below the vertical stack and source and drain on opposing sides of the channel region. Various voltages may be applied to the cell elements to program the cell with a binary 1 or 0, to erase all or some of the cells as a block, to read the cell, to verify that the cell is erased, or to verify that the cell is not over-erased.
Another type of memory cell structure is characterized by a vertical stack that includes an insulating tunnel oxide layer, a charge trapping nitride layer, an insulating top oxide layer, and a polysilicon control gate, all positioned on top of a crystalline silicon substrate. This particular structure of a silicon channel region, tunnel oxide, nitride, top oxide, and polysilicon control gate is often referred to as a SONOS (silicon-oxide-nitride-oxide-silicon) device.
Memory cells in a flash memory device are typically connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in a column being connected to a respective bit line. To operate efficiently and reliably, each cell must be effectively isolated from neighboring cells.
As the dimensions of such memory devices have shrunk, isolation techniques have transitioned from conventional local oxidation of silicon (“LOCOS”) isolation techniques to shallow trench isolation (“STI”). In fabricating an STI structure, a trench is created in the substrate between active regions of neighboring cells. The trench is filled with a field oxide (FOX) material which isolates neighboring cells from each other. Unfortunately, conventional STI fabrication techniques fail to provide suitably efficient and reliable isolation.
Accordingly, there is a need for an improved STI structure and fabrication technique for optimizing performance of flash memory devices.
In an implementation consistent with the principles of the invention, a method for forming a memory device is provided. The method includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
In another implementation consistent with the principles of the invention, a method is provided for fabricating a semiconductor device. The method includes: forming a first dielectric layer over a substrate; forming a second dielectric layer over the first dielectric layer; forming an anti-reflective dielectric layer over the first dielectric layer; forming a photoresist layer over the anti-reflective dielectric layer; patterning the photoresist layer to define mask regions; etching the anti-reflective dielectric layer and the second dielectric layer to form a hard mask; etching the substrate and the first dielectric layer to form at least one isolation trench in portions of the substrate not covered by the hard mask; filling the trench with an oxide material; stripping the anti-reflective dielectric layer from the semiconductor device; stripping the second dielectric layer from the memory device; forming at least one charge storage element over the oxide material and the first dielectric layer; forming an inter-gate dielectric layer over the at least one charge storage element; and forming at least one control gate over at least a portion of the inter-gate dielectric layer.
In yet another implementation consistent with the principles of the invention, a method is provided for fabricating a memory device. The method includes forming an oxide layer over a substrate. A nitride layer is formed over the oxide layer. An anti-reflective silicon oxynitride layer is formed over the nitride layer. The anti-reflective silicon oxynitride layer and the nitride layer are patterned and etched to form a mask. The oxide layer and the substrate are etched using the mask to form at least one isolation trench. A field oxide material is formed in the at least one isolation trench. The anti-reflective silicon oxynitride layer is removed using dry plasma etching. The nitride layer is removed using wet phosphoric acid etching. At least one charge storage element is formed over the oxide layer and the field oxide material. The field oxide material is recessed to a predetermined depth using the at least one charge storage element as a mask. An inter-gate dielectric layer is formed over the at least one charge storage element and the recessed field oxide material. At least one control gate is formed over the inter-gate dielectric layer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, explain the invention. In the drawings,
The following detailed description of implementations consistent with the principles of the invention refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements. Also, the following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims and their equivalents.
Implementations consistent with the present invention provide non-volatile memory devices with improved lithographic spacing, such as flash electrically erasable programmable read only memory (EEPROM) devices.
Assuming that there are n columns and m rows in EEPROM 100, the bit lines may be designated as BL0 to BLn and the word lines may be designated as WL0 to WLm. Accordingly, there may be n+1 bit lines and m+1 word lines. Bit line driver 104 applies appropriate voltages to the bit lines. Similarly, appropriate voltages are applied to the word lines by word line driver 106. The voltages applied to drivers 104 and 106 may be generated by a power source 108 under the control of a controller 110, which may include on-chip logic circuitry. The controller 110 may also control the drivers 104 and 106 to address the memory cells individually or collectively.
A memory cell 102 is located at each junction of a word line and a bit line. Each cell 102 includes a Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) having a source and drain formed in a semiconductor substrate, a floating gate, and a control gate separated from the floating gate by an oxide-nitride-oxide (ONO) stack. Additional details regarding the formation of cell 102 will be described below in relation to
Cells 102 illustrated in
With reference to
Layer 320 may be a dielectric layer formed on layer 310 in a conventional manner. In an exemplary implementation, dielectric layer 320 may include an oxide, such as a silicon oxide (e.g., SiO2), and may have a thickness ranging from about 50 Å to about 350 Å. Dielectric layer 320 may function as a tunnel oxide layer for a subsequently formed memory cell of semiconductor device 300. In one implementation consistent with principles of the invention, a suitable method for forming layer 320 may be a thermal oxidation process of layer 310 at a temperature of about 750° C. to 1100° C. Alternatively, dielectric layer 320 may be deposited using a low pressure chemical vapor deposition (LPCVD) process performed at a temperature of about 400° C. to 800° C. In addition, an optional nitride layer (not shown) may be formed on layer 320.
A hard mask 410 may be formed over layer 320 (act 205-210). In one exemplary implementation, hard mask 410 may incorporate two distinct layers, an initial mask layer 420 (act 205) and a second, anti-reflective coating (ARC) layer 430 formed above mask layer 420 (act 210). By providing anti-reflective coating layer 430 beneath a photoresist material prior to formation of the mask 410, optical reflections of the radiation used to develop the mask pattern may be minimized. By using ARC layer 430, more precise lithography may be applied, resulting in narrower mask spacings. In one embodiment, mask layer 420 may be formed of a dielectric, such as silicon nitride (e.g., Si3N4), and may have a thickness ranging from about 800 Å to about 1700 Å. Additionally, in one exemplary implementation, ARC mask layer 430 may be formed of silicon oxynitride (e.g., SiON), and may have a thickness ranging from about 300 Å to about 700 Å.
A photoresist material formed over mask layers 420 and 430 may be patterned and etched in a conventional manner to form hard mask 410 on the top surface of layer 320, as illustrated in
Semiconductor device 300 may then be etched, as illustrated in
Following trench and FOX layer formation, semiconductor device 300 may then be etched, as illustrated in
In an alternative embodiment, an Ar/O2/CH3F etch chemistry may be used to perform the plasma etching. For example, to etch SiON ARC mask layer 430 having a thickness ranging from about 300 Å to 700 Å, Ar may be provided at a flow rate ranging from about 100 sccm to about 400 sccm, O2 may be provided at a flow rate ranging from about 40 sccm to about 150 sccm and CH3F may be provided at a flow rate ranging from about 10 sccm to about 60 sccm. In addition, the RF power source for the plasma etching chamber may be set to provide power ranging from about 100 to about 500 watts and a bias voltage ranging from about 100 to about 300 volts may be applied to the semiconductor device 300.
It should be understood that the particular etch chemistry, flow rates, RF power, wafer bias voltage, etching duration and other parameters may be optimized based on the particular semiconductor device being etched, the particular plasma etching chamber used and the guidance disclosed herein.
Semiconductor device 300 may then be etched, as illustrated in
A layer 1010 may be formed on layer 320 and field oxide layer 610 in a conventional manner and may include a conductive material, such as polysilicon or a dielectric material, such as silicon nitride, as shown in
A planarization process may then be performed to remove a predetermined amount of excess material from layer 1010 and FOX layer 610, as illustrated in
Following planarization, FOX layer 610 may be etched to a predetermined depth using floating gates 1110, 1120, and 1130 as the etching masks, as illustrated in
Referring to
The foregoing description of exemplary embodiments of the invention provides illustration and description, but is not intended to be exhaustive or to limit the invention to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. For example, in the above descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, implementations consistent with the invention can be practiced without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the present invention. In practicing the present invention, conventional deposition, photolithographic and etching techniques may be employed, and hence, the details of such techniques have not been set forth herein in detail.
While a series of acts has been described with regard to
No element, act, or instruction used in the description of the present application should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise.
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