Patent Application
20160093567
This disclosure relates generally to interconnections in a semiconductor substrate, and more specifically, but not exclusively, to interconnections in a cavity of a semiconductor substrate.
Conventionally, semiconductor packages include a semiconductor die and a substrate with routing or conductive paths for the die extending through the substrate. Having a cavity in the substrate is beneficial in that it reduces the vertical profile or height of the package when the die is located in the cavity. However, locating a die in the cavity provides challenges for creating the routing or conductive paths because the substrate surface is no longer even and easy to uniformly pattern and layer for creating the conductive paths. Therefore, conductive paths are generally added by additional manufacturing steps on the surface of the bottom of the cavity only. This adds steps to the manufacturing process and limits the area where conductive paths are created—namely the cavity region.
Accordingly, there are industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.
The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.
The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.
Some examples of the disclosure are directed to systems, apparatus, and methods for a semiconductor substrate include a substrate having a top side, a bottom side opposite the top side, a cavity in the top side of the substrate, a first side portion horizontally adjacent the cavity, and a second side portion horizontally adjacent the cavity opposite from the first side portion; a plurality of cavity interconnections located in a bottom surface of the cavity, the plurality of cavity interconnections providing a conductive path between the cavity and the bottom side; a plurality of first side interconnections located in the first side portion and extending from the top side of the substrate to the bottom side of the substrate; and a plurality of second side interconnections located in the second side portion and extending from the top side of the substrate to the bottom side of the substrate.
In some examples of the disclosure, the system, apparatus, and method includes applying a seed layer to a carrier; applying a first removable layer on a surface of the seed layer; patterning the first removable layer to create a cavity region, a plurality of first side interconnect regions horizontally adjacent to the cavity region, and a plurality of second side interconnect regions horizontally adjacent to the cavity region on an opposite side from the plurality of second side interconnect regions; applying an first electrically conductive material in the cavity region, the plurality of first side interconnect regions, and the plurality of second side interconnect regions; applying an electrically conductive etch stop layer on the first electrically conductive material; applying a second removable layer on the electrically conductive etch stop layer and the patterned first removable layer; patterning the second removable layer to form a plurality of cavity interconnect regions and to continue to form the plurality of first side interconnect regions and the plurality of second side interconnect regions; applying a second electrically conductive material in the plurality of cavity interconnect regions, the plurality of first side interconnect regions, and the plurality of second side interconnect regions; removing the first removable layer and the second removable layer; applying a dielectric layer on a surface of the second electrically conductive material; removing the seed layer and the carrier to expose the cavity region; and removing the first electrically conductive material from the cavity region.
Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.
The accompanying drawings are presented to describe examples of the present teachings, and are not limiting. The accompanying drawings are presented to aid in the description of examples of the disclosure and are provided solely for illustration of the examples and not limitation thereof.
In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.
Methods, apparatus and systems for semiconductor substrate interconnections are provided. The exemplary methods, apparatus, and systems disclosed herein advantageously address the industry needs, as well as other previously unidentified needs, and mitigate shortcomings of the conventional methods, apparatus, and systems. For example, a semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.
Various aspects are disclosed in the following description and related drawings to show specific examples relating to the disclosure. Alternate examples will be apparent to those skilled in the pertinent art upon reading this disclosure, and may be constructed and practiced without departing from the scope or spirit of the disclosure. Additionally, well-known elements will not be described in detail or may be omitted so as to not obscure the relevant details of the aspects and examples disclosed herein.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any details described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples. Likewise, the term “examples” does not require that all examples include the discussed feature, advantage or mode of operation. Use of the terms “in one example,” “an example,” “in one feature,” and/or “a feature” in this specification does not necessarily refer to the same feature and/or example. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of examples of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should be noted that the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element. Coupling and/or connection between the elements can be physical, logical, or a combination thereof. As employed herein, elements can be “connected” or “coupled” together, for example, by using one or more wires, cables, and/or printed electrical connections, as well as by using electromagnetic energy. The electromagnetic energy can have wavelengths in the radio frequency region, the microwave region and/or the optical (both visible and invisible) region. These are several non-limiting and non-exhaustive examples.
Any reference herein to an element using a designation such as “first,” “second,” and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must necessarily precede the second element. Also, unless stated otherwise, a set of elements can comprise one or more elements. In addition, terminology of the form “at least one of: A, B, or C” used in the description or the claims can be interpreted as “A or B or C or any combination of these elements.”
The examples described below may be incorporated into a mobile device. The term “mobile device” can describe, and is not limited to, a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, a wireless modem, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). Further, the terms “user equipment” (UE), “mobile terminal,” “mobile device,” and “wireless device,” can be interchangeable.
The semiconductor substrate 100 may include a cavity 110, a plurality of cavity interconnections 120 in the cavity 110, a third side region 130, and a fourth side region 140. The cavity 110 is horizontally centered in the first substrate layer 101 on a top or first side of substrate 100. While the cavity 110 is shown horizontally centered in the substrate 100, it should be understood that the cavity 110 may be offset from the center of the substrate 100. While the cavity 110 is shown extending from the top or first side of substrate 100 into the first substrate layer 101, is should be understood that the cavity 110 can extend beyond the first substrate layer including extending into the third substrate layer 103.
The plurality of cavity interconnections 120 may be embedded in a bottom surface of the cavity 110 such that each of the plurality of cavity interconnections 120 is recessed or below a horizontal plane of the bottom surface of the cavity 110. The plurality of cavity interconnections 120 may be vertically below the bottom surface of the cavity 110 at various depths but preferably between 1 and 4 microns deep. The plurality of cavity interconnections 120 may provide a conductive path within the substrate 100 between each of the plurality of cavity interconnections 120 as well as between the plurality of cavity interconnections 120 and both the third side region 130 and the fourth side region 140.
The third side region 130 is horizontally adjacent to the cavity 110 on a left side of the cavity 110 and the fourth side region 140 is horizontally adjacent to the cavity 110 on a right side of the cavity 110 opposite the third side region 130. The third side region 130 and the fourth side region 140 extend from the top or first side of substrate 100 to the bottom or second side of substrate 100. The third side region may include a plurality of third side interconnections 131 extending from the top or first side of the substrate 100 to the bottom or second side of the substrate 100. Each of the plurality of third side interconnections 131 may include an electrically conductive stop etch layer 132 located within the first substrate layer 101 in the same horizontal plane as the bottom of the cavity 110 (horizontally above a surface of the plurality of cavity interconnections 120). The plurality of third side interconnections 131 may provide a conductive path from the top or first side of the substrate 100 to the bottom or second side of the substrate 100 as well as to the plurality of cavity interconnections 120 and, thorough the plurality of cavity interconnections 120, to a plurality of fourth side interconnections 141.
The fourth side region 140 may include a plurality of fourth side interconnections 141 extending from the top or first side of the substrate 100 to the bottom or second side of the substrate 100. Each of the plurality of fourth side interconnections 111 may include an electrically conductive stop etch layer 142 located within the first substrate layer 101 in the same horizontal plane as the bottom of the cavity 110 (horizontally above a surface of the plurality of cavity interconnections 120). The plurality of fourth side interconnections 141 may provide a conductive path from the top or first side of the substrate 100 to the bottom or second side of the substrate 100 as well as to the plurality of cavity interconnections 120 and, thorough the plurality of cavity interconnections 120, to the plurality of third side interconnections 131.
The semiconductor substrate 200 may include a cavity 210, a plurality of cavity interconnections 220 in the cavity 210, a third side region 230, a fourth side region 240, and a semiconductor die 250. The cavity 210 is horizontally centered in the first substrate layer 201 on a top or first side of substrate 200. While the cavity 210 is shown horizontally centered in the substrate 200, it should be understood that the cavity 210 may be offset from the center of the substrate 200. While the cavity 210 is shown extending from the top or first side of substrate 200 into the first substrate layer 201, is should be understood that the cavity 210 can extend beyond the first substrate layer including extending into the third substrate layer 203.
The plurality of cavity interconnections 220 may be embedded in a bottom surface of the cavity 210 such that each of the plurality of cavity interconnections 220 is recessed or below a horizontal plane of the bottom surface of the cavity 210. The plurality of cavity interconnections 220 may be vertically below the bottom surface of the cavity 210 at various depths but preferably between 1 and 4 microns deep. The plurality of cavity interconnections 220 may provide a conductive path within the substrate 200 between each of the plurality of cavity interconnections 220 as well as between the plurality of cavity interconnections 220 and both the third side region 230 and the fourth side region 240.
The third side region 230 is horizontally adjacent to the cavity 210 on a left side of the cavity 210 and the fourth side region 240 is horizontally adjacent to the cavity 210 on a right side of the cavity 210 opposite the third side region 230. The third side region 230 and the fourth side region 240 extend from the top or first side of substrate 200 to the bottom or second side of substrate 200. The third side region may include a plurality of third side interconnections 231 extending from the top or first side of the substrate 200 to the bottom or second side of the substrate 200. Each of the plurality of third side interconnections 231 may include an electrically conductive stop etch layer 232 located within the first substrate layer 201 in the same horizontal plane as the bottom of the cavity 210 (horizontally above a surface of the plurality of cavity interconnections 220). The plurality of third side interconnections 231 may provide a conductive path from the top or first side of the substrate 200 to the bottom or second side of the substrate 200 as well as to the plurality of cavity interconnections 220 and, thorough the plurality of cavity interconnections 220, to a plurality of fourth side interconnections 241.
The fourth side region 240 may include a plurality of fourth side interconnections 241 extending from the top or first side of the substrate 200 to the bottom or second side of the substrate 200. Each of the plurality of fourth side interconnections 211 may include an electrically conductive stop etch layer 242 located within the first substrate layer 201 in the same horizontal plane as the bottom of the cavity 210 (horizontally above a surface of the plurality of cavity interconnections 220). The plurality of fourth side interconnections 241 may provide a conductive path from the top or first side of the substrate 200 to the bottom or second side of the substrate 200 as well as to the plurality of cavity interconnections 220 and, thorough the plurality of cavity interconnections 220, to the plurality of third side interconnections 231.
The semiconductor die 250 may be a number of different devices, such as a logic die or a memory die. The semiconductor die 250 may be centered within cavity 210 and include die connections 251 and underfill material 252. The die connections 251 couple the die 250 to the plurality of cavity interconnections 220. The substrate 200 may also include solder balls or connection points 205 that provide an external connection for the interconnections 220, 231, and 241 to other devices or components not shown, such as a printed circuit board.
The semiconductor substrate 300 may include a cavity 310, a plurality of cavity interconnections 320 in the cavity 310, a third side region 330, a fourth side region 340, a semiconductor die 350, and a capacitor 360. The cavity 310 is horizontally centered in the first substrate layer 301 on a top or first side of substrate 300. While the cavity 310 is shown horizontally centered in the substrate 300, it should be understood that the cavity 310 may be offset from the center of the substrate 300. While the cavity 310 is shown extending from the top or first side of substrate 300 into the first substrate layer 301, is should be understood that the cavity 310 can extend beyond the first substrate layer including extending into the third substrate layer 303.
The plurality of cavity interconnections 320 may be embedded in a bottom surface of the cavity 310 such that each of the plurality of cavity interconnections 320 is recessed or below a horizontal plane of the bottom surface of the cavity 310. The plurality of cavity interconnections 320 may be vertically below the bottom surface of the cavity 310 at various depths but preferably between 1 and 4 microns deep. The plurality of cavity interconnections 320 may provide a conductive path within the substrate 300 between each of the plurality of cavity interconnections 320 as well as between the plurality of cavity interconnections 320 and both the third side region 330 and the fourth side region 340.
The third side region 330 is horizontally adjacent to the cavity 310 on a left side of the cavity 310 and the fourth side region 340 is horizontally adjacent to the cavity 310 on a right side of the cavity 310 opposite the third side region 330. The third side region 330 and the fourth side region 340 extend from the top or first side of substrate 300 to the bottom or second side of substrate 300. The third side region may include a plurality of third side interconnections 331 extending from the top or first side of the substrate 300 to the bottom or second side of the substrate 300. Each of the plurality of third side interconnections 331 may include an electrically conductive stop etch layer 332 located within the first substrate layer 301 in the same horizontal plane as the bottom of the cavity 310 (horizontally above a surface of the plurality of cavity interconnections 320). The plurality of third side interconnections 331 may provide a conductive path from the top or first side of the substrate 300 to the bottom or second side of the substrate 300 as well as to the plurality of cavity interconnections 320 and, thorough the plurality of cavity interconnections 320, to a plurality of fourth side interconnections 341.
The fourth side region 340 may include a plurality of fourth side interconnections 341 extending from the top or first side of the substrate 300 to the bottom or second side of the substrate 300. Each of the plurality of fourth side interconnections 311 may include an electrically conductive stop etch layer 342 located within the first substrate layer 301 in the same horizontal plane as the bottom of the cavity 310 (horizontally above a surface of the plurality of cavity interconnections 320). The plurality of fourth side interconnections 341 may provide a conductive path from the top or first side of the substrate 300 to the bottom or second side of the substrate 300 as well as to the plurality of cavity interconnections 320 and, thorough the plurality of cavity interconnections 320, to the plurality of third side interconnections 331.
The semiconductor die 350 is shown at the bottom or second side of the substrate 300 while the capacitor 360 is shown on the top or first side of substrate 300 but these positions may be switched. The semiconductor die 350 may be a number of different devices, such as a logic die or a memory die. The semiconductor die 350 may be centered at the bottom or second side of substrate 300 and include die connections 351 and underfill material 352. The die connections 351 couple the die 350 to the plurality of cavity interconnections 320. The substrate 300 may also include solder balls or connection points 305 that provide an external connection for the interconnections 331 and 341 to other devices or components not shown, such as a printed circuit board. The capacitor 360 may be a number of different devices, such as a logic die, memory die, or an inductor. The capacitor 360 may be centered within the cavity 310.
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The following portion of the description will focus on only the semiconductor substrate 421, but it should be understood that the additional process flow may be applied to both semiconductor substrates 420 and 421. Next and as shown in
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Nothing stated or illustrated depicted in this application is intended to dedicate any component, step, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, step, feature, benefit, advantage, or the equivalent is recited in the claims.
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the examples disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
Although some aspects have been described in connection with a device, it goes without saying that these aspects also constitute a description of the corresponding method, and so a block or a component of a device should also be understood as a corresponding method step or as a feature of a method step. Analogously thereto, aspects described in connection with or as a method step also constitute a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps can be performed by a hardware apparatus (or using a hardware apparatus), such as, for example, a microprocessor, a programmable computer or an electronic circuit. In some examples, some or a plurality of the most important method steps can be performed by such an apparatus.
The examples described above merely constitute an illustration of the principles of the present disclosure. It goes without saying that modifications and variations of the arrangements and details described herein will become apparent to other persons skilled in the art. Therefore, it is intended that the disclosure be restricted only by the scope of protection of the appended patent claims, rather than by the specific details presented on the basis of the description and the explanation of the examples herein.
In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples require more features than are explicitly mentioned in the respective claim. Rather, the situation is such that inventive content may reside in fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that-although a dependent claim can refer in the claims to a specific combination with one or a plurality of claims—other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.
It should furthermore be noted that methods disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective steps or actions of this method.
Furthermore, in some examples, an individual step/action can be subdivided into a plurality of sub-steps or contain a plurality of sub-steps. Such sub-steps can be contained in the disclosure of the individual step and be part of the disclosure of the individual step.
While the foregoing disclosure shows illustrative examples of the disclosure, it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the examples of the disclosure described herein need not be performed in any particular order. Furthermore, although elements of the disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
