Patent Application
20250210600
System-on-chip (SoC) architectures can be used to integrate multiple electronic components into a single semiconductor device. Example SoC components include a processor core, graphics processor, memory, input/output interfaces, and the like. System-on-chip structures are typically formed on a semiconductor substrate using metal-oxide-semiconductor (MOS) technology and then singulated using a dicing operation to form individual chips or “die” that can be picked and packaged.
The accompanying drawings illustrate a number of exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.
Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the examples described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the example implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.
The present disclosure is generally directed to wafer dicing and more particularly to the processing of a semiconductor wafer to mitigate the creation of defects between adjacent die prior to or during dicing operations.
During formation or processing of a semiconductor wafer, individual integrated circuits (e.g., chips) are laterally offset from one another. The gap between adjacent chips may be referred to as a “dicing street” or “scribe line” along which the wafer can be cut to create a plurality of individual chips. A gap dielectric can be formed along the scribe line between neighboring chips to fill the space therebetween.
In accordance with some implementations, a protection layer can be formed over the chip sidewalls prior to forming the gap dielectric. The protection layer can itself be a defect free or a substantially defect free conformal layer that is configured to prevent the creation and propagation of cracks or other defects that can otherwise negatively impact the reliability and performance of the die and associated integrated circuits. In some instantiations, the protection layer can improve adhesion between the gap dielectric and a chip sidewall. The protection layer may be a high density layer. For instance, the density of the protection layer can be greater than the density of the gap dielectric.
The following will provide, with reference to
Referring to
The top and bottom gap dielectric layers 132, 134 can include any suitable dielectric material, such as silicon dioxide or silicon nitride, and can be formed using chemical vapor deposition (CVD), for example. The gap fill layers can be configured to fill the volume proximate to scribe line P between neighboring die.
Solder bumps 140 are formed over the bottom surface of each bottom die 124. The plurality of solder bumps 140 can be configured to form electrical interconnects with each stacked die 120 during downstream integration.
As shown, gap fill crack defects 150 can form at the interface between the gap fill layer and the adjacent die. Such cracks can undesirably propagate into the die, which can cause failure and disrupt performance.
Turning to
Referring to
As shown in
The protection layer 284 can be selectively removed from horizontal surfaces using an anisotropic etch. An anisotropic etch can include a dry etching process such as reactive ion etching. As shown in
A gap fill material, such as silicon dioxide or silicon nitride, is deposited over the structure of
Referring to
Referring to
Protection layers 282, 284 can inhibit crack initiation and form a barrier to crack propagation within inter-die gap 230. Although the illustrated SoC architecture is described in
Referring to
A system-on-chip architecture includes a substrate, first and second die disposed over a surface of the substrate and separated by an inter-die gap, a protection layer disposed over a sidewall of each of the first and second die, and a gap fill layer disposed over the protection layers and substantially filling the inter-die gap. In some implementations, the first and second die can have a stacked structure and the first and second die thicknesses can be substantially equal. One or both die can include a processor. The die can be arranged on the substrate to have an inter-die spacing of from approximately 50 micrometers to approximately 300 micrometers.
The protection layers can include a dielectric material, such as silicon dioxide, silicon nitride, titanium oxide, and aluminum oxide, and can have a thickness ranging from approximately 0.1 micrometers to approximately 20 micrometers. The thickness variability of each protection layer can be less than approximately 5%. As disclosed herein, the protection layers are respectively configured to inhibit crack formation in the first and second die. The gap fill layer can include a dielectric material, such as silicon dioxide and silicon nitride.
A further system-on-chip structure can include a carrier substrate, a die disposed over a surface of the substrate, a protection layer disposed over a sidewall of the die, and a gap fill layer disposed over the protection layer and over a surface of the carrier substrate proximate to the die. In various implementations, a density of the protection layer can be greater than a density of the gap fill layer.
A method of manufacture includes positioning a semiconductor die on carrier wafer, forming a protection layer over a sidewall of the semiconductor die, and forming a gap fill layer over the carrier wafer adjacent to the semiconductor die and over the protection layer. A method of forming the protection layer includes atomic layer deposition.
The term “layer,” as used herein, can generally refer to an over-formed sheet or thickness of material. A layer may be compositionally or structurally distinct from the material above or below it. Examples of a layer include, without limitation, a protection layer disposed over a sidewall of a chip and a gap layer disposed between adjacent chips.
On a semiconductor wafer having a plurality of processed die, a protection layer is formed over die sidewalls. The protection layer can include any suitable dielectric material and is configured to inhibit the formation and propagation of gap fill cracks. The protection layer can have a substantially uniform thickness, for example. Additionally, the protection layer can enable die stacking architecture flexibility.
While the foregoing disclosure sets forth various implementations using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and/or component described and/or illustrated herein can be implemented, individually and/or collectively, using a wide range of hardware, software, or firmware (or any combination thereof) configurations. In addition, any disclosure of components contained within other components should be considered example in nature since many other architectures can be implemented to achieve the same functionality.
The process parameters and sequence of steps described and/or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and/or described herein can be shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various example methods described and/or illustrated herein can also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.
While various implementations have been described and/or illustrated herein in the context of fully functional computing systems, one or more of these example implementations can be distributed as a program product in a variety of forms, regardless of the particular type of computer-readable media used to actually carry out the distribution. The implementations disclosed herein can also be implemented using modules that perform certain tasks. These modules can include script, batch, or other executable files that can be stored on a computer-readable storage medium or in a computing system. In some implementations, these modules can configure a computing system to perform one or more of the example implementations disclosed herein.
The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the example implementations disclosed herein. This example description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The implementations disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the present disclosure.
Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms “a” or “an,” as used in the specification and claims, are to be construed as meaning “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.”
