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The present invention relates to methods and apparatus for providing multi-functional operational modes to memory input/output (I/O) pins in an integrated circuit chip.
Integrated circuit memory devices are evolving in ever-greater complexity. As these memory devices evolve, often times the terminal pins that connect the memory device to the digital bus systems that carry their signals must change as well. This often results in memory devices that are not backward or forward compatible. The changes to the terminal pins also result in digital buses that are also not forward or backward compatible. Furthermore, IO pins often should be capable of supporting multiple standards, requiring multiple functionality of a pin. As memory devices evolve, there is a change of single ended, wide digital buses to narrow high-speed “serial like” bus attachments for memory devices. Some microprocessors have applicability in both areas (‘traditional’ buses and high-speed serial buses). Therefore, there exists a need for memory devices that can handle both I/O principles.
There exists a need for a memory device having terminal pins with multifunctional capability for allowing the memory device to be both backward and forward compatible. There also exists a need for a memory device that is operable with both dual inline memory modules (DIMMs) and fully buffered DIMMs. Therefore, a physical I/O circuit is needed that has a mode selection that can (1) act as power or ground; (2) act as a DDR2 or DDR3 (double data rate two or three) interface; (3) act as a high-speed differential receiver pin pair; and/or (4) act as a high-speed differential transmitter pin pair.
There also exists a need to provide a memory device that enables the mode selection to be carried out with fewer pins dedicated to that selection.
The embodiments disclosed herein provide an integrated circuit and system having one or multiple modes of operation. The integrated circuit comprises a pair of terminal input/output pins and a pair of T-coil circuits. Each pin is connected to a node of an individual T-coil circuit, wherein the individual T-coil circuit comprises a pair of serially connected coupled inductors and a bridging capacitor forming three nodes, wherein at least one node is connected to the terminal input/output pin, a middle tap is connected to a capacitive load, and a third node is connected to a resistive load. The capacitive load comprises an electrostatic discharge diode and a plurality of thick-oxide switches connecting at least one of a power or ground; a DDR2 or DDR3 data interface; and a high-speed differential receiver circuit. The resistive load comprises a plurality of thick-oxide switches connecting a high-speed differential driver, wherein the plurality of thick-oxide switches are used to select the mode of operation of the integrated circuit, and wherein the T-coil circuit is used to compensate parasitic capacitances that occur once the power, ground, or DDR2/DDR3 interface is disabled.
Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
a illustrates an exemplary embodiment of a multi-functional memory I/O pin having functionality of a DDR2 or DDR3 interface;
b illustrates an exemplary embodiment of a multi-functional memory I/O pin pair having functionality of a high-speed differential transmitter; and
c illustrates an exemplary embodiment of a multi-functional memory I/O pin pair having functionality of a high-speed differential receiver.
The detailed description explains the exemplary embodiments, together with advantages and features, by way of example with reference to the drawings.
Embodiments of the present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
One example of an integrated circuit according to the invention to be described with reference to the drawings is an integrated circuit for a memory input/output (I/O) pin having four different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. An exemplary embodiment of the invention provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter.
As shown in
In the exemplary embodiment the input return loss is small, while the transmission for the input pad to the capacitive pad also has low loss.
Z
in(f)=dv1/di1=RL
As can be seen from this formula the input impedance Zin equals the resistive load and is independent of frequency. The transfer impedance has two complex poles:
Here the transfer bandwidth is maximized with ζ=1/√{square root over (2)}. Therefore, the L1, L2, k and CB can be calculated by:
A key functionality of the circuit illustrated in
High-speed operations are different, however. Pins 110 and 115 can also be used as a high-speed differential driver (transmitter) while switches above and below driver section are closed and all other switches are open. Alternatively, pins 110 and 115 can be used as high-speed differential receiver, wherein switches above and in front of the receiver are closed and switches above and below the driver closed, while all other switches remain open. Therefore, in this mode, the transmitter circuit acts as termination impedance for the receiver. In the high-speed modes, the T-coil is used to tune the parasitic capacitances that come from the disabled low-speed circuits, thus allowing high-frequency operation despite the fact that low-speed circuits are attached to the critical nodes, such as pins 110 and 115.
In an exemplary embodiment, the multi-functional memory I/O pin effectively allows the memory device to have at least five modes of operation. Mode 1 is a high-impedance or not connected state. This occurs when all switches are set to open and the DDR interface is set to a high-impedance state. Mode 2 is a power or ground state. The respective switches in the power or ground pin block are closed. Mode 3 provides a DDR 2 or DDR 3 memory interface state. In this state, all switches are open and the DDR interface block is operational. Mode 4 operates as a high-speed differential driver state. In this implementation, all switches related to the power/ground 130, 135; DDR 2/3 interface 160, 165; and high-speed receiver logic 150 are closed. All switches to the high-speed SST logic 140 are open. Finally, Mode 5 operates as a high-speed differential receiver state. In this state all switches to the high-speed SST logic 140 are closed such that the high-speed SST logic 140 acts as termination impedance for the high-speed receiver logic 150. All switches related to the power/ground 130, 135 and DDR 2/3 interface 160, 165 are also closed.
In an exemplary embodiment (
In still another exemplary embodiment (
In another exemplary embodiment (
Therefore, in the exemplary embodiment, one pin pair allows several modes of operation in the memory device. The pin pair allows power/ground input, DDR2/3 interfaces and high-speed transmission or reception. Capacitive loading of high-speed nodes by low-speed functions is equalized by the T-coil circuit. Power minimization is also possible by enabling the use of low-voltage devices in high-speed modes of operation.
The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.
As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
The illustrations depicted herein are just examples. There may be many variations to these circuit diagrams or operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the exemplary embodiment of the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.