The present invention relates to systems and methods for high speed test probing of densely packaged semiconductor devices.
The methods and devices described herein are used to preserve signal integrity in a test environment for packaged semiconductor devices that accurately replicates the conditions that the device will experience in a designed application. To this end, the test fixture should provide the signal with transmission and termination characteristics that are predictable over the intended frequency range and match the performance specifications for the semiconductor part. The shielding performance of coaxial structures offers greatly improved crosstalk performance because the inter-probe coupling is substantially eliminated, being little more than that inherent in the device-under-test (DUT).
Simple testers that are used to verify the functionality of semiconductor components such as microprocessors Q and logic gate arrays generally make direct connection to the part and both inject and monitor voltages at connection points in a systematic manner. In general, the speed at which the tests are carried out can be increased until testing becomes unreliable and this frequency of operation set as the maximum test frequency. However, modern devices are designed to operate at very high speeds and unless the devices can be tested at their design operating speeds, any test quickly becomes inadequate and less representative of actual device capability. Typical a direct connection system can be used for a few hundreds of megahertz (MHz) providing the lengths of the connecting wires are kept short. Once the wire lengths approach fractions of a wavelength, then the operating conditions of the part under test become less certain because of impedance transformations that occur and phase shifts that are implicit in any time delays that are introduced.
By way of illustration, consider a part under test that is operating at a switching speed (clock speed, for example) of 30 MHz, this corresponds to a wavelength in free space of about 10 meters, and essentially the same in air. The time delay introduced when a wire is connected to link a signal from the device-under-test to a measuring appliance is in the neighborhood of about 1 nano-second per foot of wire, or about 33 pico-seconds per centimeter. So it can be seen that using short wires in the neighborhood of an inch or so (2.5 cm) introduces a time delay of close to 80 ps and corresponds to 2.5/1000, or 0.0025λ (a quarter of a percent of a wavelength). If the clock frequency is increased to 300 MHz, this same inch of wire represents 2.5 percent of a wavelength and at 3 GHz (now commonplace amongst high performance microprocessor parts) is a quarter of a wavelength, which can introduce disastrous errors into the measuring system; in this quarter wave case, a high impedance at one end of the connection, such as the input impedance of an amplifier, is transformed to a very low impedance close to a short circuit at the other end, where the device under test might be connected and conversely for a low impedance termination. Therefore high speed testing requires a sophisticated approach to connections for signals and a technical solution that is more complicated than has been used previously.
It is therefore apparent that an urgent need exists for testing methods and equipment that allows full performance evaluation conditions to be provided to the device under test. This improved test probe system enables realistic device assessment over the performance range specified by the device manufacturer without constraint due to the test equipment changing the working conditions of the device under test.
To achieve the foregoing and in accordance with the present invention, systems and methods for high speed test probing of densely packaged semiconductor devices is provided. In particular the systems and methods for connections to be made to a packaged semiconductor part, a probe assembly comprised of several connection points can be used. In general, the semiconductor package will only be approximately flat and so it is important that the probes are able to make reliable connections to a package that is not at a uniform distance. Conventionally, spring probes are used that enable compliance over quite a range of flatness parameters whilst ensuring sufficient pressure to make positive contact despite oxidation or similar contamination of the contact surface on the device under test.
Of particular interest are larger semiconductor packages having very high contact density. Typically, these will be in the form of either a BGA (Ball Grid Array) or LGA (Land Grid Array) where the contacts are located on the base of the semiconductor package and either finished with, for example, a solder ball in the case of the BGA or simply solder-free contact lands in the case of an LGA. As operating frequencies increase, the physical distance to connection points begins to play an increasingly important part in limiting the speed of operation of the device itself so a minimum distance design should be employed to overcome, or at least constrain this problem. Equally, coupling between probe elements due to either capacitive or inductive effects seen as “cross-talk” is an undesirable error source and this too should be considered and minimized. Except for the peripheral balls or lands that are the contact points for the device-under-test, each is surrounded by eight other connection points in the array so, if a probe is attached for test purposes, then there will be coupling between any connection and its eight neighbors as a result of parasitic capacitance or the mutual inductance between the probe elements, or pins. Primarily, because the effect of this capacitance at the higher test frequencies, this displaying an impedance that is inversely related to frequency, the speed limit of the device under test becomes dominated by the propriety of connections that link it to other components. A test probe, by definition, is a temporary connection and so carries the burden of having to be robust in order for it to be useful for many test cycles. This aspect alone translates into a structure that is prone to both capacitive and inductive coupling between neighboring connections since the test pins in the probe assembly are necessarily closely spaced and run parallel for several millimeters, sometimes as much as a centimeter or more depending on the testing environment. Once outside the test probe structure itself, shielded cabling is generally used, which limits the addition of parasitic coupling, but at the cost of relatively expensive interconnection wiring to the test instruments being used for the tests.
By locating the pins, that form the connection to the device under test, within a metal body that surrounds each pin, the inter-pin parasitic effects can be controlled and minimized. In addition, if suitable dimensions are selected, the characteristic impedance of the assembly can be determined and controlled so that problems related to mismatching of drive impedances can also be resolved and the device under test inspected up to its design operating frequencies.
Note that the various features of the present invention described above may be practiced alone or in combination. These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
In order that the present invention may be more clearly ascertained, some embodiments will now be described, by way of example, with reference to the accompanying drawings, in which:
The present invention will now be described in detail with reference to several embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention. The features and advantages of embodiments may be better understood with reference to the drawings and discussions that follow.
Aspects, features and advantages of exemplary embodiments of the present invention will become better understood with regard to the following description in connection with the accompanying drawing(s). It should be apparent to those skilled in the art that the described embodiments of the present invention provided herein are illustrative only and not limiting, having been presented by way of example only. All features disclosed in this description may be replaced by alternative features serving the same or similar purpose, unless expressly stated otherwise. Therefore, numerous other embodiments of the modifications thereof are contemplated as falling within the scope of the present invention as defined herein and equivalents thereto. Hence, use of absolute and/or sequential terms, such as, for example, “always,” “will,” “will not,” “shall,” “shall not,” “must,” “must not,” “first,” “initially,” “next,” “subsequently,” “before,” “after,” “lastly,” and “finally,” are not meant to limit the scope of the present invention as the embodiments disclosed herein are merely exemplary.
The present invention relates to systems and methods for a high speed test probe intended for inspection of densely packaged semiconductor devices. Although it should be clear that this technology can be down-scaled for small semiconductor packages, the current area of interest focuses upon packaged semiconductor devices having high connection counts and are typically seen as BGA and LGA structures. Other technologies that present the connection points directly on the semiconductor, such as Flip-Chip, are of course very similar and the use of the descriptor BGA or LGA is not intended to be limiting. Pin Grid arrays are also appropriate connection technologies.
To facilitate discussion,
Housing elements 124 and 114 may be made of any suitable conductive material, and in one embodiment an aluminum alloy 6061 is used; and for robustness, with a T6 temper. Channel 127 is drilled in both the upper housing 124 and in the lower housing 114 so that, when assembled, the channels in both of these elements are accurately aligned. In the same way as insulating material 112 is provided, terminating at the lower (outer) surface of lower element 114, a similar insulating component 122 is provided, terminating at the upper surface of the upper element 124 and it should be noted that the illustrated dimensions for 124 and 114 are only for example, in that they can be sized for height in any way that lends itself to ease of manufacture and assembly of the structure. An upper component 130 is shown in this example for a BGA probe. This component provides a surface feature that guides each solder ball 140 to which a connection is desired so that it is held in a stable manner as the connecting pin is compressed.
Component 130 may be made of an insulating material if it is very thin, but if there is significant thickness to the part, it may be made of metal and plated with an insulating lining where the connecting pin penetrates it to mate with the ball 140. In one embodiment this component 130 is made from 6061 aluminum and is passivated by anodizing the selected surfaces. Typically the outer surfaces and the holes are anodized and the surface that butts up against the upper housing 124 can be left untreated, although even if the entire part is anodized, capacitive coupling is sufficient to assure that it is effectively connected to the housing at higher frequencies. In some embodiments, an insulating sleeve may be created and positioned within this component; this has the advantage that, at the cost of some complexity in manufacturing, a predetermined impedance for the coaxial structure so formed may be established so that discontinuities are minimized and in consequence any frequency dependence can be controlled.
If a goal is to minimize crosstalk, that undesired coupling of neighboring signals to a desired signal, then the shielding effect of the metal enclosure is sufficient. In one embodiment the pin density is very high, the major diameter of a connecting pin assembly is 0.17 mm and the diameter of the hole through which this part of the connecting pin passes is about 0.2 mm. Using the coaxial cable formula Z0={138 Log10 (D/d)}/√εr where Z0 is the characteristic impedance, D is the diameter of the channel and d is the major diameter of the pin (Fr is the relative dielectric constant which is about 1 for air making the equation simpler) we see that this is about 10Ω. To make a 50Ω section using this same pin, we need to make the channel about 2.3 times the pin diameter. Fortunately it is rarely necessary to make every section a 50Ω section and since every test jig is usually specific to the tested part this is not inconvenient. It is also possible to compensate for anomalies at specific frequencies by test-specific tuning; for example the addition of a dielectric sleeve can be used to reduce the characteristic impedance of the transmission line structure formed by the connection pin assembly and the housing.
Turning now to
Turning now to
In a similar way,
The pin 150 that is used to make the connection to the DUT is a compressible pin and can be fabricated in a number of ways to allow the pin to be made suitable for the particular application.
In some embodiments, the tip is segmented so that there are more than one contact point to pierce the oxide. In other embodiments, the tip is electrically machined so as to give a very rough surface with multiple points of contact. The tip 425 may be plated in the same material as the rest of the pin 405 or may have a preferred plating to reduce thermoelectric voltage effects. Persons of ordinary skill will understand that wear properties and plating choices may not be mutually compatible and that compromises will have to be made; for example a gold plating may be preferred for its corrosion resistance, yet a nickel plating chosen for its hard wearing properties.
The pins 405 themselves can be of any suitable material having the required mechanical properties and a plating material used to achieve the desired electrical properties. The opposite end of the pin 405 within the barrel has a shoulder 435, which is chosen to be a snug fit into the enclosing barrel 410, and forms the surface against which the spring 415 exerts force; there being two pins 405 and 406, the spring pushes them apart to the extent allowed by the geometry of the parts.
The illustration of
For completeness an exemplary crimp area 420 that secures this pin 405 into the barrel 410 is also shown. In some embodiments, a small flexible washer 455 may be installed to serve as a buffer between the harder pin assembly and the insulator 122 to reduce wear or damage to the insulator over time and repetitive cycles. The conical or shouldered section shape of the insulator is exemplary and it should be clear that so long as the insulator is secured in place relative to the housing 124 then other solutions may be used; for example any keyed surface that allows durable adhesion or restraint between the housing and the insulator material can be used. The flexible washer 455 serves only to absorb impact shock from the pin assembly and if the lifetime of the probe assembly is determined to be sufficient without this component then it may be excluded. In one embodiment, the diameter of the channel cut into the housing is about 0.2 mm and the pin barrel is about 0.17 mm. In another embodiment, the housing channel is 2.3 times the barrel diameter and a smaller pin assembly is used so that the coaxial section has a line impedance of 50Ω. In yet another embodiment, a dielectric sleeve is fitted that reduces the impedance of this transmission line section to a lower impedance whilst maintaining a required tolerance for its operating voltage. Dielectric sleeves may also be used to provide reactive elements to tune out or match the device under test to the driving impedance of the testing equipment.
It will be observed that the pin and barrel crimp 420 secures these two parts firmly together and this end of the pin assembly is used to make the connection to the DUT. This offers the benefit that any incidental side loading that has to be reacted by the neck 430 region at the other end of the pin assembly is far lower than if it were proximate to the contact point and this contributes significantly to good probe assembly lifetime.
The lower housing 114 also has an insulating section where the other, sliding pin 406 penetrates it. The connection between the pin assembly and the test equipment that is connected to the DUT by the probe assembly is connected at this point and unlike the assembly in
The probe assembly dimensions vary according to the application, the number of contacts to be connected and the flatness of the DUT. The probe height measured from the bottom of the lower housing 114 to the top surface of the upper housing is typically between 2 mm and 5 mm. The upper layer 130 construction is not fixed. It may be any material that can provide insulation or a combination of materials that can perform this function. If a passivated (anodized) aluminum is used, this has the advantage of continuing the shielding as close to the ball of a BGA DUT as is possible, but creates a parasitic capacitance to ground that should be considered when the test regime for the DUT is being designed. Specific applications may use a composite upper layer where the main bulk is anodized aluminum and specific connection points have a plastic insert to reduce this parasitic component whilst still retaining most of the shielding advantages.
In sum, the present invention provides a system and methods for high speed test probing of densely packaged semiconductor devices. The advantages of such a system include the ability to greatly reduce crosstalk between channels, which is exacerbated by very densely packed connection points.
While this invention has been described in terms of several embodiments, there are alterations, modifications, permutations, and substitute equivalents, which fall within the scope of this invention. Although sub-section titles have been provided to aid in the description of the invention, these titles are merely illustrative and are not intended to limit the scope of the present invention. In addition, where claim limitations have been identified, for example, by a numeral or letter, they are not intended to imply any specific sequence.
It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and substitute equivalents as fall within the true spirit and scope of the present invention.
This non-provisional application claims priority to U.S. Provisional Application No. 62/854,117, Attorney Docket No. ES-1901-P, filed on May 29, 2019, of the same title, by inventors Joven R. Tienzo et al., which is incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
62854117 | May 2019 | US |