The present disclosure relates generally to semiconductor memory devices and, more particularly, to techniques for providing a direct injection semiconductor memory device.
The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (for example, double, triple gate, or surrounding gate), and Fin-FET devices.
A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charges may be stored. When excess majority electrical charges carriers are stored in the electrically floating body region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating body region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., multiple gate devices, Fin-FETs, recessed gates and pillars).
In one conventional technique, the memory cell of the semiconductor memory device may be read by applying bias signals to a source/drain region and/or a gate of the memory transistor. As such, a conventional reading technique may involve sensing an amount of current provided/generated by/in the electrically floating body region of the memory cell in response to the application of the source/drain region or gate bias signals to determine a data state stored in the memory cell. For example, the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: a binary “0” data state and a binary “1” data state).
In another conventional technique, the memory cell of the semiconductor memory device may be written to by applying bias signals to the source/drain region(s) and/or the gate of the memory transistor. As such, a conventional writing technique may result in an increase/decrease of majority charge carriers in the electrically floating body region of the memory cell which, in turn, may determine the data state of the memory cell. An increase of majority charge carriers in the electrically floating body region may result from impact ionization, band-to-band tunneling (gate-induced drain leakage “GIDL”), or direct injection. A decrease of majority charge carriers in the electrically floating body region may result from charge carriers being removed via drain region charge carrier removal, source region charge carrier removal, or drain and source region charge carrier removal, for example, using back gate pulsing.
Often, conventional reading and/or writing operations may lead to relatively large power consumption and large voltage potential swings which may cause disturbance to unselected memory cells in the semiconductor memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of majority charge carriers in the electrically floating body region of the memory cell in the semiconductor memory device, which, in turn, may result in an inaccurate determination of the state of the memory cell. Furthermore, in the event that a bias is applied to the gate of the memory transistor that is below a threshold voltage potential of the memory transistor, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate as a result of the applied bias. As a result, the net quantity of majority charge carriers in the electrically floating body region may be reduced. This phenomenon, which is typically characterized as charge pumping, is problematic because the net quantity of majority charge carriers may be reduced in the electrically floating body region of the memory cell, which, in turn, may result in an inaccurate determination of the state of the memory cell.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for fabricating and/or operating semiconductor memory devices.
Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
In accordance with other aspects of this particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a read operation.
In accordance with further aspects of this particular exemplary embodiment, the method may further comprise increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a read operation.
In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise maintaining the second voltage potential applied to the source line during a hold operation to perform a read operation.
In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise increasing the first voltage potential applied to the bit line from the first voltage potential applied to the bit line during a hold operation in order to reduce a disturbance during a read operation.
In accordance with other aspects of this particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the word line from the third voltage potential applied to the word line during a hold operation to perform a write logic high operation.
In accordance with further aspects of this particular exemplary embodiment, the method may further comprise lowering the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a write logic high operation.
In accordance with additional aspects of this particular exemplary embodiment, the second voltage potential applied to the source line to perform the write logic high operation may be lowered to forward bias a junction between the second N-doped region and the P-type substrate.
In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise increasing the third voltage potential applied to the respective word line from the third voltage potential applied to the respective word line during a hold operation to perform a write logic low operation.
In accordance with other aspects of this particular exemplary embodiment, the method may further comprise increasing the second voltage potential applied to the source line from the second voltage potential applied to the source line during a hold operation to perform a write logic low operation.
In accordance with further aspects of this particular exemplary embodiment, the method may further comprise maintaining the second voltage potential applied to the source line during a hold operation to perform a write logic low operation.
In accordance with additional aspects of this particular exemplary embodiment, the method may further comprise maintaining the first voltage potential applied to the bit line during a hold operation to perform a write logic low operation.
In accordance with yet another aspect of this particular exemplary embodiment, the method may further comprise increasing the first voltage potential applied to the bit line during a write logic low operation from the first voltage potential applied to the bit line during a hold operation to maintain a logic high stored in the memory cell.
In accordance with other aspects of this particular exemplary embodiment, the second voltage potential applied to the source line may be equal to the fourth voltage potential applied to the carrier injection line during a hold operation.
In another particular exemplary embodiment, the techniques may realized as a direct injection semiconductor memory device comprising a first N-doped region coupled to a bit line and a second N-doped region coupled to a source line. The direct injection semiconductor memory device may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first N-doped region and the second N-doped region the direct injection semiconductor memory device may further comprise a P-type substrate coupled to a carrier injection line.
In accordance with other aspects of this particular exemplary embodiment, the first N-doped region, the body region, and the second N-doped region may form a bipolar transistor.
In accordance with further aspects of this particular exemplary embodiment, the second N-doped region and the P-type substrate may form a PN junction diode.
In accordance with additional aspects of this particular exemplary embodiment, the bit line may extend from the first N-doped region perpendicular to at least a portion of at least one of the source line, the word line, and the carrier injection line.
In accordance with yet another aspect of this particular exemplary embodiment, the word line may extend from near the body region horizontally parallel to at least a portion of at least one of the source line and the carrier injection line.
In accordance with other aspects of this particular exemplary embodiment, the source line may extend from the second N-doped region parallel to at least one of the word line and the carrier injection line.
In another exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first P-doped region via a bit line and applying a second voltage potential to a second P-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first P-doped region and the second P-doped region. The method may further comprise applying a fourth voltage potential to an N-type substrate via a carrier injection line.
In another exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device that may comprise a first P-doped region coupled to a bit line and a second P-doped region coupled to a source line. The direct injection semiconductor memory device may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first N-doped region and the second N-doped region. The direct injection semiconductor memory device may further comprise a P-type substrate coupled to a carrier injection line.
The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.
In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.
Referring to
The data write and sense circuitry 36 may read data from and may write data to selected memory cells 12. In an exemplary embodiment, the data write and sense circuitry 36 may include a plurality of data sense amplifiers. Each data sense amplifier may receive at least one bit line (EN) 32 and a current or voltage reference signal. For example, each data sense amplifier may be a cross-coupled type sense amplifier to sense a data state stored in a memory cell 12.
Each data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In an exemplary embodiment, each data sense amplifier may employ current sensing circuitry and/or techniques. For example, a current sense amplifier may compare current from a selected memory cell 12 to a reference current (e.g., the current of one or more reference cells). From that comparison, it may be determined whether the selected memory cell 12 stores a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state). It may be appreciated by one having ordinary skill in the art that various types or forms of the data write and sense circuitry 36 (including one or more sense amplifiers, using voltage or current sensing techniques, to sense a data state stored in a memory cell 12) may be employed to read data stored in memory cells 12 and/or write data to memory cells 12.
The memory cell selection and control circuitry 38 may select and/or enable one or more predetermined memory cells 12 to facilitate reading data therefrom and/or writing data thereto by applying control signals on one or more word lines (WL) 28, source lines (CN) 30, and/or carrier injection lines (EP) 34. The memory cell selection and control circuitry 38 may generate such control signals from address signals, for example, row address signals. Moreover, the memory cell selection and control circuitry 38 may include a word line decoder and/or driver. For example, the memory cell selection and control circuitry 38 may include one or more different control/selection techniques (and circuitry therefor) to select and/or enable one or more predetermined memory cells 12. Notably, all such control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present disclosure.
In an exemplary embodiment, the semiconductor memory device 10 may implement a two step write operation whereby all the memory cells 12 in a row of memory cells 12 may be written to a predetermined data state by first executing a “clear” or a logic low (e.g., binary “0” data state) write operation, whereby all of the memory cells 12 in the row of memory cells 12 are written to logic low (e.g., binary “0” data state). Thereafter, selected memory cells 12 in the row of memory cells 12 may be selectively written to the predetermined data state (e.g., a logic high (binary “1” data state)). The semiconductor memory device 10 may also implement a one step write operation whereby selective memory cells 12 in a row of memory cells 12 may be selectively written to either a logic high (e.g., binary “1” data state) or a logic low (e.g., binary “0” data state) without first implementing a “clear” operation. The semiconductor memory device 10 may employ any of the exemplary writing, preparation, holding, refresh, and/or reading techniques described herein.
The memory cells 12 may comprise N-type, P-type and/or both types of transistors. Circuitry that is peripheral to the memory array 20 (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may also include P-type and/or N-type transistors. Regardless of whether P-type or N-type transistors are employed in memory cells 12 in the memory cell array 20, suitable voltage potentials (for example, positive or negative voltage potentials) for reading from and/or writing to the memory cells 12 will be described further herein.
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In an exemplary embodiment, the P+ region 126 may be configured as an input region for charges to be stored in the P− region 122 of the memory cell 12. The charges to be stored in the P− region 122 of the memory cell 12 may be supplied by the carrier injection line (EP) 34 and input into the P− region 122 via the P+ region 126 and the N+ region 124.
The carrier injection line (EP) 34 may be formed of a polycide layer or a metal layer extending in a row direction of the memory cell array 20. For example, the carrier injection line (EP) 34 may extend horizontally in parallel to the word line (WL) 28 and/or the source line (CN) 30, and may be coupled to a plurality of memory cells 12 (e.g., a row of memory cells 12). For example, the carrier injection line (EP) 34 and the word line (WL) 28 and/or the source line (CN) 30 may be arranged in different planes and configured to be parallel to each other. In an exemplary embodiment, the carrier injection line (EP) 34 may be arranged in a plane below a plane containing the word line (WL) 28 and a plane containing the source line (CN) 30.
Referring to
Each memory cell 12 may be coupled to a respective word line (WL) 28, a respective source line (CN) 30, a respective bit line (EN) 32, and a respective carrier injection line (EP) 34. Data may be written to or read from a selected memory cell 12 by applying suitable control signals to a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34. In an exemplary embodiment, each word line (WL) 28, source line (CN) 30, and carrier injection line (EP) 34 may extend horizontally parallel to each other in a row direction. Each bit line (EN) 32 may extend vertically in a column direction perpendicular to each word line (WL) 28, source line (CN) 30, and/or carrier injection line (EP) 34.
In an exemplary embodiment, one or more respective bit lines (EN) 32 may be coupled to one or more data sense amplifiers (not shown) of the data write and sense circuitry 36 to read data states of one or more memory cells 12 in the column direction. A data state may be read from one or more selected memory cells 12 by applying one or more control signals to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, and/or a selected carrier injection line (EP) 34 in order to generate a voltage potential and/or a current in the one or more selected memory cells 12. The generated voltage potential and/or current may be output to the data write and sense circuitry 36 via a corresponding bit line (EN) 32 in order to read a data state stored in each selected memory cell 12.
In the event that a data state is read from a selected memory cell 12 via a selected bit line (EN) 32, then only the bit line (EN) 32 may be coupled to the data sense amplifier of the data write and sense circuitry 36. In an exemplary embodiment, the data write and sense circuitry 36 may be configured on opposite sides of the memory cell array 20.
Also, a data state may be written to one or more selected memory cells 12 by applying one or more control signals to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34. The one or more control signals applied to the one or more selected memory cells 12 via a selected word line (WL) 28, a selected source line (CN) 30, a selected bit line (EN) 32, and/or a selected carrier injection line (EP) 34 may control the bipolar transistor 14a and/or the diode 14b of each selected memory cell 12 in order to write a desired data state to each selected memory cell 12.
The source line (CN) 30 may be subcircuits 302 of the memory cell selection and control circuitry 38 (e.g., driver, inverter, and/or logic circuits). The carrier injection lines (EP) 34 may be driven by subcircuits of the memory cell selection and control circuitry 38 (e.g., driver, inverter, and/or logic circuits). The subcircuits coupled to each carrier injection line (EP) 34 may be independent voltage drivers located within and/or integrated with the memory cell selection and control circuitry 38. To reduce an amount of area required by the subcircuits of the memory cell selection and control circuitry 38, a plurality of carrier injection lines (EP) 34 of the memory cell array 20 may be coupled to a single subcircuit within the memory cell selection and control circuitry 38. In an exemplary embodiment, the subcircuits of the memory cell selection and control circuitry 38 may bias a plurality of carrier injection lines (EP) 34 coupled together to different voltage potentials and/or current levels (e.g., 0V, 1.0V, etc).
In an exemplary embodiment, during active operations (e.g., read operation or write operation), the memory cell 12 (e.g., corresponding to bit line EN<0> 32) located near the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38 may be activated before the memory cells 12 (e.g., correspond to bit lines EN<1>, EN<2>, and EN<3>) located farther from the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38. The memory cell 12 (e.g., corresponding to bit line EN<0> 32) located near the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38 may impact a voltage potential and/or current applied to the source line (CN) 30. For example, when control signals are applied to the memory cell 12 (e.g., corresponding to bit line EN<0> 32) located near the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38, thereby turning the bipolar transistor 14a of the memory cell 12 to an “ON” state, the actions performed by the bipolar transistor 14a of the memory cell 12 may impact a voltage potential and/or current applied to the source line (CN) 30 (e.g., raise or lower the voltage potential). Thus, the memory cell 12 (e.g., corresponding to bit line EN<0> 32) located near the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38 may impact an operation performed by the memory cells 12 located farther from the subcircuits (e.g., drivers) within the memory cell selection and control circuitry 38.
Referring to
In an exemplary embodiment, during a hold operation, a negative voltage potential may be applied to the word line (WL) 28 that may be capacitively coupled to the P− region 122 of the memory cell 12, while a voltage potential applied to the N+ region 120 may be maintained at approximately 0V. The voltage potential applied to the N+ region 124 may be the same as the voltage potential applied to the P+ region 126. For example, the negative voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be −1.0V, the voltage potentials applied to the N+ region 124 and the P+ region 126 may range between 0.7V to 1.0V. During the hold operation, the junction between the N+ region 124 and the P− region 122 and the junction between the N+ region 120 and the P− region 122 may be reverse biased in order to retain a data state (e.g., a logic high (binary “1” data state) or a logic low (binary “0” data state)) stored in the memory cell 12.
Referring to
In an exemplary embodiment, during the read operation, the voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122 of the memory cell 12) may be raised to −0.5V and the voltage potential applied to the source line (CN) 30 may be raised to 1.1V. Under such biasing, the junction between the P− region 122 and the N+ region 120 may become forward biased. Also, under such biasing, the junction between the P− region 122 and the N+ region 124 may be reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). A voltage potential or current may be generated when forward biasing the junction between the P− region 122 and the N+ region 120. The voltage potential or current generated may be output to a data sense amplifier via the bit line (EN) 32 coupled to the N+ region 120. An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12.
In an exemplary embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell 12 (e.g., corresponding to bit line (EN<1>) 32), the junction between the P− region 122 and the N+ region 120 may remain reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). A small amount of voltage potential or current or no voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region 122 and the N+ region 120 is reverse biased or weakly forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the small amount of voltage potential or current or no voltage potential or current via the bit line (EN<1>) 32 coupled to the N+ region 120.
In another exemplary embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell 12 (e.g., corresponding to the bit line (EN<0>) 32), the junction between the P− region 122 and the N+ region 120 may be forward biased. A larger amount of voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region 122 and the N+ region 120 is forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the larger amount of voltage potential or current via the bit line (EN<0>) 32 coupled to the N+ region 120.
During one or more active operations (e.g., read operation, write operation, sense operation, preparation to start/end operation, and/or refresh operation), voltage potentials may be applied to every memory cell 12 along an active row via a corresponding word line (WL) 28, a corresponding source line (CN) 30, and/or a corresponding carrier injection line (EP) 34. However, while the active operations may be performed on one or more selected memory cells 12 along the active row, one or more unselected memory cells 12 (e.g., corresponding to bit lines (EN<2>) and (EN<3>) 32) along the active row may experience a disturbance caused by the voltage potentials applied via the corresponding word line (WL) 28, the corresponding source line (CN) 30, and/or the corresponding carrier injection line (EP) 34 during the active operations. In order to reduce a disturbance experienced by the one or more unselected memory cells 12 (e.g., corresponding to bit lines (EN<2>) and (EN<3>) 32) along the active row, a masking operation may be performed on the one or more unselected memory cells 12.
In an exemplary embodiment, during a masking operation, a voltage potential may be applied to the one or more unselected memory cells 12 on an active row via corresponding bit lines (EN<2>) and (EN<3>) 32. The voltage potential applied via the corresponding bit lines (EN<2>) and (EN<3>) 32 to the one or more unselected memory cells 12 on the active row may be raised to a predetermined voltage potential. In an exemplary embodiment, the voltage potential applied to the corresponding bit lines (EN<2>) and (EN<3>) 32 associated with the one or more unselected memory cells 12 along the active row may be 1.1V in order to reduce a disturbance caused by the other voltage potentials applied during the active operations.
Referring to
Under such biasing, the junction between the P− region 122 and the N+ region 120 may become forward biased. Also, under such biasing, the junction between the P− region 122 and the N+ region 124 may be reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). A voltage potential or current may be generated when forward biasing the junction between the P− region 122 and the N+ region 120. The voltage potential or current generated may be output to a data sense amplifier via the bit line (EN) 32 coupled to the N+ region 120. An amount of voltage potential or current generated may be representative of a data state (e.g., a logic low (binary “0” data state) and/or a logic high (binary “1” data state)) stored in the memory cell 12.
In an exemplary embodiment, when a logic low (e.g., binary “0” data state) is stored in the memory cell 12 (e.g., corresponding to the bit line (EN<1>) 32), the junction between the P− region 122 and the N+ region 120 may remain reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). A small amount of voltage potential or current or no voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region 122 and the N+ region 120 is reverse biased or weakly forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the small amount of voltage potential or current or no voltage potential or current via the bit line (EN<1>) 32 coupled to the N+ region 120.
In another exemplary embodiment, when a logic high (e.g., binary “1” data state) is stored in the memory cell 12 (e.g., corresponding to the bit line (EN<0>) 32), the junction between the P− region 122 and the N+ region 120 may be forward biased. A larger amount of voltage potential or current (e.g., compared to a reference voltage potential or current) may be generated when the junction between the P− region 122 and the N+ region 120 is forward biased. A data sense amplifier in the data write and sense circuitry 36 may detect the larger amount of voltage potential or current via the bit line (EN<0>) 32 coupled to the N+ region 120.
During one or more active operations (e.g., read operation, write operation, sense operation, preparation to start/end operation, and/or refresh operation), voltage potentials may be applied to every memory cell 12 along an active row via a corresponding word line (WL) 28, a corresponding source line (CN) 30, and/or a corresponding carrier injection line (EP) 34. However, while the active operations may be performed on one or more selected memory cells 12 along the active row, one or more unselected memory cells 12 (e.g., corresponding to bit lines (EN<2>) and (EN<3>) 32) along the active row may experience a disturbance caused by the voltage potentials applied via the corresponding word line (WL) 28, the corresponding source line (CN) 30, and/or the corresponding carrier injection line (EP) 34 during the active operations. In order to reduce a disturbance experienced by the one or more unselected memory cells 12 (e.g., corresponding to bit lines (EN<2>) and (EN<3>) 32) along the active row, a masking operation may be performed on the one or more unselected memory cells 12.
In an exemplary embodiment, during a masking operation, a voltage potential may be applied to the one or more unselected memory cells 12 on an active row via corresponding bit lines (EN<2>) and (EN<3>) 32. The voltage potential applied via the corresponding bit lines (EN<2>) and (EN<3>) 32 to the one or more unselected memory cells 12 on the active row may be raised to a predetermined voltage potential. In an exemplary embodiment, the voltage potential applied to the corresponding bit lines (EN<2>) and (EN<3>) 32 associated with the one or more unselected memory cells 12 along the active row may be 1.1V in order to reduce a disturbance caused by the other voltage potentials applied during the active operations.
Referring to
In an exemplary embodiment, during the write logic high (e.g., binary “1” data state) operation, a voltage potential applied to the N+ region 120 of a selected memory cell 12 via a corresponding bit line (EN) 32 may be maintained at 0V, a voltage potential applied to the P+ region 126 of the selected memory cell 12 via a corresponding carrier injection line (EP) 34 may be maintained at 0.7V, and a voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) may be raised to −0.5V from −1.0V. Simultaneously to or subsequent to raising a voltage potential applied to the word line (WL) 28, a voltage potential applied to the source line (CN) 30 may be lowered to 0V from 0.7V.
Under such biasing, the junction between the N+ region 120 and the P− region 122 may be reverse biased and the junction between the P+ region 126 and the N+ region 124 may become forward biased. A logic high (e.g., binary “1” data state) may be written to the P− region 122 (e.g., majority charge carriers injected into the P− region 122 from the P+ region 126 via the N+ region 124) via the forward biased junction between the P+ region 126 and the N+ region 124. As more majority charge carriers accumulate in the P− region 122, the voltage potential at the P− region 122 may increase to approximately 0.7V to 1.0V above the voltage potential at the N+ region 124. A sufficient amount of majority charge carriers may be injected into the P− region 122 to represent that a logic high (e.g., binary “1” data state) is stored in the memory cell 12.
Referring to
In an exemplary embodiment, during the write logic high (e.g., binary “1” data state) operation, a voltage potential applied to the N+ region 120 of a selected memory cell 12 via a corresponding bit line (EN) 32 may be maintained at 0V, a voltage potential applied to the P+ region 126 of the selected memory cell 12 via a corresponding carrier injection line (EP) 34 may be maintained at 1.0V, and a voltage potential applied to the word line (WL) 28 (e.g., capacitively coupled to the P− region 122) may be raised to −0.7V from −1.0V. Simultaneously to or subsequent to raising a voltage potential applied to the word line (WL) 28, a voltage potential applied to the source line (CN) 30 may be lowered to 0.3V from 1.0V.
Under such biasing, the junction between the N+ region 120 and the P− region 122 may be reverse biased and the junction between the P+ region 126 and the N+ region 124 may become forward biased. A logic high (e.g., binary “1” data state) may be written to the P− region 122 (e.g., majority charge carriers injected into the P− region 122 from the P+ region 126 via the N+ region 124) via the forward biased junction between the P+ region 126 and the N+ region 124. As more majority charge carriers accumulate in the P− region 122, the voltage potential at the P− region 122 may increase to approximately 0.7V to 1.0V above the voltage potential at the N+ region 124. A sufficient amount of majority charge carriers may be injected into the P− region 122 to represent that a logic high (e.g., binary “1” data state) is stored in the memory cell 12.
Referring to
In an exemplary embodiment, a voltage potential applied to the N+ region 120 via the bit line (EN(“0”)) 32 may be maintained at 0V in order to perform the write logic low (e.g., binary “0” data state) operation. A voltage potential applied to the N+ region 124 via the source line (CN) 30 may be raised to 1.1V from 0V in order to perform a write logic low (e.g., binary “0” data state) operation. Subsequent to or simultaneously to raising the voltage potential applied to the N+ region 124 via the source line (CN) 30, a voltage potential applied to the word line (WL) 28 may be raised to approximately 0.5V from −1.0V.
Under such biasing, the junction between the N+ region 120 and the P− region 122 may become forward biased. The junction between the N+ region 124 and the P− region 122 may become reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). Majority charge carriers that may have accumulated in the P− region 122 during a write logic high (e.g., binary “1” data state) operation may be removed via the forward biased junction between the N+ region 120 and the P− region 122. After removing the majority charge carriers from the P− region 122, a logic low (e.g., binary “0” data state) may be written to the memory cell 12.
In order to maintain a logic high (e.g., binary “1” data state) in one or more unselected memory cells 12 during the write logic low (e.g., binary “0” data state) operation, a masking operation may be performed on the one or more unselected memory cells 12. For example, a voltage potential applied to the N+ region 120 via a bit line (EN(“1”)) 32 of the one or more unselected memory cells 12 may be raised to 1.1V from 0.7V or higher (e.g., 1.2V) in order to prevent the depletion of majority charge carriers accumulated in the P− region 122. Under such biasing, the junction between the N+ region 120 and the P− region 122 may not be forward biased and the junction between the P− region 122 and the N+ region 124 may not be forward biased in order to prevent the depletion of majority charge carriers accumulated in the P− region 122 so as to allow the logic high (e.g., binary “1” data state) to be maintained in the memory cell 12.
Referring to
In an exemplary embodiment, a voltage potential applied to the N+ region 120 via the bit line (EN(“0”)) 32 may be maintained at 0V in order to perform the write logic low (e.g., binary “0” data state) operation. A voltage potential applied to the N+ region 124 via the source line (CN) 30 may be maintained at 1.0V in order to perform a write logic low (e.g., binary “0” data state) operation. A voltage potential applied to the P+ region 126 via the carrier injection line (EP) 34 may be maintained at 1.0V. A voltage potential applied to the word line (WL) 28 may be raised to approximately 0.5V from −1.0V.
Under such biasing, the junction between the N+ region 120 and the P− region 122 may become forward biased. The junction between the N+ region 124 and the P− region 122 may become reverse biased or become weakly forward biased (e.g., above a reverse bias voltage and below a forward bias threshold voltage, or a voltage potential at a p-diffusion region in the P− region 122 may be higher than a voltage potential at an n-diffusion region in the N+ region 124). Majority charge carriers that may have accumulated in the P− region 122 during a write logic high (e.g., binary “1” data state) operation may be removed via the forward biased junction between the N+ region 120 and the P− region 122. After removing the majority charge carriers from the P− region 122, a logic low (e.g., binary “0” data state) may be written to the memory cell 12.
In order to maintain a logic high (e.g., binary “1” data state) in one or more unselected memory cells 12 during the write logic low (e.g., binary “0” data state) operation, a masking operation may be performed on the one or more unselected memory cells 12. For example, a voltage potential applied to the N+ region 120 via a bit line (EN(“1”)) 32 of the one or more unselected memory cells 12 may be raised to 1.0V from 0V or higher (e.g., 1.2V) in order to prevent the depletion of majority charge carriers accumulated in the P− region 122. Under such biasing, the junction between the N+ region 120 and the P− region 122 may not be forward biased and the junction between the P− region 122 and the N+ region 124 may not be forward biased in order to prevent the depletion of majority charge carriers accumulated in the P− region 122 so as to allow the logic high (e.g., binary “1” data state) to be maintained in the memory cell 12.
At this point it should be noted that providing a direct injection semiconductor memory device in accordance with the present disclosure as described above typically involves the processing of input data and the generation of output data to some extent. This input data processing and output data generation may be implemented in hardware or software. For example, specific electronic components may be employed in a direct injection semiconductor memory device or similar or related circuitry for implementing the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. Alternatively, one or more processors operating in accordance with instructions may implement the functions associated with providing a direct injection semiconductor memory device in accordance with the present disclosure as described above. If such is the case, it is within the scope of the present disclosure that such instructions may be stored on one or more processor readable media (e.g., a magnetic disk or other storage medium), or transmitted to one or more processors via one or more signals embodied in one or more carrier waves.
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.
This patent application claims priority to U.S. Provisional Patent Application No. 61/173,014, filed Apr. 27, 2009, which is hereby incorporated by reference herein in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
3439214 | Kabell | Apr 1969 | A |
3997799 | Baker | Dec 1976 | A |
4032947 | Kesel et al. | Jun 1977 | A |
4250569 | Sasaki et al. | Feb 1981 | A |
4262340 | Sasaki et al. | Apr 1981 | A |
4298962 | Hamano et al. | Nov 1981 | A |
4371955 | Sasaki | Feb 1983 | A |
4527181 | Sasaki | Jul 1985 | A |
4630089 | Sasaki et al. | Dec 1986 | A |
4658377 | McElroy | Apr 1987 | A |
4791610 | Takemae | Dec 1988 | A |
4807195 | Busch et al. | Feb 1989 | A |
4954989 | Auberton-Herve et al. | Sep 1990 | A |
4979014 | Hieda et al. | Dec 1990 | A |
5010524 | Fifield et al. | Apr 1991 | A |
5144390 | Matloubian | Sep 1992 | A |
5164805 | Lee | Nov 1992 | A |
5258635 | Nitayama et al. | Nov 1993 | A |
5295107 | Okazawa et al. | Mar 1994 | A |
5313432 | Lin et al. | May 1994 | A |
5315541 | Harari et al. | May 1994 | A |
5350938 | Matsukawa | Sep 1994 | A |
5355330 | Hisamoto et al. | Oct 1994 | A |
5388068 | Ghoshal et al. | Feb 1995 | A |
5397726 | Bergemont et al. | Mar 1995 | A |
5432730 | Shubat et al. | Jul 1995 | A |
5446299 | Acovic et al. | Aug 1995 | A |
5448513 | Hu et al. | Sep 1995 | A |
5466625 | Hsieh et al. | Nov 1995 | A |
5489792 | Hu et al. | Feb 1996 | A |
5506436 | Hayashi et al. | Apr 1996 | A |
5515383 | Katoozi | May 1996 | A |
5526307 | Yiu et al. | Jun 1996 | A |
5528062 | Hsieh et al. | Jun 1996 | A |
5568356 | Schwartz | Oct 1996 | A |
5583808 | Brahmbhatt | Dec 1996 | A |
5593912 | Rajeevakumar | Jan 1997 | A |
5606188 | Bronner et al. | Feb 1997 | A |
5608250 | Kalnitsky | Mar 1997 | A |
5627092 | Alsmeier et al. | May 1997 | A |
5631186 | Park et al. | May 1997 | A |
5659504 | Bude et al. | Aug 1997 | A |
5677867 | Hazani | Oct 1997 | A |
5696718 | Hartmann | Dec 1997 | A |
5740099 | Tanigawa | Apr 1998 | A |
5754469 | Hung et al. | May 1998 | A |
5774411 | Hsieh et al. | Jun 1998 | A |
5778243 | Aipperspach et al. | Jul 1998 | A |
5780906 | Wu et al. | Jul 1998 | A |
5784311 | Assaderaghi et al. | Jul 1998 | A |
5798968 | Lee et al. | Aug 1998 | A |
5811283 | Sun | Sep 1998 | A |
5847411 | Morii | Dec 1998 | A |
5877978 | Morishita et al. | Mar 1999 | A |
5886376 | Acovic et al. | Mar 1999 | A |
5886385 | Arisumi et al. | Mar 1999 | A |
5897351 | Forbes | Apr 1999 | A |
5929479 | Oyama | Jul 1999 | A |
5930648 | Yang | Jul 1999 | A |
5936265 | Koga | Aug 1999 | A |
5939745 | Park et al. | Aug 1999 | A |
5943258 | Houston et al. | Aug 1999 | A |
5943581 | Lu et al. | Aug 1999 | A |
5960265 | Acovic et al. | Sep 1999 | A |
5968840 | Park et al. | Oct 1999 | A |
5977578 | Tang | Nov 1999 | A |
5982003 | Hu et al. | Nov 1999 | A |
5986914 | McClure | Nov 1999 | A |
6018172 | Hidada et al. | Jan 2000 | A |
6048756 | Lee et al. | Apr 2000 | A |
6081443 | Morishita | Jun 2000 | A |
6096598 | Furukawa et al. | Aug 2000 | A |
6097056 | Hsu et al. | Aug 2000 | A |
6097624 | Chung et al. | Aug 2000 | A |
6111778 | MacDonald et al. | Aug 2000 | A |
6121077 | Hu et al. | Sep 2000 | A |
6133597 | Li et al. | Oct 2000 | A |
6157216 | Lattimore et al. | Dec 2000 | A |
6171923 | Chi et al. | Jan 2001 | B1 |
6177300 | Houston et al. | Jan 2001 | B1 |
6177698 | Gruening et al. | Jan 2001 | B1 |
6177708 | Kuang et al. | Jan 2001 | B1 |
6214694 | Leobandung et al. | Apr 2001 | B1 |
6222217 | Kunikiyo | Apr 2001 | B1 |
6225158 | Furukawa et al. | May 2001 | B1 |
6245613 | Hsu et al. | Jun 2001 | B1 |
6252281 | Yamamoto et al. | Jun 2001 | B1 |
6255166 | Ogura et al. | Jul 2001 | B1 |
6262935 | Parris et al. | Jul 2001 | B1 |
6292424 | Ohsawa | Sep 2001 | B1 |
6297090 | Kim | Oct 2001 | B1 |
6300649 | Hu et al. | Oct 2001 | B1 |
6320227 | Lee et al. | Nov 2001 | B1 |
6333532 | Davari et al. | Dec 2001 | B1 |
6333866 | Ogata | Dec 2001 | B1 |
6350653 | Adkisson et al. | Feb 2002 | B1 |
6351426 | Ohsawa | Feb 2002 | B1 |
6359802 | Lu et al. | Mar 2002 | B1 |
6384445 | Hidaka et al. | May 2002 | B1 |
6391658 | Gates et al. | May 2002 | B1 |
6399441 | Ogura et al. | Jun 2002 | B1 |
6403435 | Kang et al. | Jun 2002 | B1 |
6421269 | Somasekhar et al. | Jul 2002 | B1 |
6424011 | Assaderaghi et al. | Jul 2002 | B1 |
6424016 | Houston | Jul 2002 | B1 |
6429477 | Mandelman et al. | Aug 2002 | B1 |
6432769 | Fukuda et al. | Aug 2002 | B1 |
6440872 | Mandelman et al. | Aug 2002 | B1 |
6441435 | Chan | Aug 2002 | B1 |
6441436 | Wu et al. | Aug 2002 | B1 |
6466511 | Fujita et al. | Oct 2002 | B2 |
6479862 | King et al. | Nov 2002 | B1 |
6480407 | Keeth | Nov 2002 | B1 |
6492211 | Divakaruni et al. | Dec 2002 | B1 |
6518105 | Yang et al. | Feb 2003 | B1 |
6531754 | Nagano et al. | Mar 2003 | B1 |
6537871 | Forbes | Mar 2003 | B2 |
6538916 | Ohsawa | Mar 2003 | B2 |
6544837 | Divakauni et al. | Apr 2003 | B1 |
6548848 | Horiguchi et al. | Apr 2003 | B2 |
6549450 | Hsu et al. | Apr 2003 | B1 |
6552398 | Hsu et al. | Apr 2003 | B2 |
6552932 | Cernea | Apr 2003 | B1 |
6556477 | Hsu et al. | Apr 2003 | B2 |
6560142 | Ando | May 2003 | B1 |
6563733 | Liu et al. | May 2003 | B2 |
6566177 | Radens et al. | May 2003 | B1 |
6567330 | Fujita et al. | May 2003 | B2 |
6573566 | Ker et al. | Jun 2003 | B2 |
6574135 | Komatsuzaki | Jun 2003 | B1 |
6590258 | Divakauni et al. | Jul 2003 | B2 |
6590259 | Adkisson et al. | Jul 2003 | B2 |
6597047 | Arai et al. | Jul 2003 | B2 |
6617651 | Ohsawa | Sep 2003 | B2 |
6621725 | Ohsawa | Sep 2003 | B2 |
6632723 | Watanabe et al. | Oct 2003 | B2 |
6650565 | Ohsawa | Nov 2003 | B1 |
6653175 | Nemati et al. | Nov 2003 | B1 |
6686624 | Hsu | Feb 2004 | B2 |
6703673 | Houston | Mar 2004 | B2 |
6707118 | Muljono et al. | Mar 2004 | B2 |
6714436 | Burnett et al. | Mar 2004 | B1 |
6721222 | Somasekhar et al. | Apr 2004 | B2 |
6804149 | Ogura et al. | Oct 2004 | B2 |
6825524 | Ikehashi et al. | Nov 2004 | B1 |
6861689 | Burnett | Mar 2005 | B2 |
6870225 | Bryant et al. | Mar 2005 | B2 |
6882566 | Nejad et al. | Apr 2005 | B2 |
6888770 | Ikehashi | May 2005 | B2 |
6894913 | Yamauchi | May 2005 | B2 |
6897098 | Hareland et al. | May 2005 | B2 |
6903984 | Tang et al. | Jun 2005 | B1 |
6909151 | Hareland et al. | Jun 2005 | B2 |
6912150 | Portman et al. | Jun 2005 | B2 |
6913964 | Hsu | Jul 2005 | B2 |
6936508 | Visokay et al. | Aug 2005 | B2 |
6969662 | Fazan et al. | Nov 2005 | B2 |
6975536 | Maayan et al. | Dec 2005 | B2 |
6982902 | Gogl et al. | Jan 2006 | B2 |
6987041 | Ohkawa | Jan 2006 | B2 |
7030436 | Forbes | Apr 2006 | B2 |
7037790 | Chang et al. | May 2006 | B2 |
7041538 | Ieong et al. | May 2006 | B2 |
7042765 | Sibigtroth et al. | May 2006 | B2 |
7061806 | Tang et al. | Jun 2006 | B2 |
7085153 | Ferrant et al. | Aug 2006 | B2 |
7085156 | Ferrant et al. | Aug 2006 | B2 |
7170807 | Fazan et al. | Jan 2007 | B2 |
7177175 | Fazan et al. | Feb 2007 | B2 |
7187581 | Ferrant et al. | Mar 2007 | B2 |
7230846 | Keshavarzi | Jun 2007 | B2 |
7233024 | Scheuerlein et al. | Jun 2007 | B2 |
7256459 | Shino | Aug 2007 | B2 |
7301803 | Okhonin et al. | Nov 2007 | B2 |
7301838 | Waller | Nov 2007 | B2 |
7317641 | Scheuerlein | Jan 2008 | B2 |
7324387 | Bergemont et al. | Jan 2008 | B1 |
7335934 | Fazan | Feb 2008 | B2 |
7341904 | Willer | Mar 2008 | B2 |
7416943 | Figura et al. | Aug 2008 | B2 |
7456439 | Horch | Nov 2008 | B1 |
7477540 | Okhonin et al. | Jan 2009 | B2 |
7492632 | Carman | Feb 2009 | B2 |
7517744 | Mathew et al. | Apr 2009 | B2 |
7539041 | Kim et al. | May 2009 | B2 |
7542340 | Fisch et al. | Jun 2009 | B2 |
7542345 | Okhonin et al. | Jun 2009 | B2 |
7545694 | Raghavan et al. | Jun 2009 | B2 |
7606066 | Okhonin et al. | Oct 2009 | B2 |
7696032 | Kim et al. | Apr 2010 | B2 |
7974127 | Chong et al. | Jul 2011 | B2 |
8159875 | Bhattacharyya | Apr 2012 | B2 |
8199595 | Bauser et al. | Jun 2012 | B2 |
20010055859 | Yamada et al. | Dec 2001 | A1 |
20020030214 | Horiguchi | Mar 2002 | A1 |
20020034855 | Horiguchi et al. | Mar 2002 | A1 |
20020036322 | Divakauni et al. | Mar 2002 | A1 |
20020051378 | Ohsawa | May 2002 | A1 |
20020064913 | Adkisson et al. | May 2002 | A1 |
20020070411 | Vermandel et al. | Jun 2002 | A1 |
20020072155 | Liu et al. | Jun 2002 | A1 |
20020076880 | Yamada et al. | Jun 2002 | A1 |
20020086463 | Houston et al. | Jul 2002 | A1 |
20020089038 | Ning | Jul 2002 | A1 |
20020098643 | Kawanaka et al. | Jul 2002 | A1 |
20020110018 | Ohsawa | Aug 2002 | A1 |
20020114191 | Iwata et al. | Aug 2002 | A1 |
20020130341 | Horiguchi et al. | Sep 2002 | A1 |
20020160581 | Watanabe et al. | Oct 2002 | A1 |
20020180069 | Houston | Dec 2002 | A1 |
20030003608 | Arikado et al. | Jan 2003 | A1 |
20030015757 | Ohsawa | Jan 2003 | A1 |
20030035324 | Fujita et al. | Feb 2003 | A1 |
20030042516 | Forbes et al. | Mar 2003 | A1 |
20030042938 | Shvarts | Mar 2003 | A1 |
20030047784 | Matsumoto et al. | Mar 2003 | A1 |
20030057487 | Yamada et al. | Mar 2003 | A1 |
20030057490 | Nagano et al. | Mar 2003 | A1 |
20030102497 | Fried et al. | Jun 2003 | A1 |
20030112659 | Ohsawa | Jun 2003 | A1 |
20030123279 | Aipperspach et al. | Jul 2003 | A1 |
20030146474 | Ker et al. | Aug 2003 | A1 |
20030146488 | Nagano et al. | Aug 2003 | A1 |
20030151112 | Yamada et al. | Aug 2003 | A1 |
20030231521 | Ohsawa | Dec 2003 | A1 |
20040021137 | Fazan et al. | Feb 2004 | A1 |
20040021179 | Lee | Feb 2004 | A1 |
20040029335 | Lee et al. | Feb 2004 | A1 |
20040075143 | Bae et al. | Apr 2004 | A1 |
20040108532 | Forbes | Jun 2004 | A1 |
20040188714 | Scheuerlein et al. | Sep 2004 | A1 |
20040217420 | Yeo et al. | Nov 2004 | A1 |
20040233715 | Umezawa | Nov 2004 | A1 |
20050001257 | Schloesser et al. | Jan 2005 | A1 |
20050001269 | Hayashi et al. | Jan 2005 | A1 |
20050017240 | Fazan | Jan 2005 | A1 |
20050047240 | Ikehashi et al. | Mar 2005 | A1 |
20050062088 | Houston | Mar 2005 | A1 |
20050063224 | Fazan et al. | Mar 2005 | A1 |
20050064659 | Willer | Mar 2005 | A1 |
20050105342 | Tang et al. | May 2005 | A1 |
20050111255 | Tang et al. | May 2005 | A1 |
20050121710 | Shino | Jun 2005 | A1 |
20050135169 | Somasekhar et al. | Jun 2005 | A1 |
20050141262 | Yamada et al. | Jun 2005 | A1 |
20050141290 | Tang et al. | Jun 2005 | A1 |
20050145886 | Keshavarzi et al. | Jul 2005 | A1 |
20050145935 | Keshavarzi et al. | Jul 2005 | A1 |
20050167751 | Nakajima et al. | Aug 2005 | A1 |
20050189576 | Ohsawa | Sep 2005 | A1 |
20050208716 | Takaura et al. | Sep 2005 | A1 |
20050226070 | Ohsawa | Oct 2005 | A1 |
20050232043 | Ohsawa | Oct 2005 | A1 |
20050242396 | Park et al. | Nov 2005 | A1 |
20050265107 | Tanaka | Dec 2005 | A1 |
20060043484 | Cabral et al. | Mar 2006 | A1 |
20060091462 | Okhonin et al. | May 2006 | A1 |
20060098481 | Okhonin et al. | May 2006 | A1 |
20060126374 | Waller et al. | Jun 2006 | A1 |
20060131650 | Okhonin et al. | Jun 2006 | A1 |
20060215477 | Yano et al. | Sep 2006 | A1 |
20060223302 | Chang et al. | Oct 2006 | A1 |
20070008811 | Keeth et al. | Jan 2007 | A1 |
20070023833 | Okhonin et al. | Feb 2007 | A1 |
20070045709 | Yang | Mar 2007 | A1 |
20070058427 | Okhonin et al. | Mar 2007 | A1 |
20070064489 | Bauser | Mar 2007 | A1 |
20070085140 | Bassin | Apr 2007 | A1 |
20070091655 | Oyama et al. | Apr 2007 | A1 |
20070097751 | Popoff et al. | May 2007 | A1 |
20070103975 | Li et al. | May 2007 | A1 |
20070114599 | Hshieh | May 2007 | A1 |
20070133330 | Ohsawa | Jun 2007 | A1 |
20070138524 | Kim et al. | Jun 2007 | A1 |
20070138530 | Okhonin et al. | Jun 2007 | A1 |
20070187751 | Hu et al. | Aug 2007 | A1 |
20070187775 | Okhonin et al. | Aug 2007 | A1 |
20070200176 | Kammler et al. | Aug 2007 | A1 |
20070252205 | Hoentschel et al. | Nov 2007 | A1 |
20070263466 | Morishita et al. | Nov 2007 | A1 |
20070278578 | Yoshida et al. | Dec 2007 | A1 |
20080049486 | Gruening-von Schwerin | Feb 2008 | A1 |
20080083949 | Zhu et al. | Apr 2008 | A1 |
20080099808 | Burnett et al. | May 2008 | A1 |
20080130379 | Ohsawa | Jun 2008 | A1 |
20080133849 | Deml et al. | Jun 2008 | A1 |
20080165577 | Fazan et al. | Jul 2008 | A1 |
20080253179 | Slesazeck | Oct 2008 | A1 |
20080258206 | Hofmann | Oct 2008 | A1 |
20090021984 | Wang | Jan 2009 | A1 |
20090086535 | Ferrant et al. | Apr 2009 | A1 |
20090116286 | Chong et al. | May 2009 | A1 |
20090121269 | Caillat et al. | May 2009 | A1 |
20090127592 | El-Kareh et al. | May 2009 | A1 |
20090201723 | Okhonin et al. | Aug 2009 | A1 |
20100046290 | Park et al. | Feb 2010 | A1 |
20100085813 | Shino | Apr 2010 | A1 |
20100091586 | Carman | Apr 2010 | A1 |
20100110816 | Nautiyal et al. | May 2010 | A1 |
20110019481 | Luthra | Jan 2011 | A1 |
20110019482 | Van Buskirk et al. | Jan 2011 | A1 |
Number | Date | Country |
---|---|---|
272437 | Jul 1927 | CA |
0 030 856 | Jun 1981 | EP |
0 350 057 | Jan 1990 | EP |
0 354 348 | Feb 1990 | EP |
0 202 515 | Mar 1991 | EP |
0 207 619 | Aug 1991 | EP |
0 175 378 | Nov 1991 | EP |
0 253 631 | Apr 1992 | EP |
0 513 923 | Nov 1992 | EP |
0 300 157 | May 1993 | EP |
0 564 204 | Oct 1993 | EP |
0 579 566 | Jan 1994 | EP |
0 362 961 | Feb 1994 | EP |
0 599 506 | Jun 1994 | EP |
0 359 551 | Dec 1994 | EP |
0 366 882 | May 1995 | EP |
0 465 961 | Aug 1995 | EP |
0 694 977 | Jan 1996 | EP |
0 333 426 | Jul 1996 | EP |
0 727 820 | Aug 1996 | EP |
0 739 097 | Oct 1996 | EP |
0 245 515 | Apr 1997 | EP |
0 788 165 | Aug 1997 | EP |
0 801 427 | Oct 1997 | EP |
0 510 607 | Feb 1998 | EP |
0 537 677 | Aug 1998 | EP |
0 858 109 | Aug 1998 | EP |
0 860 878 | Aug 1998 | EP |
0 869 511 | Oct 1998 | EP |
0 878 804 | Nov 1998 | EP |
0 920 059 | Jun 1999 | EP |
0 924 766 | Jun 1999 | EP |
0 642 173 | Jul 1999 | EP |
0 727 822 | Aug 1999 | EP |
0 933 820 | Aug 1999 | EP |
0 951 072 | Oct 1999 | EP |
0 971 360 | Jan 2000 | EP |
0 980 101 | Feb 2000 | EP |
0 601 590 | Apr 2000 | EP |
0 993 037 | Apr 2000 | EP |
0 836 194 | May 2000 | EP |
0 599 388 | Aug 2000 | EP |
0 689 252 | Aug 2000 | EP |
0 606 758 | Sep 2000 | EP |
0 682 370 | Sep 2000 | EP |
1 073 121 | Jan 2001 | EP |
0 726 601 | Sep 2001 | EP |
0 731 972 | Nov 2001 | EP |
1 162 663 | Dec 2001 | EP |
1 162 744 | Dec 2001 | EP |
1 179 850 | Feb 2002 | EP |
1 180 799 | Feb 2002 | EP |
1 191 596 | Mar 2002 | EP |
1 204 146 | May 2002 | EP |
1 204 147 | May 2002 | EP |
1 209 747 | May 2002 | EP |
0 744 772 | Aug 2002 | EP |
1 233 454 | Aug 2002 | EP |
0 725 402 | Sep 2002 | EP |
1 237 193 | Sep 2002 | EP |
1 241 708 | Sep 2002 | EP |
1 253 634 | Oct 2002 | EP |
0 844 671 | Nov 2002 | EP |
1 280 205 | Jan 2003 | EP |
1 288 955 | Mar 2003 | EP |
2 197 494 | Mar 1974 | FR |
H04-176163 | Jun 1922 | JP |
1 414 228 | Nov 1975 | JP |
S62-007149 | Jan 1987 | JP |
S62-272561 | Nov 1987 | JP |
02-294076 | Dec 1990 | JP |
03-171768 | Jul 1991 | JP |
05-347419 | Dec 1993 | JP |
08-213624 | Aug 1996 | JP |
H08-213624 | Aug 1996 | JP |
08-274277 | Oct 1996 | JP |
H08-316337 | Nov 1996 | JP |
09-046688 | Feb 1997 | JP |
09-082912 | Mar 1997 | JP |
10-242470 | Sep 1998 | JP |
11-087649 | Mar 1999 | JP |
2000-247735 | Aug 2000 | JP |
12-274221 | Sep 2000 | JP |
12-389106 | Dec 2000 | JP |
13-180633 | Jun 2001 | JP |
2002-009081 | Jan 2002 | JP |
2002-083945 | Mar 2002 | JP |
2002-094027 | Mar 2002 | JP |
2002-176154 | Jun 2002 | JP |
2002-246571 | Aug 2002 | JP |
2002-329795 | Nov 2002 | JP |
2002-343886 | Nov 2002 | JP |
2002-353080 | Dec 2002 | JP |
2003-031693 | Jan 2003 | JP |
2003-68877 | Mar 2003 | JP |
2003-086712 | Mar 2003 | JP |
2003-100641 | Apr 2003 | JP |
2003-100900 | Apr 2003 | JP |
2003-132682 | May 2003 | JP |
2003-203967 | Jul 2003 | JP |
2003-243528 | Aug 2003 | JP |
2004-335553 | Nov 2004 | JP |
WO 0124268 | Apr 2001 | WO |
WO 2005008778 | Jan 2005 | WO |
Entry |
---|
Arimoto et al., A Configurable Enhanced T2RAM Macro for System-Level Power Management Unified Memory, 2006, VLSI Symposium. |
Arimoto, A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs, Nov. 2007, Solid-State Circuits. |
Asian Technology Information Program (ATIP) Scoops™, “Novel Capacitorless 1T-DRAM From Single-Gate PD-SOI to Double-Gate FinDRAM”, May 9, 2005, 9 pages. |
Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation”, IEEE IEDM, 1994, pp. 809-812. |
Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation”, IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994, pp. 510-512. |
Assaderaghi et al., “A Novel Silicon-On-Insulator (SOI) MOSFET for Ultra Low Voltage Operation”, 1994 IEEE Symposium on Low Power Electronics, pp. 58-59. |
Assaderaghi et al., “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI”, IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, pp. 414-422. |
Assaderaghi et al., “High-Field Transport of Inversion-Layer Electrons and Holes Including Velocity Overshoot”, IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 664-671. |
Avci, Floating Body Cell (FBC) Memory for 16-nm Technology with Low Variation on Thin Silicon and 10-nm Box, Oct. 2008, SOI Conference. |
Bae, Evaluation of 1T RAM using Various Operation Methods with SOONO (Silicon-On-ONO) device, Dec. 2008, IEDM. |
Ban, A Scaled Floating Body Cell (FBC) Memory with High-k+Metal Gate on Thin-Silicon and Thin-Box for 16-nm Technology Node and Beyond, Jun. 2008, VLSI Symposium. |
Ban, Ibrahim, et al., “Floating Body Cell with Independently-Controlled Double Gates for High Density Memory,” Electron Devices Meeting, 2006. IEDM '06. International, IEEE, Dec. 11-13, 2006. |
Bawedin, Maryline, et al., A Capacitorless 1T Dram on SOI Based on Dynamic Coupling and Double-Gate Operation, IEEE Electron Device Letters, vol. 29, No. 7, Jul. 2008. |
Blagojevic et al., Capacitorless IT DRAM Sensing Scheme Automatice Reference Generation, 2006, IEEE J.Solid State Circuits. |
Blalock, T., “A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier”, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 542-548. |
Butt, Scaling Limits of Double Gate and Surround Gate Z-RAM Cells, 2007, IEEE Trans. On El. Dev. |
Chan et al., “Effects of Floating Body on Double Polysilicon Partially Depleted SOI Nonvolatile Memory Cell”, IEEE Electron Device Letters, vol. 24, No. 2, Feb. 2003, pp. 75-77. |
Chan, et al., “SOI MOSFET Design for All-Dimensional Scaling with Short Channel, Narrow Width and Ultra-thin Films”, IEEE IEDM, 1995, pp. 631-634. |
Chi et al., “Programming and Erase with Floating-Body for High Density Low Voltage Flash EEPROM Fabricated on SOI Wafers”, Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 129-130. |
Cho et al., “Novel DRAM Cell with Amplified Capacitor for Embedded Application”, IEEE, Jun. 2009. |
Cho, A novel capacitor-less DRAM cell using Thin Capacitively-Coupled Thyristor (TCCT), 2005, IEDM. |
Choi et al., Current Flow Mechanism in Schottky-Barrier MOSFET and Application to the 1T-DRAM, 2008, SSDM. |
Choi, High Speed Flash Memory and 1T-DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS Device for Multi-functional SoC Applications, Dec. 2008, IEDM. |
Clarke, Junctionless Transistors Could Simply Chip Making, Say Researchers, EE Times, Feb. 2010, www.eetimes.com/showArticle.jhtml?articleID=223100050. |
Colinge, J.P., “An SOI voltage-controlled bipolar-MOS device”, IEEE Transactions on Electron Devices, vol. ED-34, No. 4, Apr. 1987, pp. 845-849. |
Colinge, Nanowire Transistors Without Junctions, Nature NanoTechnology, vol. 5, 2010, pp. 225-229. |
Collaert et al., Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell, 2009, IEEE EDL. |
Collaert, Comparison of scaled floating body RAM architectures, Oct. 2008, SOI Conference. |
Ershov, Optimization of Substrate Doping for Back-Gate Control in SOI T-RAM Memory Technology, 2005, SOI Conference. |
Ertosun et al., A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor Dram: 1T-QW DRAM, 2008, IEEE EDL. |
Fazan et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”, IEEE 2002 Custom Integrated Circuits Conference, Jun. 2002, pp. 99-102. |
Fazan, A Highly Manufacturable Capacitor-less 1T-DRAM Concept, 2002, SPIE. |
Fazan, et al., “Capacitor-Less 1-Transistor DRAM”, 2002 IEEE International SOI Conference, Oct. 2002, pp. 10-13. |
Fazan, P., “MOSFET Design Simplifies DRAM”, EE Times, May 14, 2002 (3 pages). |
Fisch, Beffa, Bassin, Soft Error Performance of Z-RAM Floating Body Memory, 2006, SOI Conference. |
Fisch, Carman, Customizing SOI Floating Body Memory Architecture for System Performance and Lower Cost, 2006, SAME. |
Fisch, Z-RAM® Ultra-Dense Memory for 90nm and Below, 2006, Hot Chips. |
Fossum et al., New Insights on Capacitorless Floating Body DRAM Cells, 2007, IEEE EDL. |
Fujita, Array Architectureof Floating Body Cell (FBC) with Quasi-Shielded Open Bit Line Scheme for sub-40nm Node, 2008, SOI Conference. |
Furuhashi, Scaling Scenario of Floating Body Cell (FBC) Suppressing Vth Variation Due to Random Dopant Fluctuation, Dec. 2008, SOI Conference. |
Furuyama et al., “An Experimental 2-bit/Cell Storage DRAM for Macrocell or Memory-on-Logic Application”, IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 388-393. |
Giffard et al., “ Dynamic Effects in SOI MOSFET's”, IEEE, 1991, pp. 160-161. |
Gupta et al., SPICE Modeling of Self Sustained Operation (SSO) to Program Sub-90nm Floating Body Cells, Oct. 2009, Conf on Simulation of Semiconductor Processes & Devices. |
Han et al., Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM, 2008, IEEE EDL. |
Han et al., Partially Depleted SONOS FinFET for Unified RAM (URAM) Unified Function for High-Speed 1T DRAM and Nonvolatile Memory, 2008, IEEE EDL. |
Han, Energy Band Engineered Unified-RAM (URAM) for Multi-Functioning 1T-DRAM and NVM, Dec. 2008, IEDM. |
Han, Parasitic BJT Read Method for High-Performance Capacitorless 1T-DRAM Mode in Unified RAM, Oct. 2009, IEEE EDL. |
Hara, Y., “Toshiba's DRAM Cell Piggybacks on SOI Wafer”, EE Times, Jun. 2003. |
Hu, C., “SOI (Silicon-on-Insulator) for High Speed Ultra Large Scale Integration”, Jpn. J. Appl. Phys. vol. 33 (1994) pp. 365-369, Part 1, No. 1B, Jan. 1994. |
Idei et al., “Soft-Error Characteristics in Bipolar Memory Cells with Small Critical Charge”, IEEE Transactions on Electron Devices, vol. 38, No. 11, Nov. 1991, pp. 2465-2471. |
Ikeda et al., “3-Dimensional Simulation of Turn-off Current in Partially Depleted SOI MOSFETs”, IEIC Technical Report, Institute of Electronics, Information and Communication Engineers, 1998, vol. 97, No. 557 (SDM97 186-198), pp. 27-34. |
Inoh et al., “FBC (Floating Body Cell) for Embedded DRAM on SOI”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003 (2 pages). |
Iyer et al., “SOI MOSFET on Low Cost SPIMOX Substrate”, IEEE IEDM, Sep. 1998, pp. 1001-1004. |
Jang et al., Highly scalable Z-RAM with remarkably long data retention for DRAM application, Jun. 2009, VLSI. |
Jeong et al., “A Capacitor-less 1T DRAM Cell Based on a Surrounding Gate MOSFET with Vertical Channel”, Technology Development Team, Technology Development Team, Samsung Electronics Co., Ltd., May 2007. |
Jeong et al., “A New Capacitorless 1T DRAm Cell: Surrounding Gate MOSFET with Vertical Channel (SGVC Cell)”, IEEE Transactions on Nanotechnology, vol. 6, No. 3, May 2007. |
Jeong et al., “Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure”, Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, pp. 574-575, Yokohama (2006). |
Jeong et al., “Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure”, Japanese Journal of Applied Physics, vol. 46, No. 4B, pp. 2143-2147 (2007). |
Kedzierski, J.; “Design Analysis of Thin-Body Silicide Source/Drain Devices”, 2001 IEEE International SOI Conference, Oct. 2001, pp. 21-22. |
Kim et al., “Chip Level Reliability on SOI Embedded Memory”, Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 135-139. |
Kuo et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications”, IEEE IEDM, Feb. 2002, pp. 843-846. |
Kuo et al., “A Capacitorless Double-Gate DRAM Cell”, IEEE Electron Device Letters, vol. 23, No. 6, Jun. 2002, pp. 345-347. |
Kuo et al., A Capacitorless Double Gate DRAM Technology for Sub 100 nm Embedded and Stand Alone Memory Applications, 2003, IEEE Trans. On El. Dev. |
Kwon et al., “A Highly Scalable 4F2 DRAm Cell Utilizing a Doubly Gated Vertical Channel”, Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials, UC Berkley, pp. 142-143 Sendai (2009). |
Lee et al., “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMs”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 114-115. |
Leiss et al., dRAM Design Using the Taper-Isolated Dynamic RAM Cell, IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 707-714. |
Lin et al., “Opposite Side Floating Gate SOI FLASH Memory Cell”, IEEE, Mar. 2000, pp. 12-15. |
Liu et al., Surface Generation-Recombination Processes of Gate and STI Oxide Interfaces Responsible for Junction Leakage on SOI, Sep. 2009, ECS Transactions, vol. 25. |
Liu, Surface Recombination-Generation Processes of Gate, STI and Buried Oxide Interfaces Responsible for Junction Leakage on SOI, May 2009, ICSI. |
Lon{hacek over (c)}ar et al., “One of Application of SOI Memory Cell—Memory Array”, IEEE Proc. 22nd International Conference on Microelectronics (MIEL 2000), vol. 2, NI{hacek over (S)}, Serbia, May 14-17, 2000, pp. 455-458. |
Lu et al., A Novel Two-Transistor Floating Body/Gate Cell for Low Power Nanoscale Embedded DRAM, 2008, IEEE Trans. On El. Dev. |
Ma, et al., “Hot-Carrier Effects in Thin-Film Fully Depleted SOI MOSFET's”, IEEE Electron Device Letters, vol. 15, No. 6, Jun. 1994, pp. 218-220. |
Malhi et al., “Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon”, IEEE Transactions on Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 258-281. |
Malinge, An 8Mbit DRAM Design Using a 1TBulk Cell, 2005, VLSI Circuits. |
Mandelman et al, “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 136-137. |
Matsuoka et al., FBC Potential of 6F2 Single Cell Operation in Multi Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin, 2007, IEDM. |
Minami, A Floating Body Cell (FBC) fully Compatible with 90nm CMOS Technology(CMOS IV) for 128Mb SOI DRAM, 2005, IEDM. |
Mohapatra et al., Effect of Source/Drain Asymmetry on the Performance of Z-RAMÓ Devices, Oct. 2009, SOI conference. |
Morishita, A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI, 2005, CICC. |
Morishita, F. et al., “A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory”, IEEE Journal of Solid-State Circuits, vol. 42, No. 4, pp. 853, Apr. 2007. |
Morishita, F., et al., “A 312-MHz 16-Mb Random-Cycle Embedded DRAM Macro With a Power-Down Data Retention Mode for Mobile Applications”, J. Solid-State Circuits, vol. 40, No. 1, pp. 204-212, 2005. |
Morishita, F., et al., “Dynamic floating body control SOI CMOS for power managed multimedia ULSIs”, Proc. CICC, pp. 263-266, 1997. |
Morishita, F., et al., “Leakage Mechanism due to Floating Body and Countermeasure on Dynamic Retention Mode of SOI-DRAM”, Symposium on VLSI Technology Digest of Technical Papers, pp. 141-142, 1995. |
Nagoga, Studying of Hot Carrier Effect in Floating Body Soi Mosfets by The Transient Charge Pumping Technique, Switzerland 2003. |
Nayfeh, A Leakage Current Model for SOI based Floating Body Memory that Includes the Poole-Frenkel Effect, 2008, SOI Conference. |
Nemati, A Novel High Density, Low Voltage SRAM Cell with a Vertical NDR Device, 1998, VLSI Tech. Symp. |
Nemati, A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-scale Memories, 1999, IEDM Conference. |
Nemati, Embedded Volatile Memories-Embedded Tutorial: The New Memory Revolution, New Drives Circuits and Systems, ICCAD 2008, Nov. 2008. |
Nemati, Fully Planar 0.562μm2 T-RAM Cell in a 130nm SOI CMOS Logic Technology for High-Density High-Performance SRAMs, 2004, IEDM. |
Nemati, The New Memory Revolution. New Devices, Circuits and Systems, 2008, ICCAD. |
Nemati, Thyristor RAM (T-RAM): A High-Speed High-Density Embedded Memory Technology for Nano-scale CMOS, 2007, Hot Chips. |
Nemati, Thyristor-RAM: A Novel Embedded Memory Technology that Outperforms Embedded S RAM/DRAM, 2008, Linley Tech Tour. |
Nishiguchi et al., Long Retention of Gain-Cell Dynamic Random Access Memory with Undoped Memory Node, 2007, IEEE EDL. |
Oh, Floating Body DRAM Characteristics of Silicon-On-ONO (SOONO) Devices for System-on-Chip (SoC) Applications, 2007, VLSI Symposium. |
Ohno et al., “Suppression of Parasitic Bipolar Action in Ultra-Thin-Film Fully-Depleted CMOS/SIMOX Devices by Ar-Ion Implantation into Source/Drain Regions”, IEEE Transactions on Electron Devices, vol. 45, No. 5, May 1998, pp. 1071-1076. |
Ohsawa et al., “A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003 (4 pages). |
Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522. |
Ohsawa, A 128Mb Floating Body RAM (FBRAM) on SOI with a Multi-Averaging Scheme of Dummy Cell, 2006 Symposium of VLSI Circuits Digest of Tech Papers, (2006). |
Ohsawa, An 18.5ns 128Mb SOI DRAM with a Floating Body Cell, 2005, ISSCC. |
Ohsawa, Autonomous Refresh of Floating Body Cell (FBC), Dec. 2008, IEDM. |
Ohsawa, Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC), Jan. 2006, Solid-State Circuits. |
Okhonin, A Capacitor-Less 1T-DRAM Cell, Feb. 2002, Electron Device Letters. |
Okhonin, A SOI Capacitor-less 1T-DRAM Concept, 2001, SOI Conference. |
Okhonin, Charge Pumping Effects in Partially Depleted SOI MOSFETs, 2003, SOI Conference. |
Okhonin, New characterization techniques for SOI and related devices, 2003, ECCTD. |
Okhonin, New Generation of Z-RAM, 2007, IEDM. |
Okhonin, Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs, May 2002, Electron Device Letters. |
Okhonin, Transient Charge Pumping for Partially and Fully Depleted SOI MOSFETs, 2002, SOI Conference. |
Okhonin, Transient effects in PD SOI MOSFETs and potential DRAM applications, 2002, Solid-State Electronics. |
Okhonin, Ultra-scaled Z-RAM cell, 2008, SOI Conference. |
Okhonin, Z-RAM® (Limits of DRAM), 2009, ESSDERC. |
Padilla, Alvaro, et al., “Feedback FET: A Novel Transistor Exhibiting Steep Switching Behavior at Low Bias Voltages,” Electron Devices Meeting, 2008. IEDM 2008. IEEE International, Dec. 5-17, 2008. |
Park, Fully Depleted Double-Gate 1T-DRAM Cell with NVM Function for High Performance and High Density Embedded DRAM, 2009, IMW. |
Pelella et al., “Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in PD/SOI MOSFETs”, Final Camera Ready Art, SOI Conference, Oct. 1995, 2 pages. |
Portmann et al., “A SOI Current Memory for Analog Signal Processing at High Temperature”, 1999 IEEE International SOI Conference, Oct. 1999, pp. 18-19. |
Puget et al., 1T Bulk eDRAM using GIDL Current for High Speed and Low Power applications, 2008, SSDM. |
Puget et al., Quantum effects influence on thin silicon film capacitor-less DRAM performance, 2006, SOI Conference. |
Puget, FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications, 2009, IMW. |
Ranica et al., 1T-Bulk DRAM cell with improved performances: the way to scaling, 2005, ICMTD. |
Ranica, A capacitor-less DRAM cell on 75nm gate length, 16nm thin Fully Depleted SOI device for high density embedded memories, 2004, IEDM. |
Ranica, A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAM, 2004, VLSI Symposium. |
Rodder et al., “Silicon-On-Insulator Bipolar Transistors”, IEEE Electron Device Letters, vol. EDL-4, No. 6, Jun. 1983, pp. 193-195. |
Rodriguez, Noel, et al., A-RAM Novel Capacitor-less Dram Memory, SOI Conference, 2009 IEEE International, Oct. 5-8, 2009 pp. 1-2. |
Roy, Thyristor-Based Volatile Memory in Nano-Scale CMOS, 2006, ISSCC. |
Sailing et al., Reliability of Thyristor Based Memory Cells, 2009, IRPS. |
Sasaki et al., Charge Pumping in SOS-MOS Transistors, 1981, IEEE Trans. On El. Dev. |
Sasaki et al., Charge Pumping SOS-MOS Transistor Memory, 1978, IEDM. |
Schloesser et al., “A 6F2 Buried Wordline DRAM Cell for 40nm and Beyond”, IEEE, Qimonda Dresden GmbH & Co., pp. 809-812 (2008). |
Shino et al., Floating Body RAM technology and its scalability to 32 nm node and beyond, 2006, IEDM. |
Shino et al., Operation Voltage Dependence of Memory Cell Characteristics in Fully Depleted FBC, 2005, IEEE Trans. On El. Dev. |
Shino, Fully-Depleted FBC (Floating Body Cell) with Enlarged Signal Window and Excellent Logic Process Compatibility, 2004, IEDM. |
Shino, Highly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications, 2004, VLSI Symposium. |
Sim et al., “Source-Bias Dependent Charge Accumulation in P+ -Poly Gate SOI Dynamic Random Access Memory Cell Transistors”, Jpn. J. Appl. Phys. vol. 37 (1998) pp. 1260-1263, Part 1, No. 3B, Mar. 1998. |
Singh, A 2ns-Read-Latency 4Mb Embedded Floating-Body Memory Macro in 45nm SOI Technology, Feb. 2009, ISSCC. |
Sinha et al., “In-Depth Analysis of Opposite Channel Based Charge Injection in SOI MOSFETs and Related Defect Creation and Annihilation”, Elsevier Science, Microelectronic Engineering 28, 1995, pp. 383-386. |
Song, 55 nm Capacitor-less 1T DRAM Cell Transistor with Non-Overlap Structure, Dec. 2008, IEDM. |
Stanojevic et al., “Design of a SOI Memory Cell”, IEEE Proc. 21st International Conference on Microelectronics (MIEL '97), vol. 1, NIS, Yugoslavia, Sep. 14-17, 1997, pp. 297-300. |
Su et al., “Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD”, IEEE Proceedings of the International Symposium on Quality Electronic Design (ISQED '02), Apr. 2002 (5 pages). |
Suma et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”, 1994 IEEE International Solid-State Circuits Conference, pp. 138-139. |
Tack et al., “The Multi-Stable Behaviour of SOI-NMOS Transistors at Low Temperatures”, Proc. 1988 SOS/SOI Technology Workshop (Sea Palms Resort, St. Simons Island, GA, Oct. 1988), p. 78. |
Tack et al., “The Multistable Charge Controlled Memory Effect in SOI Transistors at Low Temperatures”, IEEE Workshop on Low Temperature Electronics, Aug. 7-8, 1989, University of Vermont, Burlington, pp. 137-141. |
Tack et al., “The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, No. 5, May 1990, pp. 1373-1382. |
Tack, et al., “An Analytical Model for the Misis Structure in SOI MOS Devices”, Solid-State Electronics vol. 33, No. 3, 1990, pp. 357-364. |
Tanaka et al., “Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FINDRAM”, 2004 IEEE, 4 pages. |
Tang, Poren, Highly Scalable Capacitorless DRAM Cell on Thin-Body with Band-gap Engineered Source and Drain, Extended Abstracts of the 2009 ICSSDM, Sendai, 2009, pp. 144-145. |
Terauchi et al., “Analysis of Floating-Body-Induced Leakage Current in 0.15μ m SOI DRAM”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 138-139. |
Thomas et al., “An SOI 4 Transistors Self-Refresh Ultra-Low-Voltage Memory Cell”, IEEE, Mar. 2003, pp. 401-404. |
Tomishima, et al., “A Long Data Retention SOI DRAM with the Body Refresh Function”, IEICE Trans. Electron., vol. E80-C, No. 7, Jul. 1997, pp. 899-904. |
Tsaur et al., “Fully Isolated Lateral Bipolar-MOS Transistors Fabricated in Zone-Melting-Recrystallized Si Films on SiO2”, IEEE Electron Device Letters, vol. EDL-4, No. 8, Aug. 1983, pp. 269-271. |
Tu, et al., “Simulation of Floating Body Effect in SOI Circuits Using BSIM3SOI”, Proceedings of Technical Papers (IEEE Cat No. 97TH8303), Jun. 1997, pp. 339-342. |
Villaret et al., “Mechanisms of Charge Modulation in the Floating Body of Triple-Well nMOSFET Capacitor-less DRAMs”, Proceedings of the INFOS 2003, Insulating Films on Semiconductors, 13th Bi-annual Conference, Jun. 18-20, 2003, Barcelona (Spain), (4 pages). |
Villaret et al., “Triple-Well nMOSFET Evaluated as a Capacitor-Less DRAM Cell for Nanoscale Low-Cost & High Density Applications”, Handout at Proceedings of 2003 Silicon Nanoelectronics Workshop, Jun. 8-9, 2003, Kyoto, Japan (2 pages). |
Villaret et al., Further Insight into the Physics and Modeling of Floating Body Capacitorless DRAMs, 2005, IEEE Trans. On El. Dev. |
Wang et al., A Novel 4.5F2 Capacitorless Semiconductor Memory Device, 2008, IEEE EDL. |
Wann et al., “A Capacitorless DRAM Cell on SOI Substrate”, IEEE IEDM, 1993, pp. 635-638. |
Wann et al., “High-Endurance Ultra-Thin Tunnel Oxide in MONOS Device Structure for Dynamic Memory Application”, IEEE Electron Device Letters, vol. 16, No. 11, Nov. 1995, pp. 491-493. |
Wei, A., “Measurement of Transient Effects in SOI DRAM/SRAM Access Transistors”, IEEE Electron Device Letters, vol. 17, No. 5, May 1996, pp. 193-195. |
Wouters, et al., “Characterization of Front and Back Si-SiO2 Interfaces in Thick- and Thin-Film Silicon-on-Insulator MOS Structures by the Charge-Pumping Technique”, IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, pp. 1746-1750. |
Wu, Dake, “Performance Improvement of the Capacitorless DRAM Cell with Quasi-SOI Structure Based on Bulk Substrate,” Extended Abstracts of the 2009 ICSSDM, Sendai, 2009, pp. 146-147. |
Yamanaka et al., “Advanced TFT SRAM Cell Technology Using a Phase-Shift Lithography”, IEEE Transactions on Electron Devices, vol. 42, No. 7, Jul. 1995, pp. 1305-1313. |
Yamauchi et al., “High-Performance Embedded SOI DRAM Architecture for the Low-Power Supply”, IEEE Journal of Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp. 1169-1178. |
Yamawaki, M., “Embedded DRAM Process Technology”, Proceedings of the Symposium on Semiconductors and Integrated Circuits Technology, 1998, vol. 55, pp. 38-43. |
Yang, Optimization of Nanoscale Thyristors on SOI for High-Performance High-Density Memories, 2006, SOI Conference. |
Yoshida et al., “A Design of a Capacitorless 1-T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-Power and High-speed Embedded Memory”, 2003 IEEE, 4 pages. |
Yoshida et al., “A Study of High Scalable DG-FinDRAM”, IEEE Electron Device Letters, vol. 26, No. 9, Sep. 2005, pp. 655-657. |
Yoshida et al., A Capacitorless 1T-DRAM Technology Using GIDL Current for Low Power and High Speed Embedded Memory, 2006, IEEE Trans. On El. Dev. |
Yu et al., Hot-Carrier Effect in Ultra-Thin-Film (UTF) Fully-Depleted SOI MOSFET's, 54th Annual Device Research Conference Digest (Cat. No. 96TH8193), Jun. 1996, pp. 22-23. |
Yu et al., “Hot-Carrier-Induced Degradation in Ultra-Thin-Film Fully-Depleted SOI MOSFETs”, Solid-State Electronics, vol. 39, No. 12, 1996, pp. 1791-1794. |
Yu et al., “Interface Characterization of Fully-Depleted SOI MOSFET by a Subthreshold I-V Method”, Proceedings 1994 IEEE International SOI Conference, Oct. 1994, pp. 63-64. |
Yun et al., Analysis of Sensing Margin in SOONO Device for the Capacitor-less RAM Applications, 2007, SOI Conference. |
Zhou, Physical Insights on BJT-Based 1t DRAM Cells, IEEE Electron Device Letters, vol. 30, No. 5, May 2009. |
Tanabe et al., A 30-ns 64-MB DRAM with Built-in-Self-Test and Self-Repair Function, IEEE Journal of Solid State Circuits, vol. 27, No. 11, pp. 1525-1533, Nov. 1992. |
Ban et at, Integration of Back-Gate Doping for 15-nm Node Floating Body Cell (FBC) Memory, Components Research, Process Technology Modeling, presented in the 2010 VLSI Symposium on Jun. 17, 2010. |
Number | Date | Country | |
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20100271857 A1 | Oct 2010 | US |
Number | Date | Country | |
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61173014 | Apr 2009 | US |