Patent Application
20080054358
a, 2b, 2c and 2d are explanatory drawings illustrating a process for manufacturing films on the substrate on which conductive line pattern has been formed.
a, 3b, 3c and 3d are sectional views illustrating a cross sectional view of the embodiment of a method of manufacturing a thin film transistor pertaining to the present invention.
a, 4b, 4c and 4d are plan views illustrating an embodiment of a method of the manufacturing a thin film transistor of the present invention.
a and 5b are explanatory drawings illustrating the directions of a first discharging electrode 4 and a conductive line pattern when manufacturing a thin film.
The present invention will be described in detail by referring to embodiments of the present invention. However, the present invention is not limited to these embodiments.
A thin film is manufactured by a plasma film manufacturing process under the atmospheric pressure in this invention. The plasma film manufacturing process under the atmospheric pressure will be described hereinafter.
The plasma film manufacturing process under the atmospheric pressure means a process for forming a thin film on a substrate by causing discharge and exciting discharge gas to form plasma under the atmospheric pressure or the pressure close to the atmospheric pressure. The method thereof is disclosed in Unexamined Japanese Patent Publications Nos. 2003-179234, 2004-207331, H11-133205, 2000-185362, H11-61406, 2000-147209 and 2000-121804. This is named, an atmospheric pressure plasma method.
The film manufacturing apparatus 50 is configured by a high frequency power source 9, a discharge adjustment apparatus 6 and a film manufacturing apparatus case 5.
The first end of the high frequency power source 9 is connected to a first discharge electrode 4 in the film manufacturing apparatus case 5 through the discharge adjustment apparatus 6. A second discharge electrode 1 is disposed against the first discharge electrode 4 in the film manufacturing apparatus case 5. The second discharge electrode 1 is connected to the second end of the high frequency power source 9, which is grounded.
The high frequency power source 9 supplies power for causing discharge between the first discharge electrode 4 and the second discharge electrode 1. The voltage for starting discharge is, for example, equal to or more than 500V. The discharge adjustment apparatus 6 is provided for impedance matching between the high frequency power supply 9 and the first discharge electrode 4. In the discharge adjustment apparatus 6 (not shown), for example, a tuning coil and a tuning condenser are connected in parallel to adjust them to be an optimum impedance. The discharge power is appropriate within the range where glow-discharge keeps occurring, the range being set, for example, 100 W-800 W.
The method for supplying high frequency power between the first discharge electrode 4 and the second discharge electrode 1 is not limited to an embodiment where the power is supplied from the high frequency power source 9. It may also be possible to conduct discharge by separately connecting respective high frequency power sources with the first discharge electrode 4 and the second discharge electrode 1 and utilizing the voltage difference between the ground and respective electrodes.
A space, which is indicated by an arrow G1, as illustrated in
In this embodiment, an embodiment including a single first discharge electrode 4 will be described. However, an embodiment including a plurality of first discharge electrodes 4, where gas is injected into the space formed between the plurality of first discharge electrodes 4 may be possible.
The film manufacturing apparatus 50 can generate plasma by starting discharges under the atmospheric pressure or the pressure close thereto. The atmospheric pressure or the pressure close thereto denotes pressure of about 20 kPa-110 kPa, preferably about 93 kPa-104 kPa.
The second discharge electrode 1 is fixed onto the support table 10, which is capable of being reciprocally moved along an arrow S of
In this embodiment, an example including the second discharge electrode 1 having a flat surface as shown in
Next, the process for forming a film onto the substrate having a conductive line pattern by using the film formation apparatus 50, which is illustrated in
a and 2c are plan views illustrating the substrate 2 viewed from the upper surface side.
a and 2b are drawings illustrating the substrate 2, on which conductive line patters 12 having a line width W with equal interval x have been formed.
In this invention, a glass substrate having a resistibility of not less than 10−8 Ω·cm, which is called an insulator, in general, or a flexible resin sheet can be used as the substrate 2. Or there can be used a substrate having a conductive pattern thereon, on the surface of which an insulation material having a resistibility of not less than 10−8 Ω·cm is coated such that the thickness of coating layer is not less than 0.1 mm to give insulation to the surface of the substrate.
The conductive line pattern 12 is formed by material having a resistibility of not more than 10−2 Ω·cm by using a direct patterning technique, such as a photo-lithography process, IJ method and a screen print method, onto the substrate 2.
The substrate 2 on which the conductive line pattern 12 has been formed is placed onto the second discharge electrode 1 in the film manufacturing apparatus 50.
Next, a surface roughness Ra of the thin film 40 will be described.
When forming a thin film 40 onto the substrate 2 by using the film manufacturing apparatus 50, in case where the line width W of the conductive line pattern 12 on the substrate 2 becomes larger with respect to the spatial distance L between the lower surface of the first discharge electrode 4 and the substrate 2, the disorder of the discharge tends to occur and there comes a situation where a thin film formation having a uniform film quality cannot be achieved. Accordingly, the surface roughness Ra of the formed thin film becomes large. Suppose that the width of the conductive line pattern is to be W, and the spatial distance between the lower surface of the first discharge electrode 4 and the substrate 2 of the film manufacturing apparatus 50 is to be L, the thin film surface roughness Ra depends on the space ratio (W/L). The space ratio (W/L) to obtain a uniform film thickness needs to be not more than 0.1, which will be described by using an embodiment. In order to realize that the space ratio (W/L) to be not more than 0.1, the line width W of the conductive line pattern 12 may be designed corresponding to the spatial distance L or the spatial distance may be adjusted corresponding to the line width W.
In an example where the second discharge electrode 1 having a flat surface is placed so as to be parallel with the first discharge element 4, the distance between them is always the same, which is the spatial distance L as shown in
Next, a method for manufacturing a thin film transistor by employing the method for manufacturing a thin film of the present invention will be described.
a, 3b 3c and 3d are cross sectional views illustrating an embodiment of the method of manufacturing a thin film transistor pertaining to the present invention.
Processes S0-S4 for a bottom gate type thin film transistor will be described as an example of a method for manufacturing the thin film transistor pertaining to the present invention will be described. S0: a process for forming a gate electrode 17, S1: a process for forming a gate insulation layer 14, S2: a process for manufacturing a source electrode and a drain electrode, S3: a process for manufacturing a film of semiconductor layer 18, and S4: a process for manufacturing a film of a semiconductor protective layer.
Respective processes will be described hereinafter.
S0: A process for forming the gate electrode 17
The material of the substrate 2 will not be limited. For example, glass or a flexible resin sheet may be used as the substrate 2. After having coated photo-resist onto the substrate 2 on which a conductive thin film has been formed, exposure through a photo-mask and a development process is conducted. The conductive line pattern 12 as illustrated in
In
W: a line width of conductive line pattern 12.
x: an interval between conductive line patterns 12.
The line width of conductive line pattern 12 “W” is arranged so that the space ratio (W/L) becomes not more than 0.1 as described in
S1: A process for forming the gate insulation layer 14
Next, the gate insulation layer 14 is formed on the entire surface of the substrate 2.
The film manufacturing apparatus 50 forms the gate insulation layer 14 by a plasma manufacturing film under the atmospheric pressure or the pressure closed thereto.
In this embodiment, an example for manufacturing a SiO2 film, which is an insulation film, as the gate insulation layer 14 will be described. With respect to the material of the SiO2, TEOS (Tetraethoxysilane) is used. A gas formed by bubbling TEOS with the same kind of discharge gas as a discharge gas and by vaporizing thereof is used as a source gas. Argon is used as the discharge gas in this embodiment. Further, for example, O2 is used as a reactant gas.
Source gas, discharge gas and reactant gas are not limited to ones described above, and should be determined corresponding to the kind of the film to be formed.
For example, rare gas, such as, Argon, Helium, Neon and Xenon can be used as discharge gas. However, from the cost reduction point of view, Argon is preferable. Further, instead of the rare gas described above, Oxygen, Nitrogen, Carbon dioxide and Hydrogen may be used. However, Nitrogen is preferably used from the cost reduction point of view.
Regarding the source gas for forming a gate insulation layer 14, for example, Organometallic chemical compound, Halogen chemical compound and Metal-Hydrogen chemical compound can be sued. From handling point of view, since the risk of explosion is low, organometallic compound is preferably used. Particularly, the organometallic compound including oxygen not less than 1 in a molecule preferably used.
With respect to the organometallic compound, which may be used to form an insulation layer, for example, Tetraethlsilane, Tetramethylsilane, Tetraethoxysilane (TEOS), Tetramethoxysilane (TMOS), Tetramethoxysilan (TMS), Trimethylefluososilane (4MS), Hexamethyldisiloxane (HMDSO) may be used.
S2: A process for manufacturing a source electrode and a drain electrode
As illustrated in
In
a: Length of the drain electrode 16
b: Width of the drain electrode 16
c: Distance between the drain electrode 16 and the source electrode 15a
d: Distance between the source line 15b and the drain electrode 16
e: Length of the portion extended from the source line 15b of the source electrode 15a
f: Width of the source electrode 15a
g: Width of the source line 15b
y: Interval between the source lines 15b
S3: Process for manufacturing a film of semiconductor layer
As illustrated in
In this invention, the semiconductor material is not limited to special one. There can be employed materials from inorganic semiconductor, such as Amorphous Silicon, to organic semiconductor, such as Pentacene. With respect to the method for forming a film, it is not limited to an inkjet method, a coating method and an evaporation method.
S4: A process for manufacturing a film of a semiconductor protective layer
As illustrated in
After that, a contact hole for contacting the drain electrode 16 is made in the semiconductor protective layer 19, and a pixel electrode for contacting with the contact hole is formed by the coating type ITO to compete the organic TFT.
Examples to confirm effects of the present invention will be described hereinafter. However, the present invention is not limited to these examples.
In this example, the conductive line patterns as illustrated in
A thin film of SiO2 has been formed onto the substrate 2 on which the conductive line pattern 12 has been formed, by using the film manufacturing apparatus 50, which has been explained by referring to
In the cases where the spatial distance L between the lower surface of the first discharge electrode 4 and the substrate 2 are 0.5 mm, 1 mm and 1.5 mm, SiO2 thin films have been formed on the substrate 2 with the line width of the SiO2 thin film varied corresponding to the space ratio (W/L). And the surface roughness for respective cases has been measured. The discharge power between the first discharge electrode 4 and the second discharge electrode 1 was 500 W, and the atmospheric pressure was 100 kPa.
a and 5b are explanatory drawings for illustrating drawings for explaining the directions of a first discharging electrode 4 and the conductive line pattern 12 when manufacturing the thin film. As illustrated in
TEOS (Tetraethoxysilane) has been used as a material of SiO2 film, and the gas into which TEOS has been bubbled with the same kind of gas as the discharge gas and evaporated has been used as the source gas. The discharge gas was Argon and the reactant gas was O2. With regard to the gas flow amount, the source gas is 5 (L/min.), the discharge gas is 20 (L/min.) and the reactant gas is 0.1 (L/min.).
[Experimental Results]
According to
A bottom gate type thin film transistor has been formed on the substrate 2, the number of the bottom gate type thin film transistors on the substrate 2 being total 100, which comes from 10×10 on the substrate 2, by using the film manufacturing apparatus 50.
In the cases where the spatial distance L between the lower surface of the first discharge electrode 4 and the substrate 2 are set 0.5 mm, 1 mm and 1.5 mm, the relationship between the space ratio and the mobility has been obtained by using the substrate 2 where the line width W has been varied corresponding to the space ratio (W/L).
The atmospheric pressure was 100 kPa when forming the film by the plasma method.
[Manufacturing of Thin Film Transistor]
The substrate 2 is a substrate having a size of 100 mm×100 mm, Polyethersulfone substrate of Sumitomo Bakelite Co., Ltd.
Since the film transistor has been formed on the process S0-S4 of the embodiment 1, which has been explained by referring to
S0: A process for forming a gate electrode 17
By coating photo-resist onto the substrate 2 on which a conductive thin film has been formed and conducting exposure through a photo-mask, the conductive line pattern 12 has been formed. The interval “x” of the formed line patterns 12 formed of the conductive thin film is 350 μm. In case where the spatial distance L is 0.5 mm, 1 mm and 1.5 mm, there has been made and test the substrate 2, on which the line width W is varied so that the space ratio (W/L) became seven values of 0.02, 0.05, 0.08, 0.1, 0.11, 0.15 and 0.2.
S1: A process for forming a gate insulation layer 14
The film manufacturing apparatus 50 forms the gate insulation layer 14 structured by SiO2.
With regard to the source gas of SiO2, a gas, into which TEOS (Tetraethoxysilane) has been bubbled with the same kind of gas as the discharge gas and evaporated, has been used. The discharge gas was Argon and the reactant gas was O2. With respect to the gas flow amount, the source gas is 5 (L/min.), the discharge gas is 20 (L/min.) and the reactant gas is 0.1 (L/min.). The discharge power between the first discharge electrode 4 and the second discharge electrode 1 is 500 W.
S2: A process for forming a source electrode and a drain electrode
The electrode illustrated in
The dimensions of respective sections of this embodiment illustrated in
Length a of the drain electrode 16: 150 μm
Width of the drain electrode 16: 50 μm
Distance c between the drain electrode 16 and the source electrode 15a: 10 μm
Distance d between the source line 15b and the drain electrode 16: 5 μm
Length e of the part extended from a source line 15b of the source electrode 15a: 155 μm
Width f of the source electrode 15b: 50 μm
Width g of the source line 15b: 50 μm
Interval between the source lines 15b: 350 μm
S3: A process for manufacturing a semiconductor layer 18
Film is formed by a vacuum evaporation method of Pentacene.
S4: A process for manufacturing a semiconductor layer 19
The film manufacturing apparatus 50 forms the semiconductor protective layer 19 structured by SiO2.
With regard to the source gas of SiO2, a gas, into which TEOS (Tetraethoxysilane) has been bubbled with the same kind of gas as the discharge gas and evaporated, has been used. The discharge gas was Argon and the reactant gas was O2. With regard to the gas flow amount, the source gas is 5 (L/min.), the discharge gas is 20 (L/min.) and the reactant gas is 0.1 (L/min.). The discharge power between the first discharge electrode 4 and the second discharge electrode 1 is 500 W.
After that, a contact hole for contacting the drain electrode 16 was made in the semiconductor protective layer 19 and a pixel electrode for contacting with the contact hole was formed by the coating type ITO to complete the organic TFT.
[Experimental Results]
The experimental results are shown in
According to
The reason is thought to be as follows. When the surface roughness of the gate insulation layer 14 becomes large, there is increased the number of starting points, from which the film grows when forming a film of a semiconductor material, accordingly, crystal size (grain size) of the semiconductor material becomes small. Thus, it is thought that when the crystal size becomes small, since the boundary surface (particle surface) between crystal particles, which interferes carriers to move, increase, the value of the mobility of a formed thin film transistor decreases.
As described above, since when the space ratio (W/L) is set not more than 0.1, the surface roughness of the gate insulating layer 14 can be controlled small, and the thin film transistor having high mobility can be manufactured.
A method of manufacturing a thin film of the present invention can be adopted by the manufacturing process of the semiconductor integrated circuit and by the process where forming conductive line pattern on a substrate, such as a printed circuit board (PCB) or a flexible printed circuit board (FPC), where a conductive layer and an insulation layer are alternatively layered.
As described above, according to the present invention, by setting the ratio of the line width W of a conductive line pattern on the substrate on which a thin film is formed to a spatial distance L not more than 0.1, there can be provided a method for stably manufacturing a thin film having a uniform thickness even on a substrate having a conductive line pattern, a method of manufacturing a thin film transistor having a superior characteristic and a thin film transistor.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP2006-231825 | Aug 2006 | JP | national |
| JP2007-174957 | Jul 2007 | JP | national |
