Patent Application
20230098467
Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, thin film transistors having a spin-on two-dimensional (2D) channel material.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.
For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.
The performance of a thin-film transistor (TFT) may depend on a number of factors. For example, the efficiency at which a TFT is able to operate may depend on the sub threshold swing of the TFT, characterizing the amount of change in the gate-source voltage needed to achieve a given change in the drain current. A smaller sub threshold swing enables the TFT to turn off to a lower leakage value when the gate-source voltage drops below the threshold voltage of the TFT. The conventional theoretical lower limit at room temperature for the sub threshold swing of the TFT is 60 millivolts per decade of change in the drain current.
Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the, e.g., 13 nm or sub-13 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.
Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, “below,” “bottom,” and “top” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.
Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.
One or more embodiments described herein are directed to spin-on two-dimensional (2D) transition metal dichalcogenide (TMD) growth. Embodiments may include or pertain to one or more of front end transistors, back end transistors, thin film transistors, or system-on-chip (SoC) technologies.
To provide context, conventional use of metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) uses precursors of both metal and chalcogenide. The quality of growth tends to lead to smaller crystals with more defects and contamination.
In accordance with one or more embodiments described herein, by utilizing a spin-on metal solution, only exposure of the solution to a chalcogenide gas is needed, completely removing the need for a metal gas source. Approaches described herein can be implemented to reduce or altogether eliminate unwanted contamination and can lead to relatively much larger crystal growth and quality. This, in turn, can lead to higher performing devices at smaller dimensions. Embodiments described herein include new synthesis techniques for 2D materials. Embodiments described herein include approaches to realize high quality large grain 2D materials. Conventional MOCVD uses organic plus H2S (or Se); by contrast, in an embodiment, a solution of ammonia metatungstate (AMT) or ammonia heptamolybdate (AHM) plus H2S (or Se) is used to fabricate a 2D TMD material layer or film. In one embodiment, sodium cholate or NaCl, or a combination of both sodium cholate or NaCl, is used as a growth promoter for the reaction.
Growth signatures can be indicative of embodiments implemented herein. For example, it may be possible to identify growth patterns based on seed density. Dislocation patterns formed when crystals are merged based on promotor density or patterned seed density may be detectable using SEM, AFM, and/or TEM. Chemical residues can be indicative of embodiments implemented herein. For example, promotors containing minerals can remain behind after growth, or carbon impurities incorporated into the films may be identifiable. In one embodiment, residual amounts (e.g., less than 2%) of carbon (C) and/or sodium (Na), followed by O may be detectable by TEM and/or EDX. Particulates may be detectable by TEM and/or EDX.
As a first exemplary processing scheme,
Referring to part (a) of
Referring to part (b) of
Referring to part (c) of
Referring to part (d) of
Referring to part (e) of
Referring to part (f) of
In an embodiment, a structure 120 of part (f) of
As a second exemplary processing scheme,
Referring to part (a) of
Referring to part (b) of
In an embodiment, a structure 140 of part (b) of
As a third exemplary processing scheme,
Referring to part (a) of
Referring to part (b) of
In an embodiment, a structure 160 of part (b) of
As described above, structures 120, 140 or 160 may be used to fabricate a device layer, such as a transistor layer. In one embodiment, the TMD layers are used as transistor channel layers. In an embodiment, the 2D TMD material layers each has a thickness in a range of 0.6-5 nanometers.
In an embodiment, each 2D material layer is maintained as a blanket structure. In other embodiments each 2D material layer can have a nanowire structure (e.g., about the same vertical dimension as the dimension into the page) or a nanosheet structure or nanoribbon structure (e.g., a greater dimension into than page than the vertical dimension). In an embodiment, a channel region of the 2D material layer be suspended. In another embodiment, the 2D material layer is a conformal layer over a planar dielectric layer (e.g., as is described in association with
Source or drain contacts can be fabricated for each device layer. In an embodiment, the source or drain contacts include a metal and are conductive structures (as opposed to a semiconductor structure). In other embodiments, the source or drain contacts are semiconductor structures.
A gate dielectric layer can be fabricated for each device layer. In an embodiment, the gate dielectric layer includes a dielectric material selected from the group consisting of hafnium oxide, zirconium oxide, hafnium aluminum oxide, zirconium hafnium oxide, and strontium titanium oxide.
Gate spacers can be fabricated for each device layer. In an embodiment, the gate spacers include a dielectric material selected from the group consisting of aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride. A conductive gate electrode can be fabricated on the gate dielectric layer and between the gate spacers.
It is to be appreciated that spin-on two-dimensional (2D) channel materials can be used in multiple layer structures and/or have a varied composition within an integrated circuit structure. As an exemplary structure,
Referring to
The first device 202 includes a first plurality of vertically stacked two-dimensional (2D) material layers 206, such as MoS2 layers. A first gate stack 208/210 is around the first plurality of vertically stacked 2D material layers 206. The first gate stack 208/210 has a gate electrode 208, such as a metal gate electrode, around a gate dielectric layer 210, such as a high-k gate dielectric layer. First gate spacers 212, such as boron nitride spacers or carbon-doped oxide spacers, are along sides of the first gate stack 208/210. A dielectric cap 214, such as a silicon carbide cap, is on a top one of the first plurality of vertically stacked 2D material layers 206. Source or drain contacts 216/218 are along sides of the first plurality of vertically stacked 2D material layers 206. The source or drain contact 216 can be coupled to a lower power rail 222 by a conductive via 220, such as is depicted.
The second device 204 includes a second plurality of vertically stacked two-dimensional (2D) material layers 226, such as WSe2 layers. A second gate stack 228/230 is around the second plurality of vertically stacked 2D material layers 226. The second gate stack 228/230 has a gate electrode 228, such as a metal gate electrode, around a gate dielectric layer 230, such as a high-k gate dielectric layer. Second gate spacers 232, such as boron nitride spacers or carbon-doped oxide spacers, are along sides of the second gate stack 228/230. A dielectric cap 234, such as a silicon carbide cap, is on a top one of the second plurality of vertically stacked 2D material layers 226. Source or drain contacts 236/238 are along sides of the second plurality of vertically stacked 2D material layers 226. The source or drain contact 236 can be coupled to a lower power rail 242 by a conductive via 240, such as is depicted, e.g., which may be fabricated during a backside reveal process.
The first device 202 and the second device 204 can be surrounded by a dielectric framework 224, such as a silicon nitride framework. For simplicity, a single dielectric framework 224 is depicted. However, each device 202 and 204 may have its own associated separate and distinct dielectric framework. In an embodiment, the first device 202 and the second device 204 are vertically separated by a break layer 250, such as a layer of amorphous boron nitride. In an embodiment, a conductive connection layer 252, such as a tungsten via or cobalt via, electrically couples the first device 202 and the second device 204 through the break layer 250, e.g., to provide an inverter structure. In another embodiment, the break layer 250 entirely electrically isolates the first device 202 from the second device 204.
With reference again to
In an embodiment, the first device 202 is an NMOS device, and the second device 204 is a PMOS device. In another embodiment, the first device 202 is a PMOS device, and the second device 204 is an NMOS device. In another embodiment, the first device 202 is a first PMOS device, and the second device 204 is a second PMOS device. In another embodiment, the first device 202 is a first NMOS device, and the second device 204 is a second NMOS device.
In an embodiment, the first device 202 is electrically coupled to the second device 204, as is depicted. In another embodiment, the first device 202 is electrically isolated from the second device 204.
With reference again to
In an embodiment, the NMOS device 202 is electrically coupled to the PMOS device 204. In another embodiment, the NMOS device 202 is electrically isolated from the PMOS device 204.
In an embodiment, the first plurality of vertically stacked 2D material layers 206 is a first plurality of vertically stacked nanosheets, and the second plurality of vertically stacked 2D material layers 226 is a second plurality of vertically stacked nanosheets. In another embodiment, the first plurality of vertically stacked 2D material layers 206 is a first plurality of vertically stacked nanowires, and the second plurality of vertically stacked 2D material layers 226 is a second plurality of vertically stacked nanowires.
In another aspect, thin film transistors having a relatively thick body may not exhibit good electrostatic gate control. Furthermore, a passivation layer on a bottom of a TFT may cause interactions leading to undesirable doping which may increase OFF-state leakage and degrade subthreshold swing of a TFT device. In accordance with one or more embodiments of the present disclosure, a second gate is introduced on a bottom of a channel material layer of a TFT in order to control the channel closest to the bottom interface. Such embodiments may be implemented to improve overall electrostatics and ON/OFF ratio for the TFT device.
As an exemplary structure,
Referring to
In an embodiment, the gate dielectric layers 314 and 314′ are composed of a same material. In an embodiment, gate electrodes 312 and 312′ are composed of a same material. It is to be appreciated that source or drain regions are into and out of the page of the view of
In another aspect, in accordance with one or more embodiments described herein, non-planar BEOL-compatible double gated thin film transistors (TFTs) are fabricated by effectively increasing the transistor width (and hence the drive strength and performance) for a given projected area. A double gated TFT fabricated using such an architecture may exhibit an increase in gate control, stability, and performance of thin film transistors. Applications of such systems may include, but are not limited to, back-end-of-line (BEOL) logic, memory, or analog applications. Embodiments described herein may include non-planar structures that effectively increase transistor width (relative to a planar device) by integrating the devices in unique architectures.
The planar double gated TFT 300 has an effective gate width that is the length of the planar channel material 306 between locations A and B′, as depicted in
Referring to
In an embodiment, the gate dielectric layers 364 and 364′ are composed of a same material. In an embodiment, gate electrodes 362 and 362′ are composed of a same material. It is to be appreciated that source or drain regions are into and out of the page of the view of
The non-planar double gated TFT 350 has an effective gate width that is the length of the conformal semiconducting oxide channel material layer 356 between locations A′ and B′, i.e., the full length including undulating portions over the tops and sidewalls of the dielectric fins 355, as is depicted in
To highlight other aspects of a non-planar double gated TFT topography,
Referring to
In an embodiment, a gate electrode 362′ of the first gate stack 362′/364′ is electrically coupled to a gate electrode 362 of the second gate stack 362/364, e.g., they may share a common contact or interconnect (not shown). In another embodiment, as shown, a gate electrode 362′ of the first gate stack 362′/364′ is electrically independent from a gate electrode 362 of the second gate stack 362/364.
In an embodiment, the first gate stack 362′/364′ includes a first high-k gate dielectric layer 364′ between the channel material layer 356 and a gate electrode 362′ of the first gate stack 362′/364′. The second gate stack 362/364 includes a second high-k gate dielectric layer 364 between the channel material layer 356 and a gate electrode 362 of the second gate stack 362/364. In an embodiment, gate electrodes 362 and 362′ are or include metal gate electrodes.
In an embodiment, the integrated circuit structure 370 further includes a first dielectric spacer (front or left 372) between the first conductive contact (front or left 374) and the first side of the second gate stack 362/364. The first dielectric spacer (front or left 372) is over a fourth portion of the channel material layer 356. A second dielectric spacer (back or right 372) is between the second conductive contact (back or right 374) and the second side of the second gate stack 362/364. The second dielectric spacer (back or right 372) is over a fifth portion of the channel material layer 356.
In an embodiment, fin 335 induces a strain on channel material layer 356. In an embodiment, spacers 372 induce a strain on channel material layer 356. In an embodiment, both fin 335 and spacers 372 induce a strain on channel material layer 356.
In an embodiment, dielectric fins described herein may be fabricated as a grating structure, where the term “grating” is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have dielectric fins spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach. In an embodiment, the dielectric fin or fins each have squared-off (as shown) or rounded corners.
In accordance with an embodiment of the present disclosure, the above TFT double gate non-planar architectures 350 and 370 provide for higher effective widths for a transistor for a scaled projected area. In an embodiment, the drive strength and performance of such transistors are improved over state-of-the-art planar BEOL transistors.
Thus, in accordance with one or more embodiment of the present disclosure, three dimensional (3D) double gated field effect transistors (TFETs) having increased gate width are described. In an embodiment, such double gated FETs are based on a channel material including a 2D material (e.g., MoS2, WS2, MoSe2, WSe2, MoTe2, or InSe). The 2D material can be a spin-on 2D material, such as described above.
It is to be appreciated that in some embodiments the layers and materials described in association with embodiments herein are typically formed on or above an underlying semiconductor substrate, e.g., as FEOL layer(s). In other embodiments, the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s) above an underlying semiconductor substrate. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated on underlying lower level back-end-of-line (BEOL) interconnect layers.
In the case that an insulator layer is optionally used, the insulator layer may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a gate structure from an underlying bulk substrate or interconnect layer. For example, in one embodiment, the insulator layer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, carbon-doped silicon nitride, aluminum oxide, or aluminum nitride. In a particular embodiment, the insulator layer is a low-k dielectric layer of an underlying BEOL layer.
In an embodiment, a channel material layer of a TFT is or includes a 2D material (e.g., MoS2, WS2, MoSe2, WSe2, MoTe2, or InSe). The 2D material of layer can be formed together with a lower hexagonal boron nitride (hBN) layer, an upper hBN layer, or both a lower hBN layer and an upper hBN layer. In an embodiment, the channel material layer has a thickness between 0.5 nanometers and 10 nanometers.
In an embodiment, gate electrodes described herein include at least one P-type work function metal or N-type work function metal, depending on whether the integrated circuit device is to be included in a P-type transistor or an N-type transistor. For a P-type transistors, metals that may be used for the gate electrode may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an N-type transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode includes a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a barrier layer. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In an embodiment, gate dielectric layers described herein are composed of a high-k material. For example, in one embodiment, a gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, hafnium zirconium oxide, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In some implementations, the gate dielectric may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
In an embodiment, dielectric spacers are formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, silicon oxynitride, aluminum oxide, or aluminum nitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate electrode.
In an embodiment, conductive contacts act as contacts to source or drain regions of a TFT, or act directly as source or drain regions of the TFT. The conductive contacts may be spaced apart by a distance that is the gate length of the transistor. In some embodiments, the gate length is between 2 and 30 nanometers. In an embodiment, the conductive contacts include one or more layers of metal and/or metal alloys.
In an embodiment, interconnect lines (and, possibly, underlying via structures), such as interconnect lines, described herein are composed of one or more metal or metal-containing conductive structures. The conductive interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the interconnect lines includes a barrier layer and a conductive fill material. In an embodiment, the barrier layer is composed of a metal nitride material, such as tantalum nitride or titanium nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.
In an embodiment, ILD materials described herein are composed of or include a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, aluminum oxide, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.
In one aspect, a gate electrode and gate dielectric layer, particularly upper gate stacks, may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.
In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structures described herein. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed. The anneal is performed prior to formation of the permanent contacts.
It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.
In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.
In another aspect, the integrated circuit structures described herein may be included in an electronic device. As a first example of an apparatus that may include one or more of the TFTs disclosed herein,
Referring to
Referring to
The IC device 600 may include one or more device layers, such as device layer 604, disposed on the substrate 602. The device layer 604 may include features of one or more transistors 640 (e.g., TFTs described above) formed on the substrate 602. The device layer 604 may include, for example, one or more source and/or drain (S/D) regions 620, a gate 622 to control current flow in the transistors 640 between the S/D regions 620, and one or more S/D contacts 624 to route electrical signals to/from the S/D regions 620. The transistors 640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 640 are not limited to the type and configuration depicted in
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 640 of the device layer 604 through one or more interconnect layers disposed on the device layer 604 (illustrated in
The interconnect structures 628 may be arranged within the interconnect layers 606-610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 628 depicted in
In some embodiments, the interconnect structures 628 may include trench structures 628a (sometimes referred to as “lines”) and/or via structures 628b filled with an electrically conductive material such as a metal. The trench structures 628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 602 upon which the device layer 604 is formed. For example, the trench structures 628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 606-610 may include a dielectric material 626 disposed between the interconnect structures 628, as shown in
A first interconnect layer 606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 604. In some embodiments, the first interconnect layer 606 may include trench structures 628a and/or via structures 628b, as shown. The trench structures 628a of the first interconnect layer 606 may be coupled with contacts (e.g., the S/D contacts 624) of the device layer 604.
A second interconnect layer 608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 606. In some embodiments, the second interconnect layer 608 may include via structures 628b to couple the trench structures 628a of the second interconnect layer 608 with the trench structures 628a of the first interconnect layer 606. Although the trench structures 628a and the via structures 628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 608) for the sake of clarity, the trench structures 628a and the via structures 628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 608 according to similar techniques and configurations described in connection with the second interconnect layer 608 or the first interconnect layer 606.
The IC device 600 may include a solder resist material 634 (e.g., polyimide or similar material) and one or more bond pads 636 formed on the interconnect layers 606-610. The bond pads 636 may be electrically coupled with the interconnect structures 628 and configured to route the electrical signals of the transistor(s) 640 to other external devices. For example, solder bonds may be formed on the one or more bond pads 636 to mechanically and/or electrically couple a chip including the IC device 600 with another component (e.g., a circuit board). The IC device 600 may have other alternative configurations to route the electrical signals from the interconnect layers 606-610 than depicted in other embodiments. For example, the bond pads 636 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.
Referring to
In some embodiments, the circuit board 702 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 702. In other embodiments, the circuit board 702 may be a non-PCB substrate.
The IC device assembly 700 illustrated in
The package-on-interposer structure 736 may include an IC package 720 coupled to an interposer 704 by coupling components 718. The coupling components 718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 716. Although a single IC package 720 is shown in
The interposer 704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 704 may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 706. The interposer 704 may further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 704. The package-on-interposer structure 736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 700 may include an IC package 724 coupled to the first face 740 of the circuit board 702 by coupling components 722. The coupling components 722 may take the form of any of the embodiments discussed above with reference to the coupling components 716, and the IC package 724 may take the form of any of the embodiments discussed above with reference to the IC package 720.
The IC device assembly 700 illustrated in
Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.
Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 806 enables wireless communications for the transfer of data to and from the computing device 800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more thin film transistors having a spin-on two-dimensional (2D) channel material, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more thin film transistors having a spin-on two-dimensional (2D) channel material, in accordance with implementations of embodiments of the disclosure.
In further implementations, another component housed within the computing device 800 may contain an integrated circuit die that includes one or more thin film transistors having a spin-on two-dimensional (2D) channel material, in accordance with implementations of embodiments of the disclosure.
In various implementations, the computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.
Thus, embodiments described herein include thin film transistors having a spin-on two-dimensional (2D) channel material.
The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.
These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example embodiment 1: An integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.
Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein the first device layer is an NMOS device layer, and the second device layer is a PMOS device layer.
Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein the first 2D material layer is above the second 2D material layer.
Example embodiment 4: The integrated circuit structure of example embodiment 1 or 2, wherein the second 2D material layer is above the first 2D material layer.
Example embodiment 5: The integrated circuit structure of example embodiment 1 or 2, wherein the first 2D material layer is laterally adjacent to the second 2D material layer.
Example embodiment 6: A method of fabricating an integrated circuit structure, the method including forming a first device layer including a first spin-on two-dimensional (2D) material layer above a substrate. The method also includes forming a second device layer including a second spin-on 2D material layer above the substrate, the second spin-on 2D material layer having a different composition than the first spin-on 2D material layer.
Example embodiment 7: The method of example embodiment 6, wherein the first spin-on 2D material layer includes molybdenum and sulfur.
Example embodiment 8: The method of example embodiment 7, wherein the first spin-on 2D material layer further includes sodium and carbon.
Example embodiment 9: The method of example embodiment 6, 7 or 8, wherein the second spin-on 2D material layer includes tungsten and selenium.
Example embodiment 10: The method of example embodiment 9, wherein the second spin-on 2D material layer further includes sodium and carbon.
Example embodiment 11: The method of example embodiment 6, 7, 8, 9 or 10, wherein the first device layer is an NMOS device layer, and the second device layer is a PMOS device layer.
Example embodiment 12: The method of example embodiment 6, 7, 8, 9, 10 or 11, wherein the first spin-on 2D material layer is formed above the second spin-on 2D material layer.
Example embodiment 13: The method of example embodiment 6, 7, 8, 9, 10 or 11, wherein the first spin-on 2D material layer is formed laterally adjacent to the second spin-on 2D material layer.
Example embodiment 14: A computing device includes a board, and a component coupled to the board. The component includes an integrated circuit structure including a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.
Example embodiment 15: The computing device of example embodiment 14, further including a memory coupled to the board.
Example embodiment 16: The computing device of example embodiment 14 or 15, further including a communication chip coupled to the board.
Example embodiment 17: The computing device of example embodiment 14, 15 or 16, further including a camera coupled to the board.
Example embodiment 18: The computing device of example embodiment 14, 15, 16 or 17, further including a battery coupled to the board.
Example embodiment 19: The computing device of example embodiment 14, 15, 16, 17 or 18, further including a GPS coupled to the board.
Example embodiment 20: The computing device of example embodiment 14, 15 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.
