Patent Application
20120208347
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application Nos. 10-2011-0012553 and 10-2011-0043618, filed on Feb. 11, 2011 and May 9, 2011, respectively, the disclosures of which are hereby incorporated by reference in their entireties.
1. Technical Field
The present disclosure relates to semiconductor devices and methods of fabricating the same and, more particularly, to three-dimensional semiconductor devices and methods of fabricating the same.
2. Description of Related Art
Semiconductor devices are becoming more highly integrated to meet the requirements of customers, e.g., in order to provide high performance and low cost. The integration density of the semiconductor devices is a factor that may directly influence the cost of the semiconductor devices. Thus, semiconductor devices have been continuously scaled down. In two-dimensional semiconductor memory devices, i.e., planar semiconductor memory devices, the integration density may be mainly determined by a planar area that a unit memory cell occupies. Accordingly, the integration density of two-dimensional semiconductor memory devices may be significantly limited by the level of technology for forming fine and small patterns. In addition, implementing fine patterns in two-dimensional semiconductor memory devices may result in increasing manufacturing costs and/or high priced apparatuses. Therefore, there may be some limitations in increasing the integration density of two-dimensional semiconductor devices.
Recently, three-dimensional semiconductor devices including memory cells arranged in a three-dimensional array have been proposed to overcome the above limitations. Nevertheless, new processes which are capable of reducing bit cost and realizing reliable products are still required for successful mass production of three-dimensional semiconductor devices, such as three-dimensional memory devices.
Exemplary embodiments in accordance with principles of inventive concepts may provide methods of fabricating three-dimensional semiconductor devices, such as three-dimensional semiconductor memory devices, and three-dimensional semiconductor devices, such as semiconductor memory devices, fabricated thereby.
In an exemplary embodiment in accordance with principles of inventive concepts, a method comprises forming a stack structure including first and second layers alternately stacked on a substrate, patterning the stack structure to form at least one isolation trench, forming channel structures penetrating the stack structure and being spaced apart from the isolation trench, and forming upper interconnection lines on the stack structure to connect the channel structures to each other. In an exemplary embodiment in accordance with inventive concepts, an isolation trench may be formed prior to formation of channel structures.
In an exemplary embodiment in accordance with principles of inventive concepts, each of the channel structures may include a semiconductor layer, and an isolation trench may be formed prior to formation of the semiconductor layer.
In an exemplary embodiment in accordance with principles of inventive concepts, the isolation trench may be formed to penetrate the stack structure and to expose a substrate.
In an exemplary embodiment in accordance with principles of inventive concepts, the isolation trench may be formed to split the stack structure into a plurality of sub-stack structures that are spaced apart from each other in a horizontal direction parallel with a top surface of the substrate.
In an exemplary embodiment in accordance with principles of inventive concepts, the isolation trench may be formed to expose a substrate, and a first impurity region may be formed in the substrate under the isolation trench.
In an exemplary embodiment in accordance with principles of inventive concepts, a method may comprise forming a first structure in an isolation trench. First structure may extend along the isolation trench.
In an exemplary embodiment in accordance with principles of inventive concepts, forming a first structure may include forming a first insulation pattern in the isolation trench, and the first isolation pattern may be formed of a material having an etch selectivity with respect to the second layers.
In an exemplary embodiment in accordance with principles of inventive concepts, forming a first structure may include forming a first conductive pattern in the isolation trench.
In an exemplary embodiment in accordance with principles of inventive concepts, forming channel structures may include forming channel holes penetrating the stack structure, and forming a semiconductor layer in the channel holes. The isolation trench and the channel holes may be simultaneously formed using the same etching process.
In another exemplary embodiment in accordance with principles of inventive concepts, the three-dimensional semiconductor device may comprise a stack structure including a plurality of electrodes sequentially stacked on a substrate, upper interconnection lines disposed on the stack structure, channel structures penetrating the stack structure to electrically connect the upper interconnection lines to the substrate, and at least one first structure penetrating at least one of the electrodes and crossing the upper interconnection lines. A portion of the substrate under first structure may have the same conductivity type as portions of the substrate under the channel structures.
In an exemplary embodiment in accordance with principles of inventive concepts, a three-dimensional semiconductor device may further comprise a data storage layer between a stack structure and channel structures. The data storage layer may extend to intervene between first structure and the stack structure.
In an exemplary embodiment in accordance with principles of inventive concepts, a three-dimensional semiconductor device may further comprise a buried insulation layer between channel structures, and a second impurity region in the substrate under the buried insulation layer. The second impurity region may have a different conductivity type from the substrate.
In an exemplary embodiment in accordance with principles of inventive concepts, a three-dimensional semiconductor device may further comprise a first impurity region in the substrate under first structure. First structure may be provided in an isolation trench penetrating at least one of the electrodes, and first structure may include a first insulation pattern in the isolation trench and a conductive pattern penetrating the first insulation pattern to be electrically connected to the first impurity region.
In an exemplary embodiment in accordance with principles of inventive concepts, the channel structures may be arrayed in a plurality of rows parallel with first structure. The stack structure may include step-shaped pads formed at an edge thereof, and the at least one first structure may be disposed between a row of the channel structure closest to the step-shaped pads and the step-shaped pads.
In an exemplary embodiment in accordance with principles of inventive concepts, a three-dimensional semiconductor device may further comprise a peripheral circuit region disposed at one side of the stack structure. The channel structures may be arrayed in a plurality of rows parallel with first structure, and first structure may be disposed between a row of the channel structure closest to the peripheral circuit region and the peripheral circuit region.
In an exemplary embodiment in accordance with principles of inventive concepts, an electronic device includes a plurality of sub-stack structures formed within a cell array region, each including electronic circuitry, formed on a substrate and an electrical interconnection between circuitry in one sub-stack and circuitry in another sub-stack.
In an exemplary embodiment in accordance with principles of inventive concepts, sub-stacks of an electronic device include electrodes sequentially stacked on a substrate each sub-stack is separated from other sub-stacks by an isolation trench that extends at least half a distance from the top of the sub-stack to the substrate upon which the sub-stacks are formed.
In an exemplary embodiment in accordance with principles of inventive concepts, sub-stacks of an electronic device include memory circuitry.
In an exemplary embodiment in accordance with principles of inventive concepts, sub-stacks of an electronic device include memory circuitry.
In an exemplary embodiment in accordance with principles of inventive concepts, sub-stacks of an electronic device include flash memory circuitry.
In an exemplary embodiment in accordance with principles of inventive concepts, sub-stacks of an electronic device include flash memory circuitry and electrical interconnections between sub-stacks include bit lines.
In an exemplary embodiment in accordance with principles of inventive concepts, the electronic device further comprises: upper interconnection lines on the sub-stack structures; channel structures penetrating the sub-stack structures, the channel structures electrically connecting upper interconnection lines to the substrate; and at least one first structure penetrating at least one of the electrodes and crossing the upper interconnection lines; wherein a portion of the substrate under the at least one first structure has a same conductivity type as portions of the substrate under the channel structures.
The above and other features and advantages of the disclosure will become more apparent in view of the attached drawings and accompanying detailed description.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various limitations, elements, components, regions, layers and/or sections, these limitations, elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one limitation, element, component, region, layer or section from another limitation, element, component, region, layer or section. Thus, a first limitation, element, component, region, layer or section discussed below could be termed a second limitation, element, component, region, layer or section without departing from the teachings of the present application.
It will be further understood that when an element is referred to as being “on” or “connected” or “coupled” to another element, it can be directly on or above, or connected or coupled to, the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly on” or “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). When an element is referred to herein as being “over” another element, it can be over or under the other element, and either directly coupled to the other element, or intervening elements may be present, or the elements may be spaced apart by a void or gap. Descriptions may make relate directions or orientations to coordinate systems (e.g., in the y-axis direction). Those references are made for the ease of illustration only and are not meant to restrict the scope of inventive subject matter in any way.
Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this invention. Various structural, logical, and process step changes may be made without departing from the spirit or scope of the invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which these embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
The bit lines BL0 to BL3 are two-dimensionally arrayed, and some of the plurality of cell strings CSTR may be electrically connected in parallel to each of the bit lines BL0 to BL3. Each of the cell strings CSTR may be electrically connected to any one of the common source lines CSL. In an exemplary embodiment in accordance with principles of inventive concepts, the common source lines CSL may be two-dimensionally arrayed. The common source lines CSL may be electrically connected to each other and may be simultaneously controlled to have the same electrical bias, for example, the same voltage. Alternatively, the common source lines CSL may be isolated from each other and may be independently controlled.
Each of the cell strings CSTR may be configured to include a ground selection transistor GST connected to one of the common source lines CSL, a string selection transistor SST connected to one of the bit lines BL0 to BL3, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. The ground selection transistor GST, the plurality of memory cell transistors MCT and the string selection transistor SST constituting each of the cell strings CSTR may be serially connected to each other.
In an exemplary embodiment in accordance with principles of inventive concepts, each of the common source lines CSL may be electrically connected to some of sources of the ground selection transistors GST. In addition, gate electrodes of the ground selection transistors GST may extend to form ground selection lines GSL, and gate electrodes of the string selection transistors SST may extend to form string selection lines SSL. Further, gate electrodes of the memory cell transistors MCT may extend to form word lines WL to WL3. The ground selection lines GSL, the string selection lines SSL and the word lines WL0 to WL3 may be disposed between the common source lines CSL and the bit lines BL0 to BL3. Each of the memory cell transistors MCT may act as a data storage element.
The memory cell transistors MCT constituting any one of the cell strings CSTR may be located at different levels from each other. Thus, the word lines WL0 to WL3 connected to the memory cell transistors MCT of each cell string CSTR may also be located at different levels from each other. Further, the plurality of word lines WL0 connected to the plurality of cell strings CSTR may be located at the same level, and the plurality of word lines WL1 connected to the plurality of cell strings CSTR may be located at the same level. Similarly, the plurality of word lines WL2 connected to the plurality of cell strings CSTR may be located at the same level, and the plurality of word lines WL3 connected to the plurality of cell strings CSTR may be located at the same level.
The plurality of word lines WL0, WL1, WL2 or WL3, which are located at substantially the same level from the common source lines CSL, may be electrically connected to each other to have the same electrical potential. Alternately, even though the word lines WL0, WL1, WL2 or WL3 are located at the same level, the word lines WL0, WL1, WL2 or WL3 may be electrically isolated from each other and may be independently controlled to have different biases.
Referring to
Forming stack structure 100 may include alternately stacking first layer and second layers on substrate 10. The first layers may correspond to sacrificial layers 130 (131, 132, 133, 134, 135 and 136), and the second layers may correspond to insulation layers 120 (121, 122, 123, 124, 125, 126 and 127). The insulation layers 120 and sacrificial layers 130 may be alternately and repeatedly stacked, as illustrated in
Sacrificial layers 130 may be formed of a material having an etch selectivity with respect to the insulation layers 120 and vice versa. That is, when sacrificial layers 130 are etched using a predetermined etch recipe, an etch rate of the insulation layers 120 may be relatively lower than that of sacrificial layers 130. The etch selectivity may be expressed as a ratio of etch rates of two different materials exposed to a specific etch recipe. In an exemplary embodiment in accordance with principles of inventive concepts, the insulation layers 120 may be formed of a material having an etch selectivity within the range of from about 1:10 to about 1:200 (more definitely, from about 1:30 to about 1:100) with respect to sacrificial layers 130. For example, the insulation layers 120 may be formed of at least one of a silicon oxide layer and a silicon nitride layer, and sacrificial layers 130 may be formed of a material selected from the group consisting of a silicon layer, a silicon oxide layer, a silicon carbide layer and a silicon nitride layer, but different from the insulation layers 120. For the purpose of ease and convenience in explanation, exemplary embodiment in accordance with principles of inventive concepts will be described hereinafter under the assumption that the insulation layers 120 include a silicon oxide layer and sacrificial layers 130 include a silicon nitride layer.
At least one of the insulation layers 120 may have a different thickness from the others. In an exemplary embodiment in accordance with principles of inventive concepts, the lowermost insulation layer 121 may be formed to be thinner than the other insulation layers 122, 123, 124, 124, 125, 126 and 127, and the uppermost insulation layer 127 may be formed to be thicker than the other insulation layers 121, 122, 123, 124, 124, 125 and 126. However, the thickness of each of the insulation layers 120 is not limited to the above descriptions. That is, the insulation layers 120 and sacrificial layers 130 may be modified to have various thicknesses. Further, the number of the layers 120 and 130 constituting stack structure 100 may also be changed according to a design purpose.
Referring to
The process of forming isolation trench 107 may include forming a mask pattern having an opening on stack structure 100, anisotropically etching stack structure 100 using the mask pattern as an etch mask, and removing the mask pattern. In an exemplary embodiment in accordance with principles of inventive concepts, the isolation trench 107 may be relatively deep, compared with a width thereof Isolation trench 107 may be formed so that a sidewall of isolation trench 107 may have a sloped profile. For example, the width of isolation trench 107 may be gradually reduced toward substrate 10. In an exemplary embodiment in accordance with principles of inventive concepts, the width of isolation trench 107 (e.g., a distance along an x-axis direction) may denote a bottom width w1 of isolation trench 107, which corresponds to a minimum width thereof.
Isolation trench 107 may be formed to expose substrate 10 and substrate 10 may be recessed during formation of isolation trench 107. Formation of a recess in substrate 10 may be due, for example, to an over-etch step of the anisotropic etching process of forming isolation trench 107. The array and/or disposition of isolation trench 107 will be described in detail hereinafter with reference to
If stack structure 100 may be formed to include heterogeneous layers vertically stacked, internal physical stress may be generated in stack structure 100. The internal physical stress may be due to a difference between thermal expansion (or contraction) coefficients of the heterogeneous layers. The internal physical stress may result in deformation of stack structure 100 in a subsequent thermal process, e.g., formation of a semiconductor layer in a channel hole performed at a relatively high temperature. For example, a silicon nitride layer may have a thermal contraction coefficient which is greater than that of a silicon oxide layer. Thus, a physical stress may be generated between the insulation layers 120 and sacrificial layers 130 constituting stack structure 100 at a high temperature. As the height of stack structure 100 increases, the physical stress generated in stack structure 100 due to differences in coefficients of expansion and/or contraction may also increase.
According to an exemplary embodiment, the anisotropical etching process of forming isolation trench 107 may split stack structure 100 into a plurality of sub-stack structures before thermal processes are performed. The sub-stack structures may have a relatively small size as compared with the initial stack structure 100. Thus, even though the subsequent thermal processes are applied to the substrate including the sub-stack structures, the physical stresses generated in the sub-stack structures may be substantially reduced, thereby preventing deformation of the sub-stack structures during high-temperature processing.
In an exemplary embodiment, a first impurity region 245 may be formed in substrate 10 under isolation trench 107. First impurity region 245 may extend in the y-axis direction, the same direction as isolation trench 107. First impurity region 245 may be formed prior to formation of stack structure 100, or after formation of isolation trench 107, for example. First impurity region 245 may correspond to a region for applying a voltage to substrate 10 and, therefore, may be formed to have the same conductivity type as substrate 10. If a P-type well may be formed in substrate 10 adjacent to stack structure 100, first impurity region 245 may be formed in the P-type well and may be formed to have the P-type. An impurity concentration of first impurity region 245 may be higher than that of substrate 10 or the P-type well, for example. First impurity region 245 may be formed using an ion implantation process that employs the sub-stack structures as ion implantation masks, for example.
Referring to
A plurality of channel holes 105 may be formed to penetrate sub-stack structures. In an exemplary embodiment in accordance with principles of inventive concepts, channel holes 105 may be formed to have a cylindrical shape and to, therefore, have a circular shape when viewed from a plan view. The depth of a channel hole 105 may be at least five times greater than a width thereof. Channel holes 105 may be two-dimensionally arrayed in a plan view parallel with an x-y plane. That is, channel holes 105 may be arrayed along the x-axis direction and along the y-axis direction crossing the x-axis direction. Channel holes 105 may be formed to be spaced apart from each other.
Channel holes 105 may be fondled to a depth that is sufficient to expose substrate 10. In an exemplary embodiment in accordance with principles of inventive concepts, channel holes 105 may be formed after forming first insulation pattern 270. A diameter w2 of channel holes 105 in the x-axis direction may be less than the width w1 of isolation trench 107. The width w1 of isolation trench 107 may be formed to be relatively great in order to accommodate the formation of contact plugs therein in a subsequent process.
Referring to
As described above, semiconductor layer 170 may be formed in relatively higher temperature than other processes. The high temperature process may tend to deform a stack structure 100. However, according to the present embodiment, isolation trench 107 may split stack structure 100 into a plurality of sub-stack structures prior to the high temperature process of forming semiconductor layer 170. Because isolation trench 107 reduces the size of the areas over which differences in coefficients of expansion or contraction generate shearing and or other potentially damaging forces isolation trench 107 may relieve the stress generated in the sub-stack structures and may prevent temperature-induced deformation sub-stack structures.
A filling layer 180 may be formed on semiconductor layer 170. Filling layer 180 may be formed to fill channel holes 105. Filling layer 180 may be formed of an insulation material, for example, silicon oxide. Filling layer 180 may be formed using a spin on glass (SOG) technique, for example. In an exemplary embodiment in accordance with principles of inventive concepts, prior to formation of semiconductor layer 170, an annealing process may be applied to the substrate including semiconductor layer 170. The annealing process may employ a hydrogen containing gas or a deuterium containing gas as an ambient gas. A plurality of crystalline defects in semiconductor layer 170 may be cured by hydrogen atoms produced during an annealing process.
In other exemplary embodiments in accordance with principles of inventive concepts, semiconductor layer 170 may be formed to fill channel holes 105. In such embodiments, the process of forming filling layer 180 may be omitted.
Referring to
Upper portions of the filling layers 180 in channel holes 105 may be removed to form recessed regions. Semiconductor patterns may be formed in respective ones of the recessed regions. Hereinafter, it will be understood that semiconductor layer 170 includes a semiconductor pattern.
Referring to
Substrate 10 under first trenches 200 may be recessed during the process of forming first trenches by over-etching first trenches 200, for example. In an exemplary embodiment in accordance with principles of inventive concepts, a width w3 of first trenches 200 in the x-axis direction may be less than the width w1 of isolation trench 107.
Referring to
Recessed regions 210 may be formed by laterally etching sacrificial layers 130 using an etch recipe having an etch selectivity with respect to the insulation layers 120 and the semiconductor layers 170. For example, when sacrificial layers 130 are formed of a silicon nitride layer and the insulation layers 120 are formed of a silicon oxide layer, sacrificial layers 130 may be selectively removed using an etchant containing a phosphoric acid solution.
Portions of sacrificial layers 130 between the channel structures VS and first insulation pattern 270 may be etched by the etchant that passes through recessed regions 210 between the channel structures VS arrayed and separated in the y-axis direction. That is, while sacrificial layers 130 may be selectively removed, the etchant supplied into first trenches 200 may pass through the regions between the channel structures VS arrayed in the y-axis direction and may reach the sidewalls of first insulation pattern 270. Thus, sacrificial layers 130 between the channel structures VS and first insulation pattern 270 may also be completely removed. As described above, sacrificial layers 130 may be formed of a material having an etch selectivity with respect to first insulation pattern 270. Accordingly, first insulation pattern 270 may still remains even though sacrificial layers 130 are removed to form recessed regions 210.
Referring to
The process of forming electrode patterns HS may include sequentially forming a data storage layer and a conductive layer on the substrate including recessed regions 210, and removing the conductive layer in first trenches 200 to leave portions of the conductive layer in respective ones of recessed regions 210. The data storage layers 220 and electrode patterns 230 may also fill recessed regions 210 between first insulation pattern 270 and channel structures VS through the spaces between the channel structures VS arrayed in the y-axis direction. The configurations of data storage layers 220 will be described hereinafter with reference to
The conductive layer may be formed to fill recessed regions 210 surrounded by the data storage layer. First trenches 200 may be completely or partially filled with the conductive layer. The conductive layer may be formed to include at least one of a doped silicon layer, a metal layer, a metal nitride layer or a metal silicide layer. For example, the conductive layer may include a tantalum nitride layer or a tungsten layer. In an exemplary embodiment in accordance with principles of inventive concepts, conductive layer may be conformally formed along inner surfaces of first trenches 200. In this case, the electrode patterns HS may be formed by isotropically etching the conductive layer in first trenches 200. Alternatively, the conductive layer may be formed to completely fill first trenches 200. In this case, the electrode patterns HS may be formed by anisotropically etching the conductive layer in first trenches 200.
According to an embodiment for fabricating a flash memory device, after forming the electrode patterns HS, second impurity regions 240 may be formed in substrate 10. The second impurity regions 240 may be formed in substrate 10 under first trenches 200 using an ion implantation process, for example. The second impurity regions 240 may be formed to have a different conductivity type from that of substrate 10.
In an exemplary embodiment in accordance with principles of inventive concepts, second impurity regions 240 may be electrically connected to each other, thereby having the same electrical potential. In other exemplary embodiments, the second impurity regions 240 may be electrically isolated from each other and have different electrical potentials. In other exemplary embodiments, second impurity regions 240 may include a plurality of source groups, and each of the source groups may include some of the second impurity regions 240. In this case, the plurality of source groups may be electrically isolated from each other and have different electrical potentials.
Third impurity regions 261 may be formed in respective ones of upper portions of the channel structures VS. The third impurity regions 261 may be formed to have a different conductivity type from substrate 10. In an exemplary embodiment in accordance with principles of inventive concepts, the second and third impurity regions 240 and 261 may be simultaneously formed using the same process.
Referring to
Data storage layer 220 may be formed prior to formation of buried insulation layers 250. Thus, data storage layer 220 may not extend between electrode patterns 230 and buried insulation layers 250. That is, each of buried insulation layers 250 may be in direct contact with the electrode patterns 230 adjacent thereto. Because data storage layer 220 may be formed after formation of first insulation pattern 270, data storage layer 220 may be formed to intervene between the electrode patterns 230 and first insulation pattern 270.
Contact plugs 271 may be formed in first insulation pattern 270. Contact plugs 271 may penetrate first insulation pattern 270 and may be electrically connected to first impurity region 245. Contact plugs 271 may be formed of a metal layer such as a titanium layer or a tungsten layer, for example. Forming contact plugs 271 may include etching first insulation pattern 270 to form contact holes exposing first impurity region 245, forming a metal layer filling the contact holes, and planarizing the metal layer to expose first insulation pattern 270. Contact plugs 271 may have ohmic contact with substrate 10 through first impurity region 245. The configuration of contact plugs 271 is not limited to the shape illustrated in
Referring to
A three-dimensional semiconductor device according to an exemplary embodiment in accordance with principles of inventive concepts will be described in more detail with reference again to
First structure SC may electrically connect first impurity region 245 to second upper interconnection 273. If a predetermined voltage is applied to second upper interconnection 273, the predetermined voltage may be applied to substrate 10 through contact plugs 271 and first impurity region 245.
A portion of substrate 10 directly under first structure SC may have the same conductivity type as portions of substrate 10 directly under the channel structures VS. For example, first impurity region 245 disposed under first structure SC may be heavily doped with P-type impurities, and substrate 10 under the channel structures VS may be lightly doped with the P-type impurities.
Portions of substrate 10 directly under buried insulation layers 250 may have a different conductivity type from substrate 10 directly under the channel structures VS. For example, the second impurity regions 240 disposed under buried insulation layers 250 may be heavily doped with N-type impurities, and substrate 10 under the channel structures VS may be lightly doped with the P-type impurities.
In exemplary embodiments in accordance with principles of inventive concepts, each of the data storage layers 220 may extend to intervene between electrode pattern 230 and first structure SC. In the same embodiments, each of the data storage layers 220 may not extend to intervene between the electrode pattern 230 and first structure SC, for example.
Referring to
Referring to
Referring to
Referring to
Sacrificial layers 130 between first structure SC and string isolation layers 195 as well as between first structure SC and the channel structures VS may remain even after the electrode structures HS are formed. That is, while sacrificial layers 130 are removed to from recessed regions 210 (see
Referring to
Referring to
In an exemplary embodiment in accordance with principles of inventive concepts, first pattern 278 may be formed of an insulation layer, and second patterns 279 may also be formed of an insulation layer. In the event that the first and second patterns 278 and 279 are formed of insulation layers, first pattern 278 may be formed of a material having a lower contraction coefficient or a higher expansion coefficient than second patterns 279 when heated. That is, first pattern 278 may be less contracted or greater expanded than second patterns 279 in a subsequent thermal process for forming a semiconductor layer. In an exemplary embodiment in accordance with principles of inventive concepts, first pattern 278 may include at least one of a medium temperature oxide (MTO) layer formed using a chemical vapor deposition (CVD) process, an oxide layer formed using an atomic layer deposition (ALD) process and a high density plasma (HDP) oxide layer. Second patterns 279 may be formed of a different material layer from first pattern 278. Second patterns 279 may be formed of a material which is relatively contracted at a high temperature. For example, second patterns 279 may be formed of at least one of an undoped silicate glass (USG) layer, a tetra-ethyl-ortho-silicate (TEOS) layer, a boro-silicate-glass (BSG) layer and a boro-phospho-silicate-glass (BPSG) layer.
First pattern 278 may have a lower deposition rate than second patterns 279. First pattern 278 may be less contracted or rather more expanded than second patterns 279 at a high temperature. Thus, a tensile stress applied to stack structure 100 may be compensated in a subsequent thermal process. Further, first pattern 278 may be formed to have a relatively denser structure than second patterns 279. Thus, first pattern 278 may suppress a dishing phenomenon which can be generated in a subsequent planarization process.
In other embodiment, first pattern 278 and second patterns 279 may be formed of the same material. That is, first pattern 278 and second patterns 279 may be formed using a single deposition process.
Referring to
Contact plugs 271 may be formed to penetrate respective ones of second trench regions ST2. Contact plugs 271 and first pattern 278 may constitute a first structure SC. Each of contact plugs 271 may be formed to include at least one of a metal layer, a conductive metal nitride layer and a semiconductor layer. Forming contact plugs 271 may include etching at least portions of respective ones of second patterns 279 illustrated in
In still another exemplary embodiment, first pattern 278 and/or second patterns 279 may be formed of a semiconductor material or a conductive material. For example, first pattern 278 and/or second patterns 279 may be formed of a undoped polysilicon layer or a P-type polysilicon layer. In the event that first pattern 278 and/or second patterns 279 may be formed of a conductive layer, the process of forming contact plugs 271 may be omitted.
Referring to
Referring to
According to the present embodiment, the internal stress in stack structure 100 may be alleviated prior to a high temperature process, for example, a process of forming semiconductor layers 170 constituting the channel structures VS. Thus, deformation of stack structure 100 may be prevented.
Referring to
First structure SC may include a conductive pattern. The conductive pattern may be formed of at least of a metal material and a semiconductor material. In an exemplary embodiment in accordance with principles of inventive concepts, isolation trench 107 may be completely filled with the conductive pattern. In this case, the conductive pattern may be formed to directly contact sidewalls of sacrificial layers 130 and the insulation layers 120 exposed by isolation trench 107. When a three-dimensional semiconductor device according to the present embodiment operates, a certain voltage may be applied to substrate 10 through first structure SC including the conductive pattern.
Channel holes 105 may be formed to penetrate stack structure 100 after formation of first structure SC. A depth D2 by which first structure SC extends into substrate 10 may be greater than a depth D1 by which channel holes 105 extend into substrate 10. That is, isolation trench 107 may be formed to be deeper than channel holes 105. If isolation trench 107 is deeper than channel holes 105, first structure SC in isolation trench 107 may more stably support first structure SC while sacrificial layers 130 are removed. Thus, subsequent processes may be stably performed.
Referring to
Various embodiments relating to first data storage layer 150 will be described in detail with reference to
Referring to
Referring to
Referring to
Second impurity regions 240 may be formed in substrate 10 under buried insulation layers 250 that penetrate stack structure 100 and extend in the y-axis direction, and third impurity regions 261 may be formed in upper portions of the channel structures VS. In an exemplary embodiment in accordance with principles of inventive concepts, the second and third impurity regions 240 and 261 may be heavily doped with N-type impurities.
Referring to
Referring to
A first insulation pattern 270 may be formed in isolation trench 107, and a first conductive pattern 286 may be formed to penetrate first insulation pattern 270 and to contact substrate 10, for example. Forming first insulation pattern 270 and the first conductive pattern 286 may include conformally forming an insulation layer in isolation trench 107, anisotropically etching the insulation layer to expose substrate 10 (e.g., first impurity region 245) under isolation trench 107, and filling isolation trench 107 with a conductive material. First insulation pattern 270 may be formed of a material having an etch selectivity with respect to sacrificial layers 130. In an exemplary embodiment in accordance with principles of inventive concepts, a thickness of first insulation pattern 270 may be more than quarter a width (a distance along the x-axis direction) of isolation trench 107. First insulation pattern 270 and the first conductive pattern 286 may constitute a first structure SC.
The first conductive pattern 286 may completely fill isolation trench 107 surrounded by first insulation pattern 270. The first conductive pattern 286 may be formed to include at least one of a polysilicon layer and a metal layer. The first conductive pattern 286 and first insulation pattern 270 may be formed using a planarization process. Channel holes 105 may be formed to penetrate stack structure 100. Channel holes 105 may expose substrate 10.
Referring to
Referring to
Referring to
Referring to
Referring to
A fourth impurity region 274 may be formed in an upper portion of first structure SC, and third impurity regions 261 may be formed in respective ones of upper portions of the channel structures VS. The third and fourth impurity regions 261 and 274 may be formed, for example, by removing upper portions of filing patterns 181 and second insulation patterns 183 to form recessed regions, filling the recessed regions with semiconductor material patterns, and doping the semiconductor material patterns with impurity ions.
The fourth impurity region 274 may be doped with impurity ions having the same conductivity type as substrate 10, and the third impurity regions 261 may be doped with impurity ions having a different conductivity type from that of substrate 10, for example. When the third impurity regions 261 have a different conductivity type from the fourth impurity region 274, the third and fourth impurity regions 261 and 274 may be formed using a plurality of separate ion implantation processes. Subsequently, first upper interconnections 263 and a second upper interconnection 273 may be formed on the substrate including the third and fourth impurity regions 261 and 274. The first upper interconnections 263 may be electrically connected to the channel structures VS through first upper plugs 262, and the second upper interconnection 273 may be electrically connected to first structure SC through second upper plugs 272.
Referring to
Isolation trench 107 may have a shape that a plurality of circles are arrayed in the y-axis direction and portions of the circles overlaps with each other when viewed from a plan view. Channel holes 105 may be arrayed in a plurality of rows which are parallel with the y-direction. Channel holes 105 in each row may be arrayed zigzag along the y-axis direction and may be spaced apart from each other. In an exemplary embodiment in accordance with principles of inventive concepts, channel holes 105 arrayed in each row may include even-numbered channel holes 105 and odd-numbered channel holes 105, and the even-numbered channel holes 105 may be shifted by a predetermined distance in the x-axis direction from a straight line in which the odd-numbered channel holes 105 are arrayed. Thus, distances between isolation trench 107 and the pair of adjacent channel holes 105 arrayed in the y-axis direction may be different from each other. Accordingly, the above array of channel holes 105 may increase the integration density of the memory cell array region in terms of a planar area.
Referring to
Referring to
Referring to
Referring to
Referring to
A second impurity region 240 may be formed in substrate 10. The second impurity region 240 may be formed prior to formation of stack structure 100. The second impurity region 240 may be formed to have a predetermined depth from a top surface of substrate 10 and to have a different conductivity type from substrate 10.
Referring to
Referring to
Referring to
Referring to
Referring to
Third impurity regions 261 may be formed in respective ones of upper portions of the channel structures VS. Third impurity regions 261 may be formed to have the same conductivity type as second impurity region 240. First upper interconnections 263 and first upper plugs 262 may be formed on the substrate including third impurity regions 261. The first upper interconnections 263 may be electrically connected to the third impurity regions 261 through the first upper plugs 262.
In the present embodiment, a fifth impurity region 249 may be formed in the second impurity region 240 under first structure SC. Further, contact plugs 271 may be formed to penetrate first insulation pattern 270. Contact plugs 271 may be connected to the fifth impurity region 249. The fifth impurity region 249 may provide an ohmic contact between the second impurity region 240 and contact plugs 271. The fifth impurity region 249 may have the same conductivity type as the second impurity region 240 and may have a different conductivity type from that of substrate 10. An impurity concentration of the fifth impurity region 249 may be greater than that of the second impurity region 240. The process of forming the fifth impurity region 249 may be performed after formation of isolation trench 107 described with reference to
Referring to
A second stack structure 102 may be formed on first insulation pattern 270 and first stack structure 101. Second stack structure 102 may also be formed by alternately and repeatedly stacking insulation layers 120 and sacrificial layers 130. Second stack structure 102 may be patterned to form an upper isolation trench 108 that penetrates second stack structure 102 to expose first insulation pattern 270. During formation of the upper isolation trench 108, an upper portion of first insulation pattern 270 may be recessed. A second insulation pattern 277 may be formed to fill the upper isolation trench 108.
Referring to
According to an exemplary embodiment, channel holes 105 may be formed by successively etching the first and second stack structures 101 and 102 after formation of second insulation pattern 277, and the channel structures VS may be formed in respective ones of channel holes 105. Alternatively, first semiconductor layers (not shown) may be formed to penetrate first stack structure 101 after formation of first insulation pattern 270, and second semiconductor layers (not shown) connected to the first semiconductor layers may be formed to penetrate second stack structure 102 after formation of second insulation pattern 277.
Referring to
Peripheral transistors PT may be provided on and in substrate 10 in first peripheral circuit region PER1. Peripheral transistors PT may be formed on and in active regions defined by an isolation layer 115. Peripheral transistors PT may constitute a column decoder, a sense amplifier or other control circuits, for example. A protecting insulation layer 111 may be provided to cover peripheral transistors PT. The protecting insulation layer 111 may be formed to include at least one of a silicon oxide layer and a silicon oxynitride layer. Second peripheral circuit region PER2 may include a row decoder and other control circuits.
A stack structure 100 may be formed on substrate 10 including peripheral transistors PT and the protecting insulation layer 111 covering peripheral transistors PT. Stack structure 100 may be formed by alternately and repeatedly stacking insulation layers 121-125 and sacrificial layers 131-134. Stack structure 100 may be formed to cover cell array region CAR, the pad regions PD1 and PD2, and the peripheral circuit regions PER1 and PER2.
Referring to
A pad mask pattern 112 may be formed on the patterned stack structure 100. A width of pad mask pattern 112 in the x-axis direction may be less than a width of the patterned stack structure 100 in the x-axis direction. Further, a width of pad mask pattern 112 in the y-axis direction may be less than a width of the patterned stack structure 100 in the y-axis direction. Thus, even after pad mask pattern 112 is formed, a top surface of an edge of the patterned stack structure 100 may be still exposed. Pad mask pattern 112 may be formed to include at least one of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, for example.
In an exemplary embodiment in accordance with principles of inventive concepts, pad mask pattern 112 may be formed on stack structure 100 before patterning stack structure 100, and stack structure 100 may be patterned using pad mask pattern 112 as an etch mask to remove a portion of stack structure 100, which is located in the peripheral circuit regions PER1 and PER2. In this case, pad mask pattern 112 may be isotropically etched to form a shrunk mask pattern. A width of the shrunk pad mask pattern 112 in the x-axis direction may be less than a width of the patterned stack structure 100 in the x-axis direction, and a width of the shrunk pad mask pattern 112 in the y-axis direction may also be less than a width of the patterned stack structure 100 in the y-axis direction.
Referring to
After formation of the first pad Pa1, the shrunk pad mask pattern 112 may be isotropically etched again to form a second shrunk pad mask pattern 112. Using the second shrunk pad mask pattern 112 as an etch mask, the insulation layers 124-125 and the sacrificial layers 134-134 may be etched to expose edges of the insulation layer 123 and form the second pad Pa2. Thus, the isotropic etching process for shrink of pad mask pattern 112 and the anisotropic etching process of some of the insulation layers and the sacrificial layers may be alternately and repeatedly performed to form the step structural pads Pa1-Pa4. That is, the step structural pads Pa1-Pa4 may be formed using pad mask pattern 112 as a consumption mask. The pads Pa1-Pa4 may be formed on the pad regions PD1 and PD2. The shrunk pad mask pattern 112 may be removed after formation of the pads Pa1-Pa4.
After formation of the pads Pa1-Pa4 and removal of the shrunk pad mask pattern 112, a first interlayer insulation layer 114 may be formed to cover stack structure 100 having the step structural pads Pa1-Pa4. First interlayer insulation layer 114 may cover the peripheral circuit regions PER1 and PER2 as well as stack structure 100. First interlayer insulation layer 114 may expose the uppermost insulation layer (e.g., the fifth insulation layer 125). In an exemplary embodiment in accordance with principles of inventive concepts, forming first interlayer insulation layer 114 may include forming an insulation layer (not shown) on an entire surface of the substrate having the pads Pa1-Pa4 and planarizing first interlayer insulation layer 114 until a top surface of the fifth insulation layer 125 is exposed. First interlayer insulation layer 114 may be formed of at least one of an undoped silicate glass (USG) material, a tetra-ethyl-ortho-silicate (TEOS) material, a boro-silicate-glass (BSG) material and a boro-phospho-silicate-glass (BPSG) material, for example.
Referring to
In the present embodiment, the at least one isolation trench 107 may prevent stack structure 100 from being deformed due to the non-uniform distribution of the stresses applied to the edges of stack structure 100. That is, the at least one isolation trench 107 may relieve and/or alleviate the non-uniform stresses generated by shrink of first interlayer insulation layer 114 and the sacrificial layers 131-134 during the subsequent high temperature processes.
First impurity regions 245 may be formed in substrate 10 under the isolation trenches 107. In an exemplary embodiment in accordance with principles of inventive concepts, first impurity regions 245 may have the same conductivity type as substrate 10 and may have a higher impurity concentration than substrate 10. In another embodiment, first impurity regions 245 may have a different conductivity type from substrate 10. In still another embodiment, the process of forming first impurity regions 245 may be omitted.
Referring to
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Each of the electrode structures HS may include a data storage layer 220 conformally covering an inner surface of the recessed region and an electrode pattern 230 filling the recessed region surrounded by data storage layer 220. Detailed configurations of data storage layer 220 will be described hereinafter with reference to
Buried insulation layers 250 may be formed in respective ones of first trenches 200. Buried insulation layers 250 may be formed of at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.
Referring to
Further, second upper interconnection lines 273 may be formed between the second and third interlayer insulation layers 116 and 117. Second upper interconnection lines 273 may be formed on first structures SC and may be formed to extend in the y-axis direction. That is, second upper interconnection lines 273 may extend to cross first upper interconnection lines 263. In the event that first impurity regions 245 are formed, some additional structures may be provided to electrically connect second upper interconnection lines 273 to first impurity regions 245. The additional structures for electrically connecting second upper interconnection lines 273 to first impurity regions 245 may correspond to contact plugs 271 illustrated in
Each of the electrode structures HS, which are vertically stacked, may be electrically connected to any one of third upper interconnection lines 276 extending along the x-axis direction in first pad regions PD1. Third upper interconnection lines 276 may be electrically connected to the electrode structures HS through the pads and contact plugs (not shown) formed in first pad regions PD1. Third upper interconnection lines 276 may extend onto second peripheral circuit region PER2. In the event that the uppermost electrode structure HS correspond to string selection lines SSL, the string selection lines SSL separated from each other along the x-axis direction by buried insulation layers 250 may be electrically connected to respective ones of fourth upper interconnection lines 275.
Referring to
First structures may further include second sub-structures SB2 provided between the outermost rows R1 and R2 and the second pad regions PD2. In an exemplary embodiment in accordance with principles of inventive concepts, the second sub-structures SB2 may be substantially parallel with the first sub-structures SB1. Second sub-structures SB2 may be disposed between cell array region CAR and second pad regions PD2. Second sub-structures SB2 may be formed in respective ones of second isolation trenches T2 that at least partially cross stack structure 100. First and second isolation trenches T1 and T2 may be simultaneously formed, and first and second sub-structures SB1 and SB2 may also be simultaneously formed.
In an exemplary embodiment in accordance with principles of inventive concepts, the at least one third sub-structure SB3 may include a pair of third sub-structures SB3. In this case, one of the third sub-structure SB3 may be connected to first ends of the second sub-structures SB2, and the other of the third sub-structure SB3 may be connected to second ends of the second sub-structures SB2. Thus, the second and third sub-structures SB2 and SB3 may constitute a closed loop to surround stack structure 100. The second and third sub-structures SB2 and SB3 may be simultaneously formed. According to the present embodiment, the third sub-structures SB3 may be spaced apart from the first sub-structures SB1.
Referring to
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Each of the stack structures 100 may include word lines WL, buried insulation layers FL1 and FL2 (hereinafter, referred to as FL) crossing the word lines WL, and bit lines BL crossing the word lines WL. The buried insulation layers FL may intersect at least portions of the word lines WL. The buried insulation layers FL may have the same configuration as disclosed in any one of the exemplary embodiment in accordance with principles of inventive concepts described with reference to
In an exemplary embodiment, buried insulation layers FL may include first buried insulation layers FL1 extending in the x-axis direction to completely intersect the word lines WL and/or second buried insulation layers FL2 extending in the x-axis direction to partially intersect the word lines WL. Even though not shown in the drawings, channel structures may be disposed between the buried insulation layers FL.
First structures SC may be disposed between buried insulation layers FL. First structures SC may include a first group of structures SCA completely crossing the word lines WL, as illustrated in
In each of the stack structures 100, first structures SC may be disposed to have the same configuration or different configurations from each other. For example, as illustrated in
The shape of first structures SC may not be limited to a straight line. That is, first structures SC may have a different shape from the straight line, such as a sawtooth-shaped configuration in a plan view and may extend in the x-axis direction, as illustrated in
Referring to
The charge storage layer CL may be one of insulation layers including a substantial number of trap sites or a substantial number of nano-particles and may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. For example, the charge storage layer CL may be formed of an insulation layer including the trap sites, a floating gate or conductive nano-dots. In an exemplary embodiment in accordance with principles of inventive concepts, the charge storage layer CL may be formed to include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon rich nitride layer, a nano-crystalline silicon layer and a laminated trap layer.
Tunnel insulation layer TIL may be formed to include one of material layers having a relatively wider band gap than the charge storage layer CL and may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. For example, tunnel insulation layer TIL may be formed of a silicon oxide layer using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. Further, tunnel insulation layer TIL may be subject to a predetermined annealing process prior to deposition of the charge storage layer CL. The annealing process may correspond to a normal annealing process employing at least one of a nitrogen gas and an oxygen gas as an ambient gas or a rapid thermal nitridation (RTN) process.
Blocking insulation layer BLL may be a single layered insulation layer. Alternatively, blocking insulation layer BLL may include a multi-layered insulation layer, for example, a first blocking insulation layer and a second blocking insulation layer. First blocking insulation layer may be formed of a different material layer from second blocking insulation layer. One of the first and second blocking insulation layers may be formed of a material having an energy band gap which is less than an energy band gap of the tunnel insulation layer TIL and is greater than an energy band gap of the charge storage layer CL. The first and second blocking insulation layers may be formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In an exemplary embodiment in accordance with principles of inventive concepts, first blocking insulation layer may be formed of a high-k dielectric layer such as an aluminum oxide layer or a hafnium oxide layer, and second blocking insulation layer may be formed of a material layer having a dielectric constant which is less than that of first blocking insulation layer. Alternatively, second blocking insulation layer may be formed of a high-k dielectric layer, and first blocking insulation layer may be formed of a material layer having a dielectric constant which is less than that of second blocking insulation layer.
Referring to
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The electronic system 1100 may include a controller 1110, an input/output (I/O) unit 1120, a memory device 1130, an interface unit 1140 and a data bus 1150. At least two of the controller 1110, the I/O unit 1120, the memory device 1130 and the interface unit 1140 may communicate with each other through the data bus 1150. That is, the data bus 1150 may correspond to a path through which electrical signals are transmitted.
The controller 1110 may include at least one of a microprocessor, a digital signal processor (DSP), a microcontroller or the like. The memory device 1130 may store commands executed by the controller 1110. The I/O unit 1120 may receive data or signals from an external device or may transmit data or signals to the external device. The I/O unit 1120 may include a keypad, a keyboard or a display unit.
The memory device 1130 may include at least one of the semiconductor devices according to the exemplary embodiments in accordance with principles of inventive concepts described above. The memory device 1130 may further include another type of semiconductor memory devices which are different from the semiconductor devices described in the above embodiments. For example, the memory device 1130 may further include a magnetic memory device, a phase change memory device, a dynamic random access memory (DRAM) device and/or a static random access memory (SRAM) device. The interface unit 1140 may transmit electrical data to a communication network or may receive electrical data from the communication network.
Referring to
The memory controller 1220 may include a static random access memory (SRAM) device 1221, a central processing unit (CPU) 1222, a host interface unit 1223, an error check and correction (ECC) block 1224 and a memory interface unit 1225. The SRAM device 1221 may be used as an operation memory of the CPU 1222. The host interface unit 1223 may be configured to include a data communication protocol between the memory card 1200 and the host. The ECC block 1224 may detect and correct errors of data which are read out from the flash memory device 1210. The memory interface unit 1225 may connect the memory controller 1220 to the memory device 1210. The central processing unit (CPU) 1222 may control overall operations for data communication of the memory controller 1220. Even though not shown in the drawings, the memory card 1200 may further include a read only memory (ROM) device that stores code data to interface with the host.
Referring to
The flash memory unit 1310 may store data processed by the CPU 1330 or data transmitted from an external system. The flash memory unit 1310 may be configured to include a solid state disk. In this case, the flash memory unit 1310 constituting the information processing system 1300 may stably and reliably store a large capacity of data. If the reliability of the flash memory unit 1310 is improved, the information processing system 1300 may save sources that are required to check and correct data. As a result, the information processing system 1300 may provide fast data communication. Even though not shown in the drawings, the information processing system 1300 may further include a camera image processor, an application chipset and/or an input/output unit.
The semiconductor devices according to exemplary embodiments in accordance with principles of inventive concepts described above may be encapsulated using various packaging techniques. For example, the semiconductor devices according to the aforementioned exemplary embodiments may be encapsulated using any one of a package on package (POP) technique, a ball grid arrays (BGAs) technique, a chip scale packages (CSPs) technique, a plastic leaded chip carrier (PLCC) technique, a plastic dual in-line package (PDIP) technique, a die in waffle pack technique, a die in wafer form technique, a chip on board (COB) technique, a ceramic dual in-line package (CERDIP) technique, a plastic quad flat package (PQFP) technique, a thin quad flat package (TQFP) technique, a small outline package (SOIC) technique, a shrink small outline package (SSOP) technique, a thin small outline package (TSOP) technique, a system in package (SIP) technique, a multi chip package (MCP) technique, a wafer-level fabricated package (WFP) technique and a wafer-level processed stack package (WSP) technique.
According to the embodiments set forth above, a stack structure may be formed by alternately and repeatedly stacking at least two different material layers, and the stack structure may be covered with an interlayer insulation layer having a different stress from the stack structure. Thus, physical stresses may be generated in the stack structure and interlayer insulation layer, and the physical stresses may be applied to channel structures which are formed to penetrate the stack structure. As a result, the channel structures may be deformed by the physical stresses, thereby degrading electrical characteristics and reliability of a semiconductor device including the channel structures. However, according to the embodiments, the stack structure may be patterned to form at least one isolation trench in the stack structure and to form an insulation pattern in the isolation trench, prior to formation of the channel structures. Thus, the physical stresses in the stack structure may be significantly relieved or alleviated because of the presence of the insulation pattern that partially or completely splits the stack structure into a plurality of sub-stack structures. Accordingly, the insulation pattern can prevent the channel structures from being deformed.
Furthermore, at least one first impurity region may be formed in the substrate under the isolation trench, and the first impurity region may act as a substrate pick-up region.
While the inventive concept has been described with reference to exemplary embodiments in accordance with principles of inventive concepts, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2011-0012553 | Feb 2011 | KR | national |
| 10-2011-0043618 | May 2011 | KR | national |
