Patent Application
20070281432
Features and advantages of the invention may be readily appreciated by persons skilled in the art from the following detailed description of exemplary embodiments thereof, as illustrated in the accompanying drawings, in which:
In the following detailed description and in the several figures of the drawing, like elements are identified with like reference numerals.
In an exemplary embodiment, each transistor 2 may have a shallow trench isolation (STI) trench 4. In an exemplary embodiment, the trench 4 may be formed in a surface of the silicon substrate 3. In an exemplary embodiment, the trench 4 may be about 30 nm to about 350 nm wide and have an aspect ratio of approximately 1 to 200 or have a width in a range from about 100 nm to about 200 nm and an aspect ratio in a range from about 10 to about 100.
In an exemplary embodiment, each transistor 2 may have a source portion 5 and a drain portion 6. In an exemplary embodiment, each transistor 2 may have a gate 7 between the source 5 and the drain 6 portions. In an exemplary embodiment, the source, drain and gate may be fabricated using thin film production technology or methods.
The substrate 3, on which the inverter 1 may have been formed, may include strained silicon portions 9, for example, interlocking strained silicon portions. In an exemplary embodiment, the interlocking strained silicon portions may be located under the shallow trench isolation (STI) trenches 4 for their respective transistors 2 of the inverter 1.
In an exemplary embodiment, the inverter 1 may include transistors 2 of a first type 21 and a second type 22. In an exemplary embodiment, the first type may be a pFET transistor 21 and the second type may be an nFET transistor 22, for example, the first type may be a p MOS FET transistor 21 and the second type may be an n MOS FET transistor 22 (MOS: Metal Oxide Semiconductor).
The interlocking strained silicon portions 9 of the first type of transistor 21 may include at least one strain type portion 91 aligned in a first direction and a second strain type portion 92 aligned in an orthogonal direction, for example at about a 90 degree angle. It should be noted that the orthogonal direction may comprise a direction in two dimension, i.e., an orthogonal direction that is in a plane that is parallel to the main surface of the substrate 3 or in an orthogonal direction that is in a plane perpendicular to the main surface of the substrate 3. In an exemplary embodiment, the first strain type portion 91 may be tensile strain portion 91 and the second strain type portion 92 may be a compressive strain portion 92.
The strained portions 9, 91, 92 may be formed in holes etched into the silicon. In an exemplary embodiment, the portions may be formed by exemplary methods similar to those described and discussed below with respect to
In an exemplary embodiment, the STI trench 4 may have an arbitrary cross section, e.g., the cross section of a polygon, for example a quadrilateral or square cross section. In an exemplary embodiment, the gate portion 7 may run parallel with two of the STI sides and approximately perpendicular with the other two STI sides.
In an exemplary embodiment, the STI trench of a transistor may be about 200 nm to several μm, e.g., about 200 nm to 400 nm, long depending on the selected layout along the outside edge of each leg of the trench. In an exemplary embodiment, the pFET and nFET share a common gate portion 7 as shown in
The nFET transistor 22 may include tensile strain portions 91. In an exemplary embodiment, the tensile strain portions 91 may be arranged in an array running parallel with the edges of the STI trench 4, for example in a line parallel with the edges of the STI trench 4. In an exemplary embodiment, the nFET transistor 22 may include tensile strain portions 91 along each side of the STI trench 4.
The pFET transistor 21 may include tensile strain portions 91 and compressive strain portions 92. In an exemplary embodiment, the tensile strain portions 91 of the pFET may run along sides of the STI trench 4 that are approximately perpendicular with the gate 7. The compressive strain portions 92 may be arranged along sides of the STI trench 4 that run approximately parallel with the gate portion 7.
In an exemplary embodiment, the nFET 22 may be formed alongside the pFET 21.
The method 30 may include providing a silicon substrate. In an exemplary embodiment, the method includes providing the source, drain and gate for both an nFET and pFET, respectively. In an exemplary embodiment, the nFET and pFET may be arranged in close proximity to one another. In an exemplary embodiment, providing the source, drain and gate may be performed after the formation of the trenches. However, in an alternative embodiment of the invention, the source, drain and gate may be formed before the formation of the trenches.
In an exemplary embodiment as shown by step 31, the method may include providing strain holes (see
In an exemplary embodiment, providing the holes may include providing tensile strain holes and providing compressive strain holes (as noted by regions 32 and 33 in
In an exemplary embodiment, the tensile strain holes may be etched such that they are bigger than the compressive strain holes, which are etched as well.
However, in an alternative embodiment of the invention, the tensile strain holes may be etched such that they have the same size as or are smaller than the compressive strain holes. In this embodiment of the invention, the tensile strain holes would be etched first, then filled and after the filling of the tensile strain holes, the compressive strain holes would be etched.
In another exemplary embodiment of the invention, the tensile strain holes and the compressive strain holes may be etched at the same time (and may optionally have the same size). In this case, a mask is used for defining a first type of holes (the compressive strain holes), which should not be filled with the tensile material. Using the mask, the still exposed holes are filled with the tensile material. Next, the holes that have been covered by means of the mask are opened and the thus exposed holes are then filled with compressive material.
Referring back to the embodiment shown in
The method 30 may include, in step 35, providing tensile material in the tensile strain holes. Providing tensile material in the tensile strain holes may include depositing SiN into the tensile strain holes. As an alternative tensile material, Al2O3 (optionally plus polysilicon), SiO2, HfO2, ZrO2, W, TaN, TiSiN, TaSiN, Si:C (e.g., up to 1.5% or up to 10%) or TiN (optionally plus polysilicon) may be provided in the tensile strain holes. Furthermore, any combination of the above-mentioned materials can be used as the tensile material. Moreover, the deposition may be carried out using eptiaxy.
The method 30 may include, in step 36, providing compressive strain regions. In an exemplary embodiment, providing the compressive strain regions may include reoxidation (step 37) of polysilicon that has previously deposited into the compressive strain holes or depositing (step 38) compressive strain material into the compressive strain holes. Depositing compressive strain material may include depositing a compressive strain material into the compressive strain holes until a strain conversion has occurred. The compressive strain material may include epitaxial SiGe. In an exemplary embodiment, the compressive strain material may be deposited by means of chemical vapor deposition. As an alternative compressive material, carbon, SiO2 (deposited or oxidized) or SiON may be provided
The method 30 further may include removing material from the surface, as indicated in step 39. Removing material from the surface may include an anisotropic trench etch.
The method 30 further may include filling the formed trench(es) with, for example, polysilicon. This is shown in step 40.
In an exemplary embodiment, the method 30 may include planarizing step 41. In an exemplary embodiment, planarizing may include using a chemical/mechanical polish (CMP) or an etch, e.g., a reactive ion etching.
In an exemplary embodiment, the substrate may further be processed according to known processes. These processes may include the formation of the STI, the well implantation, the formation of the gate, the source and the drain including spacers and possible source and drain extensions, the formation of passivation, contacts and the respective metal contacting layers.
The method 50 may further include providing tensile portions, as shown in step 55. In an exemplary embodiment, providing tensile portions may include depositing tensile material in the tensile strain holes, e.g., by means of chemical vapor deposition, by means of oxidation, by means of atomic layer deposition or by means of changing the morphology of the layers, e.g., rapid thermal processing (RTP) steps.
The method 50 may include providing compressive portions, as shown in step 56. In an exemplary embodiment, providing the compressive portions may include either reoxidation (box 57) or depositing (box 58) compressive strain material. In an exemplary embodiment, the compressive strain material may comprise SiGe.
In an exemplary embodiment, the method 50 may include filling and recess steps 59 and 60. In an exemplary embodiment, filling may include filling with polysilicon. In an exemplary embodiment, recessing may include chemical mechanical polishing (CMP).
In an exemplary embodiment, the method 50 may include stripping the layer sequence in the large holes, e.g., the used hard mask or the used photoresist. This is illustrated by step 61.
The method 50 may include a second fill process 62, for example a polysilicon fill.
The method 50 may further include a planarizing step 63. In an exemplary embodiment, planarizing may include a CMP.
The substrate may further be processed according to a typical process, e.g., including the process steps as described above.
In an exemplary embodiment, the tensile strain holes 73, 74 for the tensile strain portion 91 and the compressive strain portion 92 for both an nFET and a pFET of an inverter pair of transistors may be formed in a common etch step.
It should be noted that the above-described processes can also be provided for only nFETs or for only pFETs. Thus, any arbitrary transistor arrangement can be formed in this way and the invention is not limited to the formation of an inverter.
Although the foregoing has been a description and illustration of specific embodiments of the invention, various modifications and changes thereto can be made by persons skilled in the art without departing from the scope and spirit of the invention as defined by the following claims.
In one embodiment of the invention, the stress conversion from tensile stress to compressive stress is achieved by providing TiN and polysilicon into the holes and then oxidizing the materials in the respective holes. This reaction results in TiN and SiO2.
In another embodiment of the invention, the stress conversion from tensile stress to compressive stress is achieved by providing SiN into the holes and then oxidizing the SiN in the respective holes. This reaction results in SiON.
In yet another embodiment of the invention, the stress conversion from tensile stress to compressive stress is achieved by providing Al2O3 and polysilicon into the holes and then oxidizing the materials in the respective holes. This reaction results in Al2O3 and SiO2.
In one embodiment of the invention, the stress conversion from compressive stress to tensile stress is achieved by providing carbon into small holes and into larger holes and then ashing the carbon. The ashed carbon will be pulled back into the smaller holes. Furthermore, the carbon in the larger holes will be removed completely.
