Patent Application
20230055891
Common transistor devices for power applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). U.S. Pat. No. 9,680,004 B2 discloses a power MOSFET including a metal gate electrode in a gate trench having a stripe shape. The power MOSFET also includes a field plate in a field plate trench which has a columnar or needle shape. The field plate provides charge compensation and offers an opportunity to reduce the area specific on resistance of the MOSFET device.
Transistor devices having even better performance would be desirable.
According to the invention, a transistor device comprises a semiconductor body comprising a plurality of transistor cells comprising a drift region of a first conductivity type, a body region of a second conductivity type forming a first pn junction with the drift region, the second conductivity type opposing the first conductivity type, a source region of the first conductivity type forming a second pn junction with the body region, a columnar field plate trench extending into a major surface of a semiconductor body and comprising a columnar field plate and a gate trench structure extending into the major surface of the semiconductor body and comprising a gate electrode. At least one of the depth and doping level of the body region locally varies within the transistor cell to improve VGSTH homogeneity within the transistor cell.
In some embodiments, the gate trench structure comprises a first section extending in a first lateral direction and a second section extending in a second lateral direction that is different from the first lateral direction, wherein the second section intersects with the first section at an intersection.
The angle α formed between the first and second lateral sections may be 0°<α<180°.
In some embodiments, the depth of the body region is greater at the intersection of the gate trench structure than in a region bounding the columnar field plate trench and/or the doping level of the body region is higher at the intersection of the gate trench structure than in a region bounding the columnar field plate trench.
In some embodiments, a maximum dopant concentration at the intersection of the gate trench is at least 1.1 times and at most ten times a maximum dopant concentration of a region bounding the columnar field plate trench.
In some embodiments, a maximum net dopant concentration of the semiconductor body at a position adjacent a side wall of the intersection of the gate trench is at least 1.1 times or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body at a position adjacent a side wall of the columnar field plate trench.
In some embodiments, in a plane of the semiconductor body, a maximum net dopant concentration of the semiconductor body at a position adjacent a side wall of the intersection of the gate trench is at least 1.1 times or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body at a position adjacent a side wall of the columnar field plate trench.
In some embodiments, the depth of the body region in the region of the intersection is tint and the depth of the body region adjacent the columnar field plate trench is tbody, and the doping level of the body region at the intersection is Dint and the doping level of the body region adjacent the columnar field plate trench is Dbody, wherein tint>1.05tbody or tint>1.01tbody and/or Dint22 1.1Dbody or Dint>1.2Dbody
In some embodiments, in a plane of the semiconductor body that is positioned between the main surface of the semiconductor body and the depth tbody, the maximum net dopant concentration of the semiconductor body at a lateral position adjacent the side wall of the intersection of the gate trench is at least 1.1 times or at least 1.2 times and at most ten times the maximum net dopant concentration of the semiconductor body at the lateral position adjacent the side wall of the columnar field plate trench.
In some embodiments, the transistor device further comprises a plurality of columnar field plate trenches arranged in a regular array. The regular array may be an array of rows and columns, such as a square grid array, or may be a hexagonal array.
In some embodiments, the first section of the gate trench structure is arranged between adjacent ones of the columnar field plate trenches and the second section of the gate trench structure is arranged between adjacent ones of the columnar plate trenches.
In some embodiments, the gate trench structure comprises a grid structure formed by a plurality of first sections intersecting a plurality of second sections and forming a plurality of intersections, and the gate electrode has a grid structure, wherein a pair of first sections and a pair of second sections bound one of the plurality of columnar field plate trenches.
In some embodiments, the first sections extend substantially parallel to one another, the sections extend substantially parallel to cone another and the first and second sections extend substantially perpendicular to one another and form a square grid or a rectangular grid.
In some embodiments, the gate trench structure comprises a grid structure formed by a plurality of first sections intersecting a plurality of second sections and forming a plurality of intersections, and the gate electrode has a grid structure, wherein the grid structure has a hexagonal form.
In embodiments in which the grid structure is hexagonal, the columnar field plate trenches may be arranged in a regular hexagonal array.
In some embodiments, at least one of the depth and the doping level of the body region varies laterally between adjacent ones of the plurality of intersections and/or between the intersection and the columnar field plate trench.
In some embodiments, the body region comprises a higher doping level in a region adjacent the intersection than in a region positioned between neighbouring two intersections, and/or the body region comprises a higher doping level in a region adjacent the intersection than in a region adjacent the columnar field plate trench, and/or the body region extends deeper into the semiconductor body at the intersection than in a region positioned between two neighbouring intersections, and/or the body region extends deeper into the semiconductor body adjacent the intersection than in a region positioned adjacent the columnar field plate trench.
In some embodiments, the depth of the gate trench at the intersection is greater than the depth of the gate trench adjacent the intersection.
A method of fabricating a transistor device is provided, the transistor device comprising a columnar field plate trench extending into a major surface of a semiconductor body comprising a first conductivity type, the columnar field trench comprising a columnar field plate, and a gate trench structure comprising an elongate gate trench having a length, the elongate gate trench extending into the major surface of the semiconductor body and comprising a gate electrode, a lateral spacing between the columnar field plate trench and the elongate gate trench varying along the length of the elongate gate trench. The method comprises implanting dopants of a second conductivity type into the major surface of the semiconductor body to form a body region in the semiconductor body, wherein the second conductivity type opposes the first conductivity type and implanting dopants of the second conductivity type into predetermined regions of the main surface of the semiconductor body so that at least one of the depth and doping level of the body region varies laterally.
In some embodiments, the dopants of the second conductivity type are implanted into predetermined regions of the main surface of the semiconductor body so that at least one of the depth and doping level of the body region varies laterally and varies locally within each transistor cell of the transistor device to improve VGSTH homogeneity within the transistor cell.
In some embodiments, the dopants of the second conductivity type are implanted into predetermined regions of the main surface of the semiconductor body so that at least one of the depth and doping level of the body region varies laterally with a predetermined pattern, for example has a laterally regular variation in value, across the cell field of the transistor device.
In some embodiments, the method further comprises, after implanting the dopants of the second conductivity type into the regions of the body region, annealing the semiconductor body.
In some embodiments, the method further comprises forming a source region of the first conductivity type in the major surface of the semiconductor body.
In some embodiments, the gate trench structure comprises a first section extending in a first lateral direction and a second section extending in a second lateral direction that is different from the first lateral direction. The second section intersects with the first section at an intersection and the discrete region is arranged at the intersection. The discrete region may extend laterally outwardly from the side wall of the gate trench structure into the semiconductor body by a predetermined distance.
In some embodiments, the transistor device comprises a plurality of columnar field plate trenches in the major surface of the semiconductor body, the plurality of columnar field plate trenches being arranged in a regular array.
In some embodiments, the gate trench structure comprises a grid structure formed by a plurality of first sections intersecting a plurality of second sections to form a plurality of intersections and the gate electrode has a grid structure. A pair of first sections and a pair of second sections laterally surround of the plurality of columnar field plate trenches. The regions are arranged at the intersections so that at least one of the depth and doping level of the body region varies laterally between the columnar field plate trench and the intersection.
The discrete region may extend laterally from the side wall of the gate trench structure towards the side wall of the field plate trench.
In some embodiments, the gate trench structure comprises a grid structure formed by a plurality of first sections intersecting a plurality of second sections to form a plurality of intersections and the gate electrode has a grid structure having a hexagonal form in plan view. The regions are arranged at the intersections so that at least one of the depth and doping level of the body region varies laterally between the columnar field plate trench and the intersection.
The discrete region may extend laterally from the side wall of the gate trench structure towards the side wall of the field plate trench.
In some embodiments, the intersections of the gate trench structure are formed in the regions.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and are detailed in the description which follows.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, thereof, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.
As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.
As employed in this specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
As used herein, various device types and/or doped semiconductor regions may be identified as being of n type or p type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either n or p type and the second type then is either p or n type.
The FIGS. illustrate relative doping concentrations by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n−” means a doping concentration which is lower than the doping concentration of an “n”—doping region while an “n+”—doping region has a higher doping concentration than an “n”—doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”—doping regions may have the same or different absolute doping concentrations.
MOSFET devices using needle-shaped field plates positioned in needle-shaped field plate trenches can suffer from a strong RonA(VGSTH) dependency, which can prevent the use of this design concept for low voltage technologies, where RonA below 10V is relevant. Such devices can exhibit so called “early turn on”.
It is thought that the grid-like gate design commonly used for transistor structures including an array of needle-shaped field plate trenches leads to a non-homogeneous VGSTH within the transistor cell. Without wishing to be bound by theory, the observed behavior can be described by two MOSFETs coupled in parallel that have different threshold voltages. For example, for a grid-like gate structure, each transistor cell can be considered to include a corner MOSFET arranged at the intersection between two gate trench sections extending in different lateral directions and a straight MOSFET formed with a central section of the gate trench section, i.e. a section of the gate trench section positioned between two neighbouring intersections.
In order to turn on both MOSFETs at the same time (low RonA at any VGSTH), VGSTH of both MOSGETs should match, because otherwise the MOSFET with low VGSTH will conduct first. This leads to a higher RonA in comparison to a homogeneous VGSTH within the cell. With the same body doping level, the corner MOSFET will show a lower VGSTH than the straight MOSFET due to a two directional field effect at the corner of the transistor cell formed by the intersection of the two gate sections (VGSTH measured=min(VGSTH corner, VGSTH straight)).
According to embodiments described herein, a more uniform threshold voltage (VGSTH) is achieved by locally tuning the threshold voltage within the transistor cell. This can be achieved, for example, by locally increasing the doping level of the body region at the intersections of the grid-like gate structure, so as to locally increase the VGSTH of the corner MOSFET and mitigate the effects of the two dimensional electric field at the corner of the transistor cell, i.e. at the intersection of the gate trench sections.
In some embodiments, a second body (“corner body”) is introduced into the transistor structure which is only present in the corners, i.e. at the intersections of the gate trenches. This enables the VGSTH of the corner and straight MOSFET to be tuned separately and to be set to have a more similar value that may even be substantially the same. Furthermore, the additional corner body enables the length of the accumulation region in the gate crossings to be tuned separately. Due to locally higher open area, the gate crossings may be etched deeper in comparison to the straight parts. This further enables a QGD tuning.
A second body implant in the gate crossing or intersection region is provided which enables a homogenous VGSTH in needle trench MOSFET technologies. In addition, the QGD in the gate crossing can be reduced. The additional implantation can be detected by top view images, in which the needle trench design and grid-like gate design can be seen, and transfer characterization measurements. Furthermore, the variation in the doping level of the body region can be detected with SSRM (Scanning Spreading Resistance Microscopy) or methods for the characterization of the doping profile of the MOSFET cell, such as SIMS (Secondary Ion Mass Spectroscopy).
The cell field 13 contributes to the switching of the transistor device 10, whereas the edge termination region 15 serves to provide electrical isolation between the active device region, i.e. the cell field 13, and the edge region of the device.
Referring to the cross-sectional view of
The transistor device 10 further comprises a charge compensation structure which comprises a plurality of electrically conductive field plates 26, each field plate 26 being positioned in a field plate trench 23. The field plate trenches 23 extend into the major surface 12 of the semiconductor body 11 and are defined by a base 24 and sidewalls 25 which extend substantially perpendicular to the main surface 12. The field plate 26 is electrically conductive and may be formed of polysilicon, for example. The field plate trench 23 is lined with an electrically insulating layer 39, which is commonly known as a field oxide, to electrically isolate the electrically conductive field plate 26 from the semiconductor body 11. The field oxide 39 typically has a larger thickness than the gate dielectric 17.
The semiconductor body 11 may be formed of a monocrystalline semiconductor body such as a monocrystalline silicon wafer. In some embodiments, the semiconductor body may be formed by epitaxial semiconductor layer, for example an epitaxial silicon layer.
The transistor device 10 is a vertical transistor device with a drain region 27 positioned at a second main surface 28 of the semiconductor body which opposes the main surface 12. The semiconductor body 11 may form the drift region 29 of the transistor device 10 and be lightly doped with a first conductivity type, e.g. n-type. The drain region 27 is highly doped with the first conductivity type, for example n-type. A body region 30 is positioned on the drift region 29 and the comprises dopants of a second conductivity type, e.g. p-type, which opposes first conductivity type. A source region 31 is positioned on or in the body region and comprises dopants of a first conductivity type.
A metallic layer, indicated schematically in
In the top view of
In the embodiment illustrated in
Also illustrated in
As mentioned above, the intersections 37 of the gate structure can cause two dimensional electric field effects which result in a local decrease of the threshold voltage of the transistor cell 14 in the region adjacent and bounded by the perpendicular corner of the gate structure formed at the intersection 37 compared to the threshold voltage of other parts of the transistor cell 14, for example adjacent the field plate trench 23 or adjacent portion of the longitudinal section 35 or transverse section 36 positioned midway between two immediately neighbouring intersections 37. This effect can be mitigated by locally tuning the threshold voltage VGSTH within the area of the transistor cell 14, i.e. VGSTH has different values at different positions within the transistor cell 14, for example at different positions within the region enclosed by a ring of the gate trench grid.
According to some embodiments, the effect of the two-dimensional electric field at the intersection of two gate trenches can be mitigated by locally tuning at least one parameter of the body region 30, for example doping level and/or depth, within the area of the transistor cell 14. In some embodiments, the body region 30 of the transistor device 10 includes at least one parameter having a value that varies depending on the lateral position within the transistor device 10 and also on its lateral position within each transistor cell 14.
In some embodiments, the depth t of the body region 30 and/or a doping level D of the body region 30 varies as a function of its lateral position. The maximum variation in the doping level D of the body region 30 can be around 10 times. The variation may be a minimum of 1.1 times. By locally tuning the doping level D and/or depth t of the body region 30 within the cell 14, the threshold voltage can be locally tuned within the cell so that the threshold voltage is more uniform and early turn on of the transistor device 10 can be avoided.
Each of the regions 40 is arranged at an intersection 37 between a longitudinal gate trench section 35 and a transverse gate trench section 36. Each region 40 has a lateral extent such at it extends from the inner edge of the gate trench section 35, 36 in the immediate vicinity of the intersection 37 towards the field plate trench 23 by a distance. This results in the threshold voltage being locally increased within the region 40 compared to outside of the region 40 so that the effect of the electric field extending from two perpendicular directions at the corner of the transistor cell 14 formed at the intersection 37 by the longitudinal section 35 and transverse section 36 of the gate trench 16 can be mitigated. The threshold voltage of the transistor cell 14 is more uniform or homogeneous over the area of the transistor cell and therefore over the area of the cell field 13.
In the embodiment illustrated in
The columnar field plate trenches 23 and the columnar field plates 26 are arranged in a regular square grid array. The regions 40 are also arranged in a regular square array that has the same pitch but that that is laterally offset from the square grid array of the field plate trenches 23.
The region 40 as depicted in the drawings may correspond to the opening in a mask used for locally implanting additional dopants into the body region 30. In these embodiments, the discrete regions 40 may indicate a region in which a second body implant to implant dopants of the second conductivity type is performed so that the doping level of the body region 30 at and around the intersections 37 between the longitudinal gate trench sections 37 and transverse gate trench sections 36 is locally increased.
The doping level of the body region 30 varies as a function of the lateral position within the cell field 13 and within each transistor cell 14, for example in a lateral direction between the field plate trench 23 to the gate trench 16, in particular to the intersection 37 of the gate trench 16 of that transistor cell 14.
The regions 40 are depicted in
The doping level of the body region 30 at the intersection 37 of the gate trench structure 16 differs from the doping level of the body region 30 at the columnar field trench 23. For example, the doping level of the body region 30 may be higher at in a portion of the semiconductor body 11 positioned immediately adjacent the intersection 37 than in a portion of the semiconductor body positioned immediately adjacent the columnar field trench 23.
In some embodiments, the depth, tint, of the body region 30 from the main surface 12 of the semiconductor body 11 in the region 40 differs from the depth, tbody, of the body region 30 that bounds the columnar field trench 23. For example, the depth of the body region immediately adjacent the intersection 37 may be greater than the depth of the body region immediately adjacent the columnar field plate trench 23.
The depth of the body region 30 can also be defined as the position of the pn junction between the body junction 30 and the drift region 29.
In some embodiments, within each transistor cell 14, a maximum net dopant concentration of the semiconductor body 11 at a position adjacent a side wall of the intersection 37 of the gate trench 16 is at least 1.1 and at most ten times a maximum net dopant concentration of the semiconductor body 11 at a position adjacent a side wall of the columnar field plate trench 23.
In some embodiments, within each transistor cell 14, a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the gate dielectric 17 positioned on the side wall of the gate trench 16 forming the side wall of the intersection 37 is at least 1.1 times or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the field oxide 39 positioned the side wall 25 of the columnar field plate trench 23.
In some embodiments, within each transistor cell 14 and in a plane of the semiconductor body 11, a maximum net dopant concentration of the semiconductor body 11 at a position adjacent a side wall of the intersection 37 of the gate trench 16 is at least 1.ltimes or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body 11 at a position adjacent a side wall of the columnar field plate trench 23.
In some embodiments, within each transistor cell 14 and in a plane of the semiconductor body 11, a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the gate dielectric 17 positioned on the side wall of the gate trench 16 forming the side wall of the intersection 37 is at least 1.1 times or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the field oxide 39 positioned the side wall 25 of the columnar field plate trench 23.
In some embodiments, within each transistor cell 14, in a plane of the semiconductor body 11 that is positioned between the main surface 12 of the semiconductor body 11 and the depth tbody, the maximum net dopant concentration of the semiconductor body 11 at a lateral position adjacent the side wall of the intersection 37 of the gate trench 16 is at least 1.ltimes or at least 1.2 times and at most ten times the maximum net dopant concentration of the semiconductor body 11 at the lateral position adjacent the side wall of the columnar field plate trench 23.
In some embodiments, within each transistor cell 14 and in a plane of the semiconductor body 11 that is positioned between the main surface 12 of the semiconductor body 11 and the depth tbodyr a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the gate dielectric 17 positioned on the side wall of the gate trench 16 forming the side wall of the intersection 37 is at least 1.1 times or at least 1.2 times and at most ten times a maximum net dopant concentration of the semiconductor body 11 at a position adjacent the field oxide 39 positioned the side wall 25 of the columnar field plate trench 23.
The variation in the level of the parameter of the body region 30 in one or more lateral directions and/or the vertical direction may be periodic and correspond to the periodic arrangement of the intersections 37. For example, the regions 40 may be arranged in a regular array corresponding to the regular array of intersections 40.
In some embodiments, at least one of the depth and doping level of the body region 30 varies laterally with a predetermined pattern, for example has a laterally regular variation in value, across the cell field 13 of the transistor device 10.
In some embodiments, such that that illustrated in
In some embodiments, the regions 40 and intersections 37 are arranged in a hexagonal array.
In order to provide increased doping levels in the body region 30 at predetermined regions of the semiconductor body 11, a two-stage process may be used in which dopants comprising the second conductivity type are implanted into the main surface 11 of the semiconductor body 11 uniformly and then a second implantation process is used to implant further dopants of the second conductivity type into predetermined regions of the main surface 12 of the semiconductor body 11. A body drive, or annealing treatment, may be carried out after the first implantation and before the second implantation or only after the second implantation.
In some embodiments, a first implant process is used to form the body region 30 over the entire area of the cell field 13 having a substantially uniform doping level. This first implant process can be carried out first followed by a local or area selective implantation using a second implant process so as to increase the doping level of the body region 30 at preselected regions 40, which are to correspond to the position of the intersections 37 of the gate trench structure 16.
The gate structure for a compensation structure including columnar field plates is not limited to a square grid. In other embodiments, the gate trench structure comprises a first section 35 extending in a first lateral direction A and a second section 36 extending in a second lateral direction B that is different from the first lateral direction A, wherein the second section 36 intersects with the first section 35 at an intersection 37. The angle between the first and second lateral directions 35, 36 may be greater or smaller than 90°, for example 0°<α<90° or 90°<α<180°. For example, the first and second sections 35, 36 may form a triangular, hexagonal or octagonal grid.
The gate electrode 18 also includes first section 35′ arranged in the first gate trench section 35 and a second section 36′ arranged on the second gate trench section 36 which intersect at an intersection 37′. The angle α between the first and second sections 35′, 36′ of the gate electrode 18 is, therefore, also less than 90°. The intersection 37 is arranged between four transistor cells 14 having different shapes in plan view at this intersection, since the angle α between one pair of trench sections 35, 36 is less than 90° and the angle af between the adjoining pair of trench sections 35, 36 is greater than 90°.
The semiconductor body 11 includes a region 40 of the body region 30 which includes a higher doping level than in regions laterally adjacent the region 40. The region 40 extends outwardly from the sidewalls of the intersecting gate trench sections 35, 36. In this embodiment, the region 40 has a square type form with rounded corners with the rounded corners being positioned in the body region 30 of the respective four transistor cells 14.
In the embodiments illustrated in
In the embodiment illustrated in
In the embodiment illustrated in
A region 40 that has a different value of a parameter, for example a higher doping level, is arranged at each of the intersections 37 so that the regions 40 have a hexagonal arrangement in plan view. Each region 40 may be arranged substantially symmetrically about the intersection 37. In this embodiment, each region 40 has a substantially circular form in plan view. However, each region 40 may also have other forms, for example hexagonal or triangular. Each region 40 extends into three adjoining transistor cells 14, each of which can be considered to have a hexagonal shape in plan view.
Each transistor cell 14 includes a columnar field plate trench 23 and field plate 26. The columnar field plate trench 23 and columnar field plate 26 may also have a hexagonal shape in plan view. However, the field plate trench 23 and field plate may have other forms, for example be substantially circular in plan view.
The columnar field plate trenches 23 and the columnar field plates 26 are arranged in a hexagonal array. The regions 40 are also arranged in a hexagonal array that has the same pitch but that is laterally offset from the hexagonal array of the field plate trenches 23.
The transistor device 10 may be used in low-voltage drives (LV drives) applications, such as forklifts, e-bikes and low-speed vehicles, in which high current drive circuitry that is both reliable and compact, yet also cost competitive is desirable. In order to meet the required high current in the above-mentioned applications, one common practice is to couple many discrete MOSFET switches in parallel. In that case, the spread of the threshold voltage (Vth) from the paralleled MOSFETs is undesired, since the MOSFET with lowest Vth would not only turn on first, but also turn off last, therefore overheating by taking more than its share of current. This Vth spread should be kept low over the lifetime of a product. An unwanted early turn on in applications with paralleled MOSFETS can provoke a short in the circuitry, potentially destroying the MOSFETs and components located nearby if the energy is high enough. Some or all of these issues can be mitigated or even overcome by use of a transistor device according to one of the embodiments described herein.
Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2020/053062 | 2/7/2020 | WO |
