Claims
- 1. A MOS transistor device, comprising:
a semiconductor body of a first conductivity type; a gate structure overlying the semiconductor body and defining a channel therebelow in the semiconductor body, the gate structure defining lateral edges; source and drain extension regions of a second conductivity type formed in the semiconductor body on opposing sides of the channel; stress inducement regions formed in the semiconductor body on opposing sides of the channel and generally corresponding to the source and drain extension regions; sidewall spacers residing over the lateral edges of the gate structure; and source and drain regions of the second conductivity type formed in the semiconductor body on opposing sides of the channel, wherein a distance between the source and drain regions is dictated by a width of the gate structure and the sidewall spacers, and wherein the distance is greater than a distance between the stress inducement regions.
- 2. The MOS transistor device of claim 1, further comprising offset spacers formed on the lateral edges of the gate structure and disposed between the lateral edges of the gate structure and the sidewall spacers, respectively, wherein the distance between the stress inducement regions is dictated by a width of the gate structure and the offset spacers.
- 3. The MOS transistor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type, and wherein the stress inducement regions comprise carbon-doped silicon formed by etching recesses in the semiconductor body and forming carbon-doped silicon therein via in-situ doped selective epi deposition.
- 4. A method of forming a transistor, comprising:
forming a gate structure over a semiconductor body; forming recesses substantially aligned to the gate structure in the semiconductor body; epitaxially growing carbon-doped silicon in the recesses; forming sidewall spacers over lateral edges of the gate structure after growing the carbon-doped silicon in the recesses; and implanting source and drain regions in the semiconductor body after forming the sidewall spacers.
- 5. The method of claim 4, further comprising forming offset spacers on the lateral edges of the gate structure before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers.
- 6. The method of claim 5, wherein the recesses are offset from the lateral edges of the gate structure a distance of about 10 nm or more and about 50 nm or less.
- 7. The method of claim 5, further comprising implanting extension regions into carbon-doped silicon before forming the sidewall spacers.
- 8. The method of claim 4, wherein forming the gate structure comprises:
forming a gate oxide over the semiconductor body; and depositing and patterning a conductive layer to form a gate electrode over the gate oxide, thereby defining the gate structure.
- 9. The method of claim 4, wherein epitaxially growing the carbon-doped silicon comprises performing a selective epitaxial deposition of silicon in the presence of a carbon containing source gas, wherein the carbon dopes the epitaxially growing silicon in-situ.
- 10. The method of claim 4, wherein the carbon-doped silicon in the recesses contains about 0.3 atomic percent carbon or more and about 2 percent atomic carbon or less.
- 11. The method of claim 4, wherein the recesses have a depth of about 30 nm or more and about 70 nm or less.
- 12. The method of claim 4, further comprising:
forming offset spacers on the lateral edges of the gate structure before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers; performing an extension region implant after formation of the offset spacers and before forming the recesses; and performing a thermal process after the extension region implant and before forming the recesses, wherein the extension regions slightly diffuse laterally in response thereto such that edges thereof extend below the offset spacers toward the gate structure.
- 13. The method of claim 12, further comprising performing a thermal process after implanting the source and drain regions, wherein the source and drain regions diffuse laterally due to the thermal process, thereby connecting to the respective extension regions under the sidewall spacers.
- 14. The method of claim 4, further comprising forming a recess in a top portion of the gate structure concurrently with the forming of the recesses.
- 15. The method of claim 14, further comprising epitaxially growing carbon-doped silicon in the recess in the top portion of the gate structure concurrently with the formation of the carbon-doped silicon in the recesses associated with the semiconductor body.
- 16. A method of forming an NMOS and a PMOS transistor concurrently, comprising:
forming gate structure over a semiconductor body in an NMOS region and a PMOS region, respectively; forming recesses substantially aligned to the gate structures in the semiconductor body in both the NMOS and PMOS regions; epitaxially growing carbon-doped silicon in the recesses; forming sidewall spacers over lateral edges of the gate structures after growing the carbon-doped silicon in the recesses; and implanting n-type source and drain regions in the NMOS region and p-type source and drain regions in the PMOS region of the semiconductor body after forming the sidewall spacers.
- 17. The method of claim 16, further comprising forming offset spacers on the lateral edges of the gate structures before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers.
- 18. The method of claim 17, wherein the recesses are offset from the lateral edges of the gate structure a distance of about 10 nm or more and about 50 nm or less.
- 19. The method of claim 17, further comprising implanting n-type extension regions in the NMOS region and p-type extension regions in the PMOS region into carbon-doped silicon before forming the sidewall spacers.
- 20. The method of claim 16, wherein the carbon-doped silicon in the recesses contains about 0.3 atomic percent carbon or more and about 2 percent atomic carbon or less.
- 21. The method of claim 16, wherein the recesses have a depth of about 30 nm or more and about 70 nm or less.
- 22. The method of claim 16, further comprising:
forming offset spacers on the lateral edges of the gate structures before forming the recesses, wherein the recesses are aligned in the semiconductor body with respect to the offset spacers; performing an n-type extension region implant in the NMOS region and a p-type extension region implant in the PMOS region, respectively, after formation of the offset spacers and before forming the recesses; and performing a thermal process after the extension region implant and before forming the recesses, wherein the extension regions slightly diffuse laterally in response thereto such that edges thereof extend below the offset spacers toward the respective gate structures.
- 23. The method of claim 22, further comprising performing a thermal process after implanting the n-type source and drain regions in the NMOS region and the p-type source and drain regions in the PMOS region, respectively, wherein the n-type and p-type source and drain regions diffuse laterally due to the thermal process, thereby connecting to the respective extension regions under the sidewall spacers.
- 24. The method of claim 16, further comprising forming a recess in a top portion of the gate structures concurrently with the forming of the recesses.
- 25. The method of claim 24, further comprising epitaxially growing carbon-doped silicon in the recess in the top portion of the gate structures concurrently with the formation of the carbon-doped silicon in the recesses associated with the semiconductor body.
- 26. A method of forming a transistor, comprising:
forming a gate structure over a semiconductor body; forming recesses substantially aligned to the gate structure in the semiconductor body; epitaxially growing a doped silicon in the recesses, wherein the dopant comprises one of the IVa elements; forming sidewall spacers over lateral edges of the gate structure after growing the carbon-doped silicon in the recesses; and implanting source and drain regions in the semiconductor body after forming the sidewall spacers.
REFERENCE TO RELATED APPLICATION
[0001] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 60/482,573, which was filed Jun. 25, 2003, entitled CARBON DOPED Si IN A RECESS NEXT TO MDD TO CREATE STRAIN IN THE CHANNEL, the entirety of which is hereby incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60482573 |
Jun 2003 |
US |