TRANSMITTER VOLTAGE AND RECEIVER TIME MARGINING

Abstract

A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 illustrates a block diagram of two integrated circuit devices coupled by a communications link consistent with one or more embodiments of the present invention.

FIG. 2 illustrates a block diagram of a portion of a communications link receive path on an integrated circuit device consistent with one or more embodiments of the present invention.

FIG. 3 illustrates a block diagram of an exemplary clock phase recovery circuit consistent with one or more embodiments of the present invention.

FIG. 4 illustrates a block diagram of an exemplary portion of the clock phase recovery circuit of FIG. 3 consistent with one or more embodiments of the present invention.

FIG. 5 illustrates a block diagram of an exemplary phase shifting circuit of a clock phase recovery circuit of FIG. 3 consistent with one or more embodiments of the present invention.

FIG. 6 illustrates a block diagram of an exemplary control logic circuit of a clock phase recovery circuit of FIG. 3 consistent with one or more embodiments of the present invention.

FIG. 7 illustrates exemplary waveforms consistent with one or more embodiments of the present invention.

FIG. 8 illustrates exemplary information and control flows consistent with one or more embodiments of the present invention.

FIG. 9 illustrates a block diagram of an exemplary communications link transmit path on an integrated circuit device consistent with one or more embodiments of the present invention.

FIG. 10 illustrates a circuit diagram of an exemplary transmit equalization and voltage margining circuit of FIG. 9 consistent with one or more embodiments of the present invention.

FIG. 11 illustrates exemplary waveforms consistent with one or more embodiments of the present invention.

FIG. 12 illustrates exemplary information and control flows consistent with one or more embodiments of the present invention.

FIG. 13 illustrates exemplary information and control flows consistent with one or more embodiments of the present invention.

Claims

1. A method for determining margin associated with a receiver circuit of an integrated circuit comprising: periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal;incrementally varying a value of the parameter associated with the signal, the varying of the parameter being through a range of values of the parameter over the time period; anddetermining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

2. The method, as recited in claim 1, wherein the parameter is a phase alignment of a sample clock signal used by the receiver sampling circuit to sample the signal.

3. The method, as recited in claim 2, wherein the incrementally varying comprises: adding a phase modulation offset to the sample clock signal, the phase modulation offset having a frequency above a tracking bandwidth of a data phase tracking circuit of the receiver circuit.

4. The method, as recited in claim 1, wherein the integrated circuit is included in a reference system and further comprising: determining an operating value of the parameter in the reference system based at least in part on the margin value determined for the integrated circuit;setting, to the operating value, a corresponding parameter in another system,wherein the other system includes a second integrated circuit coupled to a third integrated circuit by a fixed communications path.

5. The method, as recited in claim 4, wherein the fixed communications path is at least one of a bus coupling the second and third integrated circuits within an embedded application, a bus on a printed circuit board coupling the second and third integrated circuits on a single printed circuit board, and a bus coupling the second and third integrated circuits on separate printed circuit boards.

6. The method, as recited in claim 1, wherein the parameter is a voltage swing of the signal, the voltage swing of the signal being varied over the range of values by a transmitter circuit on another integrated circuit coupled to the integrated circuit.

7. The method, as recited in claim 6, wherein the voltage swing is varied over a range including at least approximately a maximum voltage swing and approximately 25% of the maximum voltage swing.

8. The method, as recited in claim 1, wherein the parameter is a phase alignment of a sample clock signal used by the receiver sampling circuit to sample the signal, the phase alignment of the sample clock signal being varied over the range of values by the receiver circuit of the integrated circuit.

9. The method, as recited in claim 8, wherein the phase alignment of the sample clock signal is varied over a range including at least approximately +/−25% of a unit interval of the sample clock signal.

10. The method, as recited in claim 1, further comprising: generating a sample clock signal on the integrated circuit based at least in part on a phase difference between the signal and a received clock signal, wherein the signal and the received clock signal are received from the second integrated circuit on separate communications paths.

11. The method, as recited in claim 1, wherein the determining the margin value comprises: comparing samples of the signal to corresponding expected values of the samples of the signal;determining a bit-error rate associated with individual values of the parameter based, at least in part on the comparison; anddetermining the margin value based, at least in part, on at least one of the individual bit-error rates.

12. The method, as recited in claim 1, further comprising; estimating a system bit-error rate based, at least in part, on the margin value of the receiver circuit.

13. An integrated circuit product comprising a second integrated circuit configured based at least in part on the margin value determined by the method recited in claim 1.

14. An apparatus comprising: an integrated circuit comprising: a transmitter circuit configured to transmit a first signal over a first communications path;a receiver circuit configured to receive a second signal over a second communications path,wherein at least one of the transmitter circuit and the receiver circuit is configured to incrementally vary a phase alignment of a sample clock signal used by the receiver circuit to sample the second signal, the varying of the phase alignment being through a range of values of the phase alignment over a time period.

15. The apparatus, as recited in claim 14, wherein the receiver circuit comprises: an amplifier circuit configured to amplify the second signal; anda receiver sampling circuit,wherein the amplifier circuit generates an input to the receiver sampling circuit,wherein the receiver circuit is configured to generate the sample clock signal and a sampled data signal, the sampled data signal being based, at least in part, on the input of the receiver sampling circuit and the sample clock signal.

16. The apparatus, as recited in claim 14, wherein the receiver circuit further comprises: a control circuit configured to vary a value of a phase offset used to vary the phase alignment of the sample clock signal.

17. The apparatus, as recited in claim 16, wherein the receiver circuit further comprises: a delay-locked loop circuit responsive to a received clock signal to provide a plurality of phase clock signals having respective phases spaced equally across at least a predetermined fraction of the period of the received clock signal;a select circuit responsive to at least one phase select signal to select from the plurality of phase clock signals, a first phase clock signal having a first phase and a second phase clock signal having a second phase different from the first phase; anda phase interpolator circuit responsive to at least one interpolation control signal to generate an interpolated clock signal based on the first phase clock signal and the second phase clock signal,wherein the control circuit is responsive to at least an indicator of a phase difference between the received clock signal, the input of the receiver sampling circuit, and a target value of the phase offset to generate the at least one phase select signal and the at least one interpolation control signal.

18. The apparatus, as recited in claim 16, wherein the receiver circuit further comprising: a phase detector circuit responsive to the input of the receiver sampling circuit and the sample clock signal to generate an indicator of a phase difference between the received clock signal and the input of the receiver sampling circuit.

19. The apparatus, as recited in claim 14, further comprising: the first and second communications paths;a third communications path coupled to the receiver circuit of the integrated circuit;a second integrated circuit coupled to the first integrated circuit to by the first, second, and third communications paths;wherein the receiver circuit is configured to receive, from the second integrated circuit, a received clock signal on the third communications path, the receiver circuit being coupled to generate a sample clock signal and a sampled data signal, the sampled data signal being the input of the receiver sampling circuit sampled by the sample clock signal,wherein the sample clock signal is determined at least in part according to a phase difference between the received clock signal and the input of the receiver sampling circuit.

20. The apparatus, as recited in claim 15, further comprising: the first and second communications paths;a second integrated circuit; anda printed circuit board,wherein the integrated circuit and the second integrated circuit are attached to the printed circuit board and coupled to each other by at least the first and second communications paths.

21. The apparatus, as recited in claim 15, further comprising: the first and second communications paths;an integrated circuit substrate; anda second integrated circuit,wherein the integrated circuit and the second integrated circuit are formed on the integrated circuit substrate and coupled to each other by at last the first and second communications paths.

22. The apparatus, as recited in claim 14, wherein the integrated circuit further comprises: a storage circuit coupled to the receiver circuit to receive data based at least in part on samples of the input of the receiver sampling circuit; andan interface circuit coupled to the storage circuit and configured to provide external to the integrated circuit, information based at least in part on the samples of the input of the receiver sampling circuit over the time period.

23. An apparatus comprising: a receiver sampling means on an integrated circuit coupled to a second integrated circuit by the communications path; andmeans for determining a margin value associated with the receiver sampling means, wherein the means for determining comprises: means for incrementally varying a value of a parameter associated with a signal sampled by the receiver sampling means, the varying of the parameter being through a range of values over a time period.

24. The apparatus, as recited in claim 23, wherein the parameter is voltage swing of the signal.

25. The apparatus, as recited in claim 23, wherein the parameter is phase alignment of a clock signal used by the receiver sampling means to sample the signal.

26. The apparatus, as recited in claim 25, wherein the means for incrementally varying the parameter inserts a phase modulating offset to the clock signal.