Patent Application
20170162557
1. Field of the Disclosure
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to the formation of a charge pump device, more particularly, the formation of a charge pump device for back-biasing an FDSOI transistor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, metal-oxide-semiconductor (MOS) technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
Nowadays, as an alternative to bulk devices, FETs are also built on silicon-on-insulator (SOI), in particular Fully Depleted silicon-on-insulator (FDSOI), substrates. The channels of the FETs are formed in thin semiconductor layers, typically including or made of silicon material, wherein the semiconductor layers are formed on insulating layers, buried oxide (BOX) layers that are formed on semiconductor bulk substrates. One severe problem caused by the aggressive downscaling of the semiconductor devices must be seen in the occurrence of leakage currents. Since leakage currents depend on the threshold voltages of the FETs, substrate biasing (back biasing) can reduce leakage power. With this advanced technique, the substrate or the appropriate well is biased to raise the transistor thresholds, thereby reducing leakage currents. In P-channel MOS (PMOS) devices, the body of the transistor is biased to a voltage higher than the positive supply voltage VDD. In N-channel MOS (NMOS) devices, the body of the transistor is biased to a voltage lower than the negative supply voltage VSS. Similar to the grid of standard cells, a grid of tap cells is commonly used in the integrated circuit design to provide for the body bias of the transistors. The tap cells have to create electrical connections between a network providing biasing voltages P+/N+ regions residing under the BOX layers of SOI, particularly FDSOI, substrates. Each standard cell row must have at least one (body- or well-) tap cell. However, usually designers have a rule of one tap cell placed in a standard cell row per every certain distance at regular intervals.
In order to bias the back gates of the NMOS and PMOS transistor devices, voltages need to be created by charge pumps which are custom blocks that output VSS and VOUT.
The circuit element shown in
In the art, charge pumps, for example, realized based on the configuration illustrated in
In view of the situation described above, the present disclosure provides a technique of providing charge pump devices comprising capacitors with a lower demand for a spatial area covered in an SOI device as compared to the art.
The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally the subject matter disclosed herein relates to the formation of semiconductor devices comprising transistor devices, and, more particularly, integrated circuits with (MOS)FETs including means for back biasing of the transistor devices.
A semiconductor device is provided including a Fully Depleted Silicon-on-Insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate. The charge pump device comprises a transistor device formed in and on the FDSOI substrate and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. By forming the charge pump device by the connected transistor device and trench capacitor, a compact design for the charge pump device may be achieved that needs less space than the charge pumps known in the art.
Further, a semiconductor device (particularly a charge pump device) is provided with a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode. The first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region. The first outer capacitor electrode and the second outer capacitor electrode may be connected to the semiconductor bulk substrate.
Furthermore, a semiconductor device (particularly a charge pump device) is provided with a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, a first switching device, and a second switching device. The first inner capacitor electrode and the second outer capacitor electrode are connectable to each other by the first switching device and the first outer capacitor electrode and the second inner capacitor electrode are connectable to each other by the second switching device. The first and the second trench capacitor are electrically cross-coupled to each other via the first and second switching devices. Electrical connection between the first inner capacitor electrode and the second outer capacitor electrode is established by closing the first switching device and electrical connection between the first outer capacitor electrode and the second inner capacitor electrode is established by closing the second switching device. The first switching device may comprise or consist of a transistor device and the second trench capacitor may comprise or consist of another transistor device wherein, particularly, the transistor devices may share a common gate electrode (poly line).
Furthermore, a method of manufacturing a semiconductor device, in particular, a charge pump device, is provided including the steps of providing a semiconductor substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a first transistor device and a second transistor device in and over the semiconductor substrate, and forming a first and a second trench capacitor at least partially in the semiconductor substrate. Forming the first transistor device includes forming a first raised source/drain region on the semiconductor layer and forming the second transistor device comprises forming a second source/drain region on the semiconductor layer, and forming the first trench capacitor includes forming a first inner capacitor electrode in contact with the first source/drain region and a first outer capacitor electrode at least partially in the semiconductor substrate and forming the second trench capacitor includes forming a second inner capacitor electrode in contact with the second source/drain region and a second outer capacitor electrode at least partially in the semiconductor substrate.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The following embodiments are described in sufficient detail to enable those skilled in the art to make use of the disclosure. It is to be understood that other embodiments would be evident, based on the present disclosure, and that system, structure, process or mechanical changes may be made without departing from the scope of the present disclosure. In the following description, numeral-specific details are given to provide a thorough understanding of the disclosure. However, it would be apparent that the embodiments of the disclosure may be practiced without the specific details. In order to avoid obscuring the present disclosure, some well-known circuits, system configurations, structure configurations and process steps are not disclosed in detail.
The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present methods are applicable to a variety of technologies, for example, NMOS, PMOS, CMOS, etc., and is readily applicable to a variety of devices, including, but not limited to, logic devices, SRAM devices, etc., particularly in the context of FDSOI technologies used for manufacturing integrated circuits (ICs). Generally, manufacturing techniques and semiconductor devices in which back (substrate)-biased N-channel transistors and/or P-channel transistors may be formed are described herein. The manufacturing techniques may be integrated in CMOS manufacturing processes. The techniques and technologies described herein may be utilized to fabricate MOS integrated circuit devices, including NMOS integrated circuit devices, PMOS integrated circuit devices, and CMOS integrated circuit devices. In particular, the process steps described herein are utilized in conjunction with any semiconductor device fabrication process that forms gate structures for integrated circuits, including both planar and non-planar integrated circuits. Although the term “MOS” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term is used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor bulk substrate.
The present disclosure, generally, provides charge pump devices comprising trench capacitors that are particularly suitable for dynamic back-biasing of transistor devices, for example, dynamic back-biasing of FDSOI (MOS)FETs.
An example for a semiconductor device 100 realizing the configuration shown in
Moreover, the semiconductor device 100 comprises a first capacitor 25 and a second capacitor 26. The inner electrode 27 of the first capacitor 25 is electrically connected to the (raised) source or drain region 28 of the first switching transistor 21 and the outer electrode 29 of the second capacitor 26 is electrically connected to the wafer bulk 30. Similarly, the outer electrode 31 of the first capacitor 25 is electrically connected to the wafer bulk 30 and the inner electrode 32 of the second capacitor 26 is electrically connected to the (raised) source or drain region 33 of the second switching transistor 22. The entire structure is isolated from other devices by an isolation region 40, for example, including shallow trench isolations (STI) formed in the wafer. In particular, the semiconductor device 100 may be an FDSOI device with a fully depleted semiconductor layer 35 formed on a buried oxide layer 34. The buried oxide layer 34 may be made of the same material, for example, silicon dioxide, as the isolation region 40. The inner electrodes 27, 32 and outer electrodes 29, 31 of the first and second capacitors 25 and 26 are respectively isolated from each other by capacitor dielectric layers 36 and 37.
Furthermore, electrical contacts 50 are formed between the wafer bulk 30 and the source/drain regions 28, 33 of the first switching transistor 21 and the second switching transistor 22. Details of the contacts are described below with reference to
According to the example shown in
A process flow for manufacturing a semiconductor device comprising a charge pump in accordance with the present disclosure is illustrated in
A gate electrode 103 of a FET is formed over the semiconductor layer 102. A gate dielectric (not shown) may be formed between the gate electrode 103 and the semiconductor layer 102. The gate electrode layer 103 may comprise a metal gate. The material of the metal gate may depend on whether the transistor device to be formed is a P-channel transistor or an N-channel transistor. In embodiments wherein the transistor device is an N-channel transistor, the metal may include La, LaN or TiN. In embodiments wherein the transistor device is a P-channel transistor, the metal may include Al, AlN or TiN. The metal gate may include a work function adjusting material, for example, TiN. In particular, the metal gate may comprise a work function adjusting material that comprises an appropriate transition metal nitride, for example, those from groups 4-6 in the periodic table, including, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN) and the like, with a thickness of about 1-60 nm. Moreover, the effective work function of the metal gate may be adjusted by added impurities, for example, Al, C or F. Moreover, the gate electrode layer 103 may comprise a polysilicon gate at the top of the metal gate. Sidewall spacers (not shown), for example, comprising silicon dioxide and/or silicon nitride, may be formed at sidewalls of the gate electrode 103.
Raised source/drain regions 104 are formed on the semiconductor layer 102. Formation of the raised source/drain regions 104 may include epitaxially growing a semiconductor material on the semiconductor layer 102 and appropriate doping of the same after or during the epitaxial growth. It should be noted that the epitaxial growth of the material of the raised source/drain regions 104 on the surface of the semiconductor bulk substrate 101 in the area where the semiconductor layer 102 is removed (see right-hand side of
A silicide layer 105, for example, comprised of NiSi, may be formed on the raised source/drain regions 104. For this purpose, a metal layer may be deposited on the raised source/drain regions 104 and an anneal process may be performed for initiating a chemical reaction between the metal of the metal layer and the semiconductor material of the raised source/drain regions 104. The silicidation process is known to improve electrical contacts of the raised source/drain regions 104. In the shown example, the silicide layer 105 is also formed on a part of the semiconductor bulk substrate 101. In principle, it could also be formed on top of the gate electrode 103.
Furthermore, the semiconductor device 100 comprises an isolation structure 106 comprising shallow trench isolations (STI) 107. A buried oxide layer 108 also contributes to the isolation structure 106 that may be formed of the same material, for example, silicon dioxide, in all shown regions. The buried oxide layer 108 may include a dielectric material, such as silicon dioxide, and may be an ultra-thin buried oxide (UT-BOX) having a thickness in a range from about 10-20 nm. The semiconductor bulk substrate 101, the buried oxide layer 108 and the semiconductor layer 102 may constitute an FDSOI substrate.
For example, an (FD)SOI wafer comprising the semiconductor bulk substrate 101, the buried oxide layer 108 and the semiconductor layer 102 may be provided, the gate electrode 103 may be formed over the (FD)SOI wafer, the raised source/drain regions 104 and the silicide layer 105 and the STIs 107 are formed by etching trenches into the semiconductor layer 102, the BOX layer 108 and the semiconductor bulk substrate 101 and filling the same with a dielectric material and, subsequently, an isolation layer is deposited over the entire configuration and polished such that the isolation structure 106 results.
As shown in
After removal of the excessive material of the outer capacitor electrode layer 130, the dummy material 140 is removed. After removal of the dummy material 140, a capacitor dielectric layer (node) 150 is formed on the outer capacitor electrode layer 130 and an inner capacitor electrode layer 160, for example, a metal layer, is formed on the capacitor dielectric layer 150 and, after recess to the upper surface of the buried oxide layer 108 and removal of excessive material of the capacitor dielectric layer 150, the semiconductor device 100 in the manufacturing stage shown in
After removal of the excessive material of the capacitor dielectric layer 150, additional material of the inner capacitor electrode 160 (or a different metal comprising material) is deposited to extend the inner capacitor electrode 160 such that the same gets into contact with the raised source/drain region 104 and the silicide layer 105 formed on the source/drain region 104, as shown in
As described above with reference to
In the example shown in
Moreover, a regular contact 286 is formed in contact with the silicide layer 240, a part of which was formed on a side surface of the buried oxide layer 220 and the semiconductor layer 225. Electrical contact between the silicided raised source/drain region 230 and the silicided surface of the semiconductor bulk substrate 210 is achieved by the contact 286 via the silicide layer 240 and the plasma enhanced nitride layer 250. The same holds for the example shown in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
