The present application is based on, and claims priority from, Chinese application number 201610587297.5, filed on Jul. 25, 2016, the disclosure of which is hereby incorporated by reference herein in its entirety.
This invention generally, relates to the field of semiconductor technology, and more particularly to trench edge termination structures for power semiconductor devices.
The blocking voltage of a power device depends mainly on the reverse bias breakdown voltage of particular PN junction in the devices. Influenced by the non-ideal factors at the termination of PN junction, the reverse breakdown voltage of an actual PN junction is much lower than the parallel plane junction. Junction termination is a specifically designed structure to reduce the local electric field intensity improve the reliability and enhance the breakdown voltage of an actual PN junction close to the parallel plane junction. The terminal structure around the active region is a subsidiary structure of PN junction, which enables the active region to withstand extra high voltage.
At present, the terminal structures for power semiconductor devices fabricated by the planar process are usually some extended structures arranged at the edge of the main junction. These extended structures play the main role in broadening the junction depletion region outwards, thereby reducing the electric field intensity and increasing the blocking voltage. Typical extended structures include field plate (FP), field limiting ring (FLR), junction termination extension (JTE) and variable lateral doping (VLD). To achieve high blocking voltage, the extended structures must be long enough to extend the depletion region. Therefore, in high voltage devices, the large extended terminal structures result in the rise of the cost.
Another type of terminal technology is the bevel edge termination. Firstly the edge of the silicon wafer is removed with a precise angle by a physical method. Then the damage during the silicon-removing process is eliminated by chemical etching. Finally, the surface is covered by the passivation layer. The surface electric field distribution and the surface breakdown voltage are improved by the truncated morphology and the surface passivation. Bevel edge termination technology is divided into the positive grinding angle technology and the negative grinding angle technology. Neither of them is applicable to the square chip, and their occupied areas are very large, especially the negative grinding angle technology.
Trench type terminal technology takes advantage of planar process and bevel process. Deep trenches around the active region are etched and filled with insulating dielectric. The PN junction is cut off by the trench, and the surface electric field distribution and the breakdown voltage are improved by the truncated morphology. The advantage of this kind of trench termination is that the occupied area is small, while the disadvantages are that the deep trench process is more complex, and the breakdown is affected by the trench wall morphology, trench filling material, and other factors. If the sectional shape of the trench is rectangular, as shown in
The present invention provides an edge termination structure with a trench for power semiconductor devices to achieve smaller area and higher blocking voltage and to reduce the technical difficulty of trench etching and dielectric filling at the same time.
According to an aspect of the invention, an edge termination is provided. The edge termination includes: a P-type heavily doped substrate 2 (i.e., a heavily doped substrate of a conductivity type P), a P-type lightly doped drift region 3 (i.e., a lightly doped drift region of the same conductivity type P) located on the top surface of the P-type heavily doped substrate 2, a metal drain electrode 1 located on the lower surface of the P-type heavily doped substrate 2, and a field oxide S on the upper surface of the P-type lightly doped drift region 3. The P-type lightly doped drift region 3 includes a trench 4 and a P-type heavily doped region 9 (i.e., a heavily doped region of a conductivity type P). The P-type heavily doped region 9 is located in the top portion of the P-type lightly doped drift region 3 and on the side away from the device active region, and the upper, surface of the P-type heavily doped region 9 contacts the lower surface of the field oxide 8. The trench 4 is filled with insulating material and its upper surface contacts the lower surface of the field oxide 8. In trench 4, there is a polysilicon floating island 5 that stores positive charge. The sidewall of the trench 4 that is close to the active region contacts the N-type junction 6 in the active region, and the upper surface of the polysilicon floating island 5 should be lower than the lower surface of the N-type junction 6 in the active region. In the cross-sectional view of the device, the trench 4 has an inverted trapezium shape, and the value of the angle between the hypotenuse of the inverted trapezium and the horizontal plane ranges from 60 to 90 degrees.
According to another aspect of the invention, an edge termination is provided. The edge termination includes: an N-type heavily doped substrate 2 (i.e., a heavily doped substrate of a conductivity type N) an N-type lightly doped drift region 3 (i.e., a lightly doped of the same conductivity type N) located on the top surface of the N-type heavily doped substrate 2, a metal drain electrode 1 located on the lower surface of the N-type heavily doped substrate 2, and a field oxide 8 located on the upper surface of N-type lightly doped drift region 3. The N-type lightly doped drift region 3 includes a trench 4 and a N-type heavily doped region 9 (i.e., a heavily doped region of a conductivity type N). The N-type heavily doped region 9 is located in the top portion of the N-type lightly doped drift region 3 and on the side away from the device active region, and the upper surface of the N-type heavily doped region 9 contacts the lower surface of the field oxide 8. The trench 4 is filled with an insulating material whose upper surface contacts the lower surface of the field oxide 8. In the trench 4, there is a polysilicon floating island 5 that stores negative charge. The sidewall of the trench 4 that is close to the active region contacts the P-type junction 6 in the active region, and the upper surface of the polysilicon floating island 5 should be lower than the lower surface of the P-type junction 6 in the active region. In the cross-sectional view of the device, the trench 4 has an inverted trapezium shape, and the value of the angle between the hypotenuse of the inverted trapezium and the horizontal plane ranges from 60 to 90 degrees.
Some beneficial effects of the present invention are as follow. On one hand, compared with fabricating a trapezoidal or rectangle trench, fabricating a trench with a sectional shape of inverted trapezium by deep trench etching and dielectric filling is less difficult. On the other hand, due to the Coulomb interaction between the ionized impurity in the drift region and the fixed charges introduced at a particular location in the trench, the depletion region of the terminal PN junction can be fully extended such that the concentration of electric field, is relieved. Therefore, the edge termination provided in this invention can exhibit a high breakdown voltage which approaches the high breakdown voltage of the parallel plane junction with a smaller area.
In the following detailed description, the features of the various exemplary embodiments may be understood in combination with the drawings.
The mechanism of the present edge termination structure provided by embodiment 1 will be explained as follows.
Compared with the planar termination structure, the trench termination structure can greatly reduce the area of the termination while increasing the withstand voltage of the device. However, in an edge structure with a conventional trench, as shown in
It is much easier to etch a groove with a negative angle, but the trench with a negative angle will take away more charges from the heavily doped N-type region than that from the lightly doped P-type region. As a result, the depletion region will extend in the N-type region while shrinking in the P-type region, as shown in
It should be noted that the upper surface of the floating island 5 should be aligned with or lower than the bottom of the N-type region 6. Otherwise, the charges in the floating island will not be efficient to improve the electric field at the terminal junction.
In this embodiment, the angle θ between the sidewall of the trench and the horizontal plane need not be as small as the angle in a negative bevel junction. The angle θ usually ranges from 60 to 90 degrees. In this way, not only the area of the trench is reduced, but also the difficulties of trench etching and dielectric filling are decreased. Therefore, the trench termination structure provided by the present invention can achieve the breakdown voltage of an ideal parallel plane junction while reducing the termination area and technical difficulty.
In embodiment 1, the structure of the present invention can be produced by the following steps.
As shown in
Firstly, an N-type semiconductor material doped region 6 is formed phosphorus ion implantation after lithography of the active region. A thermal propulsion process is used to make the N-type doped region 6 reach a certain junction depth, and the impurities is activated under a high temperature, as shown in
Then, a P-type heavily doped region 9 is formed by lithography in the terminal region and boron ion implantation, as shown in
Next, a hard mask layer 10 (such as silicon nitride) is deposited on the surface of the silicon wafer as a barrier layer for subsequent etching. Then the hard mask layer 10 is etched after the lithography and then the deep trench is etched by the shelter of the hard mask layer 10. The etching process may be ion beam etching or plasma etching. After that, an inverted trapezoidal trench 4 is etched in the terminal region, as shown in
Subsequently, the trench 4 is filled with an insulator (such as silicon dioxide), then the insulator is etched back to an appropriate thickness, as shown in
After that, an oxide layer of a certain thickness is grown on the sidewall of the trench 4, as shown in
After the growth of the oxide layer, the trench 4 is filled with polysilicon 5, as depicted in
Then the polysilicon 5 is etched back to ensure that the upper surface of the polysilicon 5 is lower than the bottom of the N-type doped region 6. Then cesium ions with a positive charge are implanted into the polysilicon 5 by ion implantation technique, as shown in
At last, the insulator is deposited on the upper of the polysilicon 5 and the surface of the device, as shown in
In addition, in both embodiment 1 and embodiment 2. some other semiconductor materials such as silicon, carbide, gallium arsenide, indium phosphide and germanium silicon can be used to replace silicon in manufacturing.
Number | Date | Country | Kind |
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201610587297.5 | Jul 2016 | CN | national |