This application is based on, and claims priority to, Japanese Patent Application No. 2011-228961, filed on Oct. 18, 2011, the contents of which are incorporated herein by reference.
A. Field of the Invention
The present invention relates to a capacitance element of a polysilicon (P)-insulator (I)-polysilicon (P) type having a trench structure (hereinafter referred to as a trench-type PIP capacitor) and a power integrated circuit device (hereinafter also referred to as a power IC) having the trench-type PIP capacitor. The invention relates also to a method of manufacturing the power IC.
B. Description of the Related Art
In order to achieve a low ON resistance semiconductor element with a small area, a trench gate type semiconductor element with a gate region formed on a trench has been proposed. To improve reliability and enhance breakdown voltage of this trench gate type semiconductor element at a low cost, a power semiconductor device called a trench gate type power IC has been developed comprising semiconductor elements for controlling and protecting the trench gate type semiconductor elements formed on one and the same semiconductor substrate. The trench gate type power IC is a power IC having a vertical power MOSFET with a trench gate structure. The vertical power MOSFET can be replaced by a vertical insulated gate bipolar transistor (IGBT) in some cases.
The trench gate type power IC comprises an output stage semiconductor element of a vertical power MOSFET 21 with a trench gate structure and controlling semiconductor elements of a low voltage lateral MOSFET 22a with a planar gate structure and a MOS type capacitance element of a MOS capacitor 22b.
Vertical power MOSFET 21 with a trench gate structure, lateral MOSFET 22a with a planar gate structure, and MOS capacitor 22b are formed on a single substrate that is a lamination of n+ type semiconductor layer 2 and n− type epitaxial layer 3. An ordinary power IC has electric circuits for controlling the output stage semiconductor element. The electric circuits include a delay circuit, a filter circuit, and an oscillator circuit. Multiple MOS capacitors 22b are used for constructing those electric circuits. The symbols 12d and 12e in
The variation of the capacitance value corresponding to the applied voltage between electrodes is smaller in planar-type PIP capacitor 22c than in MOS capacitor 22b. The electrodes to which a voltage is applied in planar-type PIP capacitor 22c are made of highly doped polysilicon 14 and 6c, and the voltage is held with capacitive insulation layer 15 sandwiched with polysilicon 14 and 6c. In this structure, a space charge region is formed in capacitive insulation layer 15 and scarcely formed in the electrodes of polysilicon 14 and 6c. As a result, the space charge layer width does not depend on the applied voltage, although it does depend on the thickness of capacitive insulation layer 15. Therefore, the capacitance value of planar-type PIP capacitor 22c varies little with the applied voltage.
Electrodes of MOS capacitor 22b shown in
In the case of the lower electrode of n-type semiconductor layer 16, when the voltage applied on the upper electrode is low with respect to n-type semiconductor layer 16, the width of the depletion layer expands, thereby decreasing capacitance value. Therefore, circuit design, for example, design of capacitance value of MOS capacitor 22b, needs to take this lowered capacitance value into consideration.
Planar-type PIP capacitor 22c exhibiting a small voltage dependence is applied to circuits that need a large capacitance value and circuits that require a capacitance value with high precision and little variation. Planar-type PIP capacitor 22c, being electrically insulated from the semiconductor substrate with thick oxide film 11a (a LOCOS), can favorably be used with less restriction to the voltage that is applied to the upper and lower electrodes as compared with MOS capacitor 2b in
In the high-side-type power IC 101, the gate voltage of output stage semiconductor element 102 is set to be higher than the drain voltage, which is the voltage at power supply terminal 103, in order to achieve sufficient current-carrying capability. Accordingly, the power supply voltage of driving circuit 112 to generate the gate voltage needs to be elevated over the voltage of power supply terminal 103 of control circuit 107. To achieve such a condition, driving circuit 112 often uses a charge pumping circuit.
Power IC 101 is desired to install a larger scale of control circuit than traditional ones to control the output stage semiconductor element with higher performance. In order to meet the requirement, efforts are in progress to make the control circuit 107 of power IC 101 finer and more precise, and to attain the overall circuit down-sizing. Recently, demand for cost-reduction and further down-sizing is significantly rising.
The following are documents disclosing power integrated circuit devices (power ICs).
Japanese Unexamined Patent Application Publication No. H06-151728 discloses a power IC in which a semiconductor substrate comprises an n+-type base body, an n−-type epitaxial layer formed thereon, and a p-type epitaxial layer formed on the n−-type epitaxial layer. The power IC has a power MOSFET that carries electric current from a first principal surface to a second principal surface of the semiconductor substrate, and a control element formed on the first principal surface side of the semiconductor substrate. The power MOSFET and the control element are isolated with a first trench.
A channel region of the MOSFET is formed on the side wall of a second trench in the p-type epitaxial layer. According to the document, this construction facilitates trench isolation between the power MOSFET for carrying an electric current from the first principal surface to the second principal surface of the semiconductor substrate and the control element formed on the first principal surface side of the semiconductor substrate.
Japanese Unexamined Patent Application Publication No. 2000-022140 discloses a semiconductor device installing a lateral power MOSFET provided with a trench disposed at a place that does not interfere with the operation current flow between a drain region formed in the active substrate and a potential lead-out region to be connected to the drain region. A gate electrode is embedded in the trench.
The trench and the gate electrode are disposed at both sides of a source region. The potential lead-out regions are disposed at both sides of another region. The trench of the lateral power MOSFET and the trench in the element-isolating region are formed with the same structure and in the same manufacturing step. The document asserts that the construction allows manufacturing a semiconductor device having an element-isolating region using a trench and a transistor using a trench with a small number of steps.
Japanese Unexamined Patent Application Publication No. 2003-264289 discloses a semiconductor device in which polycrystalline silicon gate layers are formed in and out of trenches formed on the principal surface of a semiconductor layer of a semiconductor substrate. The polycrystalline silicon gate layers are formed through a gate insulating film and connected to a gate electrode. A polycrystalline silicon diode is formed on the principal surface of the semiconductor layer through an insulating film. The film thickness of the polycrystalline silicone layer of the polycrystalline diode is thinner than the film thickness of the polycrystalline silicon layer of the polysilicon gate layer. According to the document this configuration improves performance of a semiconductor device even having a construction with a trench-type insulated gate semiconductor element and a polycrystalline silicon diode formed on the same chip.
Japanese Unexamined Patent Application Publication No. H08-102539 discloses a power integrated circuit including a power MOSFET and a control circuit on the same chip to which an npn transistor is added. The npn transistor is combined between a p well containing components of the power integrated circuit and the n-type substrate, and turns ON in response to the forward bias of the body diode of the power MOSFET.
In this power IC, a depletion mode controlled MOSFET transistor is combined to the gate of the power MOSFET through a fault-latch circuit, and connected to a capacitor in series. The node between the gate of the power MOSFET and the capacitor is isolated from the n-type substrate when the npn transistor turns ON and the power MOSFET turns OFF. According to the document this technique provides a power MOSFET exhibiting high reliability against overcurrent and overheating.
Japanese Unexamined Patent Application Publication No. 2009-260271 discloses a semiconductor device and a DC to DC converter using the semiconductor device. The semiconductor device comprises a trench formed in a MOSFET region and a trench gate electrode embedded in the trench. Another trench is formed in a capacitor region and a trench source electrode is embedded in the trench. The trench source electrode has the shape of a stripe, a part of which is connected to the source electrode. According to the document this construction suppresses surge of the source-drain voltage at the time of turning OFF.
Japanese Unexamined Patent Application Publication No. 2003-282720 discloses a semiconductor device having a capacitor that comprises a first conductive layer, a second conductive layer formed above the first conductive layer, and a capacitive insulation layer formed between the first and the second conductive layers. The first conductive layer and the second conductive layer each include a metal layer. The first conductive layer is provided with a first connecting part. A first contact is formed above the first connecting part. The second conductive layer is provided with a second connecting part. A second contact is formed above the second connecting part. The second contact is formed in a region excepting the region above the first conductive layer. The first and second conductive layers are formed of polysilicon to construct a planar-type PIP capacitor. This construction provides, according to the assertion of the document, a capacitive insulation layer exhibiting a stable film quality.
In order to achieve cost reduction and down-sizing in the power IC including a multiple of planar-type PIP capacitor 22c as shown in
However, in the fine structure of planar-type PIP capacitor 22c, having a laminated structure with polysilicon electrodes 6c and 14 sandwiching capacitive insulation layer 15, step 31a is generated between end part 31 of planar-type PIP capacitor 22c and the surroundings as shown in
If step 31a is large, metal layer 12e, which is a metallic wiring connecting circuit components over step 31a, may break. If metal layer 12e is made thicker to avoid the breakage, micromachining of metal layer 12e becomes difficult.
Step 31a of planar-type PIP capacitor 22c has a thickness dimension of the sum of the thicknesses of polysilicon 6c of the lower electrode, capacitive insulation layer 15, and polysilicon 14 of the upper electrode. Thus, step 31a is large and presents an obstacle to micromachining.
In order to decrease step 31a at end part 31 of planar-type PIP capacitor 22c, various means can be taken. For example, step 31a can be made insignificant by increasing the thickness of interlayer dielectric film 13b laminated on planar-type PIP capacitor 22c or interlayer dielectric film 13b with an increased thickness can be flattened by means of a chemical mechanical polishing method (a CMP method). These methods, however, increase both manufacturing lead time and production cost.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
The present invention solves the above-described problems, and provides a PIP capacitor having a small step at the capacitor end without increasing manufacturing cost, and a power integrated circuit device using the PIP capacitor. The invention also provides a method of manufacturing the power integrated circuit device.
A trench-type PIP capacitor according to the invention comprises a trench that is formed from a surface of a semiconductor layer toward an inner part of the semiconductor layer. An isolating insulation layer is formed on an inner wall of the trench and electrically isolates a first polysilicon from the semiconductor layer. The first polysilicon fills the trench through the isolating insulation layer and becomes a lower electrode. A capacitive insulation layer is formed on the first polysilicon and becomes a capacitance element of the capacitor. A second polysilicon that is formed on the capacitive insulation layer becomes an upper electrode. Preferably, the height of the surface of the first polysilicon is substantially equal to the height of the surface of the semiconductor layer.
A power integrated circuit device comprises the trench-type PIP capacitor defined above, an output stage element that passes or interrupts main current, and a control circuit for controlling the output stage element, the latter two components being formed on one and the same semiconductor layer as that on which the trench-type PIP capacitor is formed.
In the power integrated circuit device according to the invention, a well region of a conductivity type different from that of the semiconductor layer preferably is formed selectively in the surface region of the semiconductor layer, and the trench-type PIP capacitor is formed in the well region. Also it is preferable that a well region of a conductivity type different from that of the semiconductor layer is formed selectively in the surface region of the semiconductor layer, and the trench-type PIP capacitor is formed passing through the well region. Preferably the well region is a diffusion layer, and the semiconductor layer is an epitaxial layer formed on a semiconductor base material that has an impurity concentration higher than that of the semiconductor layer.
In a preferred embodiment the control circuit of the integrated circuit device includes a charge pumping circuit that uses the trench-type PIP capacitor for a capacitor in the charge pumping circuit. The output stage element preferably is a vertical power MOS semiconductor element with a trench gate structure or a planar gate structure. Preferably the height of the surface of the second polysilicon is substantially equal to the height of the surface of the semiconductor layer.
In a method of manufacturing a power integrated circuit device according to the invention, the trench to be filled with the first polysilicon is formed simultaneously with a trench to deposit a gate of the vertical power MOS semiconductor element with the trench gate structure. Preferably the capacitive insulation layer is a silicon oxide film formed by a chemical vapor deposition (CVD) method.
A trench-type PIP capacitor according to the invention comprises an insulation layer formed on the inner wall of a trench and a lower electrode of polysilicon embedded in the trench through the insulation layer. This construction decreases the step formed at an end part of the capacitor. As a result, the thickness of the metal layer for wiring does not need to be increased, and therefore the metal layer can have a fine structure.
When the surface height of the lower electrode of polysilicon is made substantially equal to the surface height of the semiconductor substrate according to the invention, the step at the end part of the capacitor is decreased without increasing the thickness of the interlayer dielectric film disposed on the upper electrode of polysilicon and without performing a flattening treatment by means of the CMP method. Therefore, increase of manufacturing cost is avoided. Thus, use of the trench-type PIP capacitor of the invention allows a power integrated circuit device (a power IC) to have a fine structure without increase in manufacturing cost.
When an insulation layer that is a capacitance element is formed with a silicon dioxide film by means of a CVD method according to the invention, this process facilitates integration with other general IC-manufacturing processes. This process does not add a thermal history, which might vary characteristics of semiconductor elements composing the control circuit.
The foregoing advantages and features of the invention will become apparent upon reference to the following detailed description and the accompanying drawings, of which:
Some preferred embodiments of the invention will be described in the following. In the description below, a first conductivity type is the n type and a second conductivity type is the p type, although the conductivity type can be reversed. A trench used in a trench-type PIP capacitor of the invention is formed in order to decrease the step at the end part of the capacitor. A trench in the invention does not use an insulation layer on the inner wall of the trench for obtaining a large capacitance element like a trench in known trench type MOS gate. “A trench-type PIP capacitor” referred to in this specification is a polysilicon-insulator-polysilicon (PIP) capacitor that comprises a lower electrode of polysilicon embedded in (or filling) a trench, an insulation layer formed on the lower electrode, and an upper electrode of a conductive film of polysilicon formed on the insulation layer to form a sandwich structure. Similar parts to the conventional ones are given the same symbols in the following description and the referenced drawings.
Trench-type PIP capacitor 50 has a characteristic structure as described below. Trench 52 is formed in semiconductor substrate 51. Isolating insulation layer 53 is formed on the inner wall of trench 52 to isolate electrically first polysilicon 54 from semiconductor substrate 51. First polysilicon 54 is embedded in the trench through isolating insulation layer 53 to form a lower electrode. Capacitive insulation layer 55 is formed as a capacitance element on first polysilicon 54. An upper electrode of second polysilicon 56 is formed on capacitive insulation layer 55. Thus, trench-type PIP capacitor 50 is constructed. First polysilicon 54 and second polysilicon 56 are polycrystalline silicon layers.
First polysilicon 54 of the lower electrode extends along the trench 52 and leads out along the end part of the side wall of the trench to the surface as shown in
The height H2 of the surface of first polysilicon 54 is substantially equal to the height H1 of the surface of semiconductor substrate 41. Step 60 at the end of the trench-type PIP capacitor 50 in this configuration is equal to the sum T4 of the thickness T3 of capacitive insulation layer 55 and the thickness T2 of second polysilicon 56. The height H1 of the surface of first polysilicon 54 and the height H2 of the surface of semiconductor substrate 51 are measured from a common reference level. The common reference level can be a bottom plane of semiconductor substrate 51, for example.
Step 60 of trench-type PIP capacitor 50 is smaller than step 31a at end part 31 of traditional planar-type PIP capacitor 22c shown in
Because step 60 is decreased without increasing the thickness of interlayer dielectric film 57 and without flattening interlayer dielectric film 57 by means of the CMP method, production cost is suppressed.
In application of trench-type PIP capacitor 50 to a power IC, trench 52 of trench-type PIP capacitor 50 can be formed simultaneously with the trench of a trench gate type vertical power MOSFET composing the power IC.
Trench-type PIP capacitor 65 of
Trench-type PIP capacitor 65 of the second embodiment comprises isolating insulation layer 53 formed on the inner wall of trench 52, a lower electrode of first polysilicon 54 formed in the trench through isolating insulation layer 53, capacitive insulation layer 55 formed on first polysilicon 54, and an upper electrode of second polysilicon 56 formed on capacitive insulation layer 55. The surface height H3 of second polysilicon 56 is made substantially equal to the surface height H1 of semiconductor substrate 51.
Because the step at end part 66 of the trench-type PIP capacitor 65 is eliminated, the thickness T6 of metal layer 59 for wiring is thinner than the thickness T5 of metal layer 59 in trench-type PIP capacitor 60 of
Diffusion layer 61 can be formed in trench-type PIP capacitor 65 of the second embodiment to reduce the voltage across isolating insulation layer 53, although no drawing is given.
Diffusion layer 63 can be formed in trench-type PIP capacitor 65 of the second embodiment to reduce the voltage across isolating insulation layer 53, although no drawing is given.
The power IC of
Vertical power MOSFET 21 with a trench gate structure has a trench gate structure in which gate oxide film 7a is formed on the inner wall of trench 35a and polysilicon 6a for gate electrode is embedded in the trench through gate oxide film 7a. MOSFET 21 comprises p-type channel region 5, n+-type source region 9a disposed in the surface region of p-type channel region 5, and high concentration p+-type contact region 10 that is connected to p-type channel region 5 and deeper than n+-type source region 9a.
N+-type source region 9a and p+-type contact region 10 are connected to metal layer 12f, which becomes a source terminal of vertical power MOSFET 21 with a trench gate structure. Metal layer 1 is formed on the rear surface of the semiconductor substrate. Metal layer 1 becomes a drain terminal.
Interlayer dielectric film 13a is disposed between polysilicon 6a and metal layer 12f to electrically insulate the two from each other. Edge termination structure 23 has a field plate structure that comprises oxide film 11d, polysilicon 6a formed on oxide film 11d, and metal layer 12g connected to polysilicon 6a. The field plate structure enhances breakdown voltage.
Lateral MOSFET 22a composing a control circuit comprises p−-type well region 4a, n+-type drain region 9b, n+-type source region 9b (the drain region and the source region are given the same symbol 9b), and p+-type contact region 8a. Metal layer 12a and 12b become a drain terminal and a source terminal, respectively. Metal layer 12c is a back gate terminal connected to p+ contact region 8a. Polysilicon 6a becomes a gate terminal.
Trench-type PIP capacitor 22d, which is the same as trench-type PIP capacitor 50 in
Oxide film 6d is disposed between the lower electrode of polysilicon 6c and n−-type epitaxial layer 3, to electrically insulate trench-type PIP capacitor 22d from n−-type epitaxial layer 3. Oxide film 6d corresponds to isolating insulation layer 53 in
The surface height of polysilicon 6c is made equal to the surface height of n−-type epitaxial layer 3. This configuration is achieved by etching polysilicon 6c deposited on the whole surface using n−-type epitaxial layer 3 as a stopper for the etching process.
As described previously with reference to
Between lateral type MOSFET 22a and trench-type PIP capacitor 22d an oxide film 11a is formed, which is a LOCOS and works as an element-isolating region.
Although not illustrated here, other LOCOS oxide films 11b and 11c are formed to work as an element-isolating region between circuit elements, for example, a lateral type MOSFET composing a control circuit.
Step 32a at end part 32 of trench-type PIP capacitor 22d according to the invention, having the lower electrode of polysilicon 6c embedded within trench 35b, is smaller than step 31a at end part 31 of the traditional planar-type PIP capacitor 22c shown in
Specific numerical consideration is made in the following for the case in which: a thickness of lower polysilicon 6c of trench-type PIP capacitor 22d (
Because trench-type PIP capacitor 22d of
Step 31a of planar-type PIP capacitor 22c has a thickness of the sum of thicknesses of polysilicon 6c at the bottom, capacitive insulation layer 15, and polysilicon 14 at the top, and is 0.5 μm+0.025 μm+0.25 μm=0.775 μm. Thus, step 32a of trench-type PIP capacitor 22d can be reduced by 0.5 μm, which is the thickness of bottom polysilicon 6c, as compared with step 31a of planar-type PIP capacitor 22c.
Thus, metallic layer 12e for wiring does not need to be excessively thick and a special flattening treatment such as CMP is unnecessary. As a result, obstacles to fine circuit structure are removed while suppressing the rise of manufacturing costs.
In the process of forming trench-type PIP capacitor 22d, integration with general IC processes is easily accomplished by using capacitive insulation layer 15 of a silicon oxide film between an upper electrode of polysilicon 14 and a lower electrode of polysilicon 6c. The silicon oxide film can be formed by a CVD (chemical vapor deposition) method, without adding thermal history that might change the performances of other semiconductor elements.
Reduction of steps is possible by fabricating simultaneously trench 35a of vertical power MOSFET 21, which is an output stage semiconductor element, and trench 35b of trench-type PIP capacitor 22d. Thus the manufacturing cost can be reduced.
Power ICs are generally used by applying a high voltage to output stage semiconductor elements. In such a case, n−-type epitaxial layer 3, which is at the same potential as the drain terminal of vertical power MOSFET 21 having a trench gate structure, is at a high voltage. When the lower electrode of polysilicon 6c is used at a low potential under this condition, a high voltage is applied between n−-type epitaxial layer 3 and lower side polysilicon 6c. Therefore, oxide film 6d is necessarily formed thick to avoid breakdown of the film. When oxide film 6d is made thick, however, the trench width, which is a dimension of the opening of the trench, needs to be broadened corresponding to the increased thickness of oxide film 6d. That is an obstacle against promotion of fine structure of power ICs. When oxide film 6d is not made thick, on the other hand, a high voltage must not be applied between n−-type epitaxial layer 3 and the lower electrode of polysilicon 6c. This requires a circuit design that avoids a low voltage of the lower electrode of polysilicon 6c. This is a constraint on the circuit design.
The next embodiment describes a method for reducing a voltage applied between n−-type epitaxial layer 3 and polysilicon 6c.
When a high voltage is applied between n−-type epitaxial layer 3 and polysilicon 6c for the lower electrode, pn junction 18a between p-type diffusion layer 18 and n−-epitaxial layer 3 is biased in reverse, extending a depletion layer from pn junction 18a. Thus, the applied voltage is partly borne by pn junction 18a to mitigate the electric field applied on oxide film 6d. Thus, provision of p-type diffusion layer 18 avoids breakdown of oxide film 6d without excessively increasing the thickness of oxide film 6d. Consequently, the width of trench 35b is not necessarily broadened eliminating an obstruction against fine structure of a power IC.
Provision of p-type diffusion layer 18 allows the voltage of the lower electrode of polysilicon 6c to be freely set, irrespective of the potential of n−-type epitaxial layer 3, increasing freedom of circuit design.
When trench-type PIP capacitor 65 of Second Embodiment is applied, step 32a is further decreased to make a power IC finer.
When trench-type PIP capacitor 65 of Second Embodiment is applied, step 32a is further reduced to make a power IC finer.
Thus, a trench-type pip capacitor, power integrated circuit device using the capacitor, and method of manufacturing the power integrated circuit device have been described according to the present invention. Many modifications and variations may be made to the techniques and structures described and illustrated herein without departing from the spirit and scope of the invention. Accordingly, it should be understood that the devices and methods described herein are illustrative only and are not limiting upon the scope of the invention.
Number | Date | Country | Kind |
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2011-228961 | Oct 2011 | JP | national |