Patent Application
20090166820
1. Field of the Invention
Embodiments of the present invention relate to a method of fabricating a semiconductor package, and a semiconductor package formed thereby.
2. Description of the Related Art
As the size of electronic devices continue to decrease, the associated semiconductor packages that operate them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die are mounted. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. Common leadframe-based packages include plastic small outlined packages (PSOP), thin small outlined packages (TSOP), and shrink small outline packages (SSOP).
Typically, leadframe packages are fabricated on a strip such as strip 20 shown in prior art
After the die have been mounted and all electrical connections have been established, the respective leadframe packages are encapsulated in a molding compound 32 as shown in
The strip is positioned between the upper and lower mold plates so that the recesses 46 align over each of the respective leadframe packages 22 on the strip 20. Once the strip 20 is properly positioned between the mold plates, the mold plates are closed against the strip 20 and a mold compound, for example molten epoxy resin, is then injected into each of the cavities defined by the upper and lower mold plates to encapsulate each of the leadframe packages on strip 20 as shown in
As each leadframe package is encapsulated around all four sides, the leadframe packages must be laid out on strip 20 with adequate spacing between each package. In particular, across the width of the strip 20, a keep-out area 50 (
The present invention, roughly described, relates to a method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby. In embodiments, instead of individually encapsulating each leadframe on the strip, an entire row or column of leadframes is encapsulated. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages. A reduction in the keep-out area allows the internal leads of each leadframe to be lengthened, and consequently the size of the semiconductor die affixed to the leadframe may be increased. Alternatively, the length of the internal leads and size of the semiconductor die may be kept as in prior art leadframes, but the reduction in the keep-out area may allow the addition of an extra row or column of leadframe packages on the strip.
After the rows or columns of leadframe packages are encapsulated on the strip, the individual leadframe packages may be singulated from the strip. In embodiments where for example a column of leadframe packages have been encapsulated, the strip may be cut with a saw blade across each of the columns on a strip. In addition to separating each of the leadframes in a given column, the saw cuts through a tie bar previously supporting the internal leads on each leadframe to thereby electrically isolate each of the internal leads on the leadframe. Thereafter, each leadframe in the rows of leadframes may be singulated from each other as by a stamping process or a further cutting process.
Embodiments of the present invention will now be described in reference to
Details relating to the fabrication of a semiconductor leadframe package according to the present invention will be described in detail hereinafter with respect to the flowchart of
Encapsulating an entire row or column of leadframes together allows for the reduction in the size of the keep-out area between adjacent leadframes. A reduction in the keep-out area allows the internal leads of each leadframe to be lengthened, and consequently the size of the semiconductor die affixed to the leadframe may be increased.
The fabrication of leadframe packages on strip 100 will now be described with reference to the flowchart of
Leadframes 104 each include internal leads 112 and external leads 114. Internal leads 112 are provided to transfer signals between the bond pads of semiconductor die (described hereinafter) and the external leads 114. External leads 114 in turn transfer signals from the internal leads to a printed circuit board or host device to which the finished leadframe package is mounted. Embodiments of the present invention operate with leadframes including external leads 114 on a single side of the leadframe 104, or on two opposed sides of the leadframe 104 as shown in
Some internal leads (not shown) are located adjacent external leads 114 and extend only a short distance inward for connecting with die bond pads located on a side of the semiconductor die adjacent the external leads 114. However, owing to the large number of electrical connections required between the semiconductor die and leadframe 104, typically the semiconductor die will include die bond pads along a greater number of sides than simply the sides of the die adjacent external leads 114. Therefore, internal leads 112 are provided to connect the die bond pads on the semiconductor die to the external leads 114 from sides of the die that are spaced from leads 114. In accordance with aspects of the present invention, the internal leads 112 shown in the Figures may be lengthened relative to those in conventional leadframes as described in greater detail hereinafter.
Leadframe 104 may further include tie bar 120 on each leadframe. During fabrication, the ends of the internal leads 112 may be affixed to tie bar 120 so that tie bar 120 structurally supports the internal leads 112 during leadframe fabrication. It is understood that the particular layout of internal leads 112, external leads 114 and tie bar 120 shown in the Figures is by way of example, and the actual number and/or position of internal leads 112, external leads 114 and tie bars 120 may vary in alternative embodiments of the present invention. Internal leads 112, external leads 114 and tie bars 120 may be formed on leadframes 104 by known processes such as for example mechanical stamping or various photolithographic processes.
After the pattern of leads has been defined on the strip 100, the leadframes 104 on strip 100 may be inspected in an automatic optical inspection (AOI) in a step 204. Once inspected, one or more semiconductor dies 124 may be affixed to leadframe 104 in step 206 and as shown in
Semiconductor die 124 is mounted on leadframe 104 so that internal leads 112 shown in the Figures extend beneath the semiconductor die and have ends extending out beyond a top edge of the semiconductor die. Die bond pads along the top edge of die 124 (from the perspective of
As indicated above, semiconductor die 124 may include a set of die bond pads 128 around different edges of the semiconductor die. For example, die bond pads 128a lie adjacent external leads 114 on a first side of the die. Die bond pads 128b lie adjacent external leads 114 on the opposite side of the die, and die bond pads 128c lie adjacent a top edge of the semiconductor die spaced from the external leads 114. It is understood that many more die bond pads 128 may be included on die 124 than is shown in
In step 208, semiconductor die 124 may be electrically coupled to leadframe 104 in a known wire bond process. In particular, die bond pads 128a and 128b may be wire bonded to internal leads (not shown) extending between die bond pads 128a/128b and external leads 114. The die bond pads 128c may be wire bonded to ends of the shown internal leads 112, for example at a top of the leadframe 104.
While semiconductor die 124 is shown mounted on top of internal leads 112, it is understood that semiconductor die 124 may be mounted beneath leadframe 104 with a surface including die bond pads mounted directly to the internal leads, or with semiconductor die 124 flipped over so that a surface not including die bond pads 128 are mounted directly to a bottom surface of the internal leads 112. The die mounted on the top surface of the leadframe 104 is not down-set. However, the leadframe 104 may include a down-set in alternative embodiments.
Owing to the fact that a number of leadframes 104 are encapsulated together as explained in greater detail below, the keep-out area between adjacent semiconductor die in a direction transverse to the pin-out direction may be largely or completely removed. The space formerly reserved as a keep-out area may now be used to increase the length of the internal leads 112, and consequently allows for larger semiconductor die 124 than would otherwise be possible in leadframes of the prior art. As indicated above, the ends of internal leads 112 must extend out beyond the edge of the semiconductor die to allow the connection of wire bonds thereto. The multiple encapsulation of leadframes 104 allows internal leads to be made longer and to extend into the keep-out area otherwise found in prior art leadframes. These longer internal leads allow the semiconductor die 124 to be made larger while still being able to bond to the ends of the internal leads protruding out from beneath the semiconductor die 124.
In embodiments, the multiple encapsulation of leadframes allows the internal leads and the semiconductor die to be lengthened between 0.2 to 0.5 millimeters, and more particularly about 0.4 millimeters. Thus, for example, where prior art leadframes could accommodate a semiconductor die having a width as large as approximately 11.15 millimeters, a leadframe according to the embodiments of the present invention can accommodate a die having a width of approximately 11.55 millimeters. This additional area of semiconductor die 124 can be used to add valuable storage capacity and/or function to the finished leadframe package according to the present invention.
In an alternative embodiment, the internal leads and semiconductor die may be left at the same size as prior art designs, but the additional space gained by using the keep-out area allows the leadframes to be packed more closely together on the strip. This may result in the ability to add an extra row of leadframes on strip 100 extending along the pin-out direction.
After semiconductor die 124 has been mounted on leadframe 104 and all electrical connections have been established, leadframes may be encapsulated in step 210 as shown in
The leadframes 104 which may be encapsulated together are those which lie transverse to the pin-out direction. In particular, leadframes 104 which lie next to each other along the pin-out direction must be separately encapsulated so that external leads 114 can extend outside of the molding compound. However, packages which lie next to each other transverse to the pin-out direction have no leads which extend outside of the package in that direction and may be encapsulated together. In the embodiments shown in the Figures, the pin-out direction is along the length of strip 100. Accordingly, as shown in
In the embodiment shown in
In encapsulation step 210, the strip 100 is positioned between the upper and lower mold plates so that the recesses 136 in the top and bottom mold plates align over each column of leadframes 104 on the strip 100. Once the strip 100 is properly positioned between the mold plates, the mold plates are closed against the strip 100 to define cavities around each column of leadframes 104. A mold compound 140 is then injected into each of the cavities defined by the upper and lower mold plates to encapsulate an entire column 102 of leadframes 104 as shown in
Mold compound 140 may be an epoxy resin such as for example available from Sumitomo Corp. and Nitto Denko Corp., both having headquarters in Japan. Other mold compounds from other manufacturers are contemplated. The mold compound 140 may be applied according to various processes, including by transfer molding or injection molding techniques. The columns of leadframes are encapsulated so that all portions of each leadframe 104 are encapsulated, with the exception of external leads 114 which protrude from the mold compound on each leadframe as seen in
In the embodiments shown in the Figures, the leadframe 104 has the semiconductor die 124 on a top surface of the leadframe and is not down-set. Accordingly, as is known in the art, the recesses 136 formed in the top mold plate 130 may be made deeper than the recesses 136 formed in the bottom mold plate 132. The result is that more mold compound is formed above the leadframe 104 than below it. However, as the one or more die 124 extend above the surface of the leadframe, the amount of mold compound above the semiconductor die 124 is approximately equal to the amount of mold compound below it. In this way, the forces exerted on the semiconductor die 124 from above and below the die during the encapsulation process are at least approximately equal to each other. In alternative embodiments, the leadframe 104 may be down-set. In such embodiments, the recesses in the top and bottom mold plates 130, 132 may have the same depth.
After encapsulation step 210, known “de-junk” step 212 and lead plating step 214 may be performed. The de-junk step separates the external leads 114 and removes excess molding compound 140 due to mold flash. The lead plating step plates portions of external leads 114, for example with tin, to prepare the leads for surface mounting to a printed circuit board or host device (not shown). After steps 212 and 214, individual leadframe packages may be singulated from strip 100 in step 216. Singulation step 216 may include two separate processes. In a first process, a cut may be made along the pin-out direction to cut strip 100 into a plurality of rows, each row including one leadframe from each of the former columns on strip 100.
Referring to
After the cut along the pin-out direction, the second process of singulation step 216 may involve the separation of each of the leadframes in the row of leadframes from each other to provide individual leadframe packages 160 as shown in
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
