Patent Application
20090068767
The present invention relates to the formation of semiconductor devices.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
To achieve the foregoing and in accordance with the purpose of the present invention a method for designing an etch recipe is provided. An etch is performed, comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over vias. ESC bias voltage is set such to provide optimal trench profiles for device performance. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained.
In another manifestation of the invention a method of manufacturing semiconductor devices is provided. An etch is performed comprising providing an etch gas with a set halogen to carbon ratio, forming a plasma from the etch gas, and etching trenches over vias. Via faceting is measured. The halogen to carbon ratio is reset according to the measured via faceting, where the halogen to carbon ratio is increased if too much faceting is measured and the halogen to carbon ratio is decreased if too little faceting is measured. The previous steps are repeated until a desired amount of faceting is obtained. A plurality of trenches over vias is etched in a plurality of wafers using the halogen to carbon ratio used for obtaining the desired amount of faceting.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
To facilitate understanding,
In a dual damascene via first process, vias are formed in a dielectric layer.
The stack 200 is placed in a processing chamber.
CPU 1322 is also coupled to a variety of input/output devices, such as display 1304, keyboard 1310, mouse 1312, and speakers 1330. In general, an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers. CPU 1322 optionally may be coupled to another computer or telecommunications network using network interface 1340. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely upon CPU 1322 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
A halogen to carbon ratio is selected for an etch gas (step 104). In this example, the halogen is fluorine. The etch gas is provided from the gas source to the confined plasma volume (step 108). The electrodes are energized to form a plasma from the etch gas (step 112).
In an example of an etch recipe, an etch gas is flowed from the gas source 310 into the plasma processing tool. In this example, the etch gas is 300 sccm of CF4. The chamber pressure is maintained at 100 mTorr. The etch gas is transformed to an etching plasma. In this example, 500 watts at 27 MHz of power is provided through the electrodes. In this example the halogen to carbon ratio is measured by flow rate and is 4:1 If halogen to carbon ratio needs to be decreased, a second gas such as C4F8 or H2 may be added to decrease the halogen to carbon ratio. Conversely, if halogen to carbon ratio needs to be increased a second gas such as O2 or NF3 may be added.
The via faceting is measured (step 120).
Some degree of faceting may be desirable to enable barrier and metal filling of the features. Too much faceting is undesirable and degrades electrical properties of the device. In some examples, too little faceting is undesirable. A determination is made on whether the measured faceting is about equal to the desired faceting (step 124). If the measured faceting is not about equal to the desired faceting a determination is made of whether to increase or decrease faceting. In this example, this is done by determining if there is too little faceting (step 128). If there is too little faceting, the halogen to carbon ratio is decreased (step 132). If there is not enough faceting then the halogen to carbon ratio is increased (step 136). The process goes back to step 108, where the new etch gas with the new etch gas ratio is used. This process is repeated until the desired faceting is reached (step 124). The etch recipe has now been determined. The etch recipe may now be used to etch a plurality of wafers using the etch gas found when the desired faceting is reached.
It has been found that the wider features tend to etch faster than the narrower features, which is called aspect ratio dependent etching (ARDE) or reactive ion etch (RIE) lag. To minimize ARDE or RIE lag, a bias voltage is applied at a sufficient amplitude to minimize ARDE or RIE lag. It has been found that an increase in the bias voltage increases faceting. Without wishing to be bound by theory, it is believed that electrons form an electron charge on the surface of the mask material. For high aspect ratio features, the features are thin enough to allow the electron charge to slow etching ions that are positively charged, reducing the etch rate of the high aspect ratio features. Wider low aspect ratio features have less of a slowing effect, so that the etch rate is not as significantly reduced, resulting in a higher etch rate for the lower aspect ratio devices. The difference in etching speeds causes RIE-lag (reactive ion etch-lag) or ARDE (Aspect Ratio Dependent Etch). It is believed that photoresist masks are more susceptible to charging, so that using photoresist masks may increase ARDE. As feature sizes decrease, RIE-lag problems increase.
One way to reduce the ARDE is to increase ion energy by increasing the bias voltage. However, increasing the bias voltage increases faceting. It would be desirable to reduce or more preferably eliminate ARDE or RIE-lag and be able to tune a desired amount of faceting. Having some faceting may make the features easier to fill.
One unexpected result found by an embodiment of the invention is that the halogen to carbon ratio of the etch gas may be adjusted to adjust faceting without affecting RIE-lag or ARDE. Therefore, a bias voltage may be selected to reduce or preferably eliminate RIE-lag or ARDE and then a halogen to carbon ratio may be found to tune the faceting to a desired faceting. This property is shown through the following graphs.
Although different mask materials may be used as mask for the etching process, preferably, the mask is a photoresist mask. Although different materials may be etched by this process, preferably the layer that is etched is a dielectric layer. More preferably, the layer that is etched is a low-k dielectric layer, where k<3.0. More preferably, the low-k dielectric layer is porous. The reason that the mask is preferably a photoresist mask and the layer to be etched is a porous low-k dielectric layer is that with such a combination it is especially difficult to reduce or eliminate ARDE while tuning the faceting. The inventive method is able to solve such a problem with various materials and masks and in addition solve the special difficulty provided by the above specific combination. The features may be subsequently filled with a conductive material to form conductive contacts. The tuning of the facets allows for improved conductive contacts, by providing a faceting that provides optimum electrical contacts.
As aspect ratios increase, the ability to tune faceting increases in importance. The use of higher bias may be preferred for other reasons than reducing RIE-lag.
While this invention has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present invention.
