The subject matter disclosed herein relates to integrated circuits. More particularly, the subject matter relates to via leakage and breakdown testing.
An integrated circuit (IC) is a semiconductor device containing many small, interconnected components. These components function together to enable the IC to perform a task, such as control an electronic device, or perform logic operations. ICs are found in computers, cellular telephones, and many other electronic devices.
ICs and other semiconductor devices typically comprise multiple layers. The connections between the layers are known as vias. In integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers of an IC. Multiple vias may be coupled together to connect one conductive region in an IC to another conductive region in the same or an adjacent IC.
Vias are subject to manufacturing errors. When a manufacturing error occurs in a via, the via may not conduct properly and thus may prohibit an IC from functioning correctly. Therefore, the testing of via structures is an important aspect of IC production and reliability.
Via related leakage and breakdown is one of the top issues for back end of the line (BEOL) process development and reliability. Traditional via testing structures such as via-comb (
A first aspect includes a testing structure, comprising: a first three terminal via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.
A second aspect includes semiconductor wafer, comprising: a first three terminal via testing structure, including: a first terminal coupled to a first set of sensing lines in a top level of the structure; a second terminal coupled to a second set of sensing lines in the top level of the structure, wherein first set of sensing lines and the second set of sensing lines are disposed in a comb arrangement; a third terminal coupled to a third set of sensing lines in a bottom level of the structure; and a plurality of vias electrically coupling the second set of sensing lines in the top level of the structure to the third set of sensing lines in the bottom level of the structure, each via having a via top and a via bottom.
A third aspect includes a testing method, comprising: providing a three terminal via testing structure including at least one via; and isolating and obtaining via top measurement data at a top of the via and via bottom data at the bottom of the via using the three terminal via testing structure.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention.
As noted, the subject matter disclosed herein relates to integrated circuits. More particularly, the subject matter relates to via leakage and breakdown testing.
In embodiments, the via testing structures (hereafter “via testing structures”) of the present disclosure may be located in the kerf regions surrounding the semiconductor dies on a semiconductor wafer. The kerf regions are areas where the semiconductor wafer will be cut to separate individual semiconductor dies when the fabrication process is complete. In other embodiments, the via testing structures may be located inside the semiconductor dies, as well. The via testing structures may be formed using semiconductor processing techniques on a semiconductor wafer.
A three terminal via testing structure 10 according to embodiments is depicted in
In the embodiment shown in
The via testing structure 10 further includes a lower level 14 comprising a plurality of spaced apart sensing lines E3. The sensing lines E3 are designated as “Leak Below” sensing lines. The sensing lines E2 in the upper level 12 of the via testing structure 10 are electrically coupled to the sensing lines E3 in the lower level 14 of the via testing structure 10 through vias V0. The sensing lines E2 are electrically coupled to a second terminal T2. The sensing lines E3 are electrically coupled to a third terminal T3. In embodiments, the sensing lines E1, E2 in the upper level 12 of the via testing structure 10 and the sensing lines E3 in the lower level 14 of the via testing structure 10 run perpendicularly to each other. As seen in
Unlike conventional via testing structures, such as the via-comb testing structure shown in
According to embodiments, as depicted in
Other data can be derived by employing a testing structure similar to that depicted in
The testing structure 30 further includes a lower level 34 comprising a plurality of spaced apart sensing lines E3. Unlike in the via testing structure 10 depicted in
According to embodiments, via-line versus line-line problems can be examined by comparing the operation of the via testing structure 10 of
Using via testing structures 50, a wide variety of data can be quantitatively extracted and used to analyze, for example, overlay, via size, line width, via-line, and other issues.
Other information can be obtained by comparing breakdown voltage versus via V0 misalignment for a plurality of the via testing structures 50 having different via V0 misalignments. An illustrative chart depicting breakdown voltage versus misalignment is shown in
In
The actual spacing XPP between two lines can be extracted from the chart in
Various exemplary embodiments of via test structures have been disclosed herein. However, those skilled in the art should understand that the number of components (e.g., sensing lines, vias, terminals, etc.) in such via testing structures are not limited to those depicted in the Figures.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.
When an element or layer is referred to as being “on”, “engaged to”, “connected to” or “coupled to” another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly engaged to”, “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Spatially relative terms, such as “inner,” “outer,” “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to an individual in the art are included within the scope of the invention as defined by the accompanying claims.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
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