Patent Application
20070013080
An embodiment relates to a voltage regulator on a chip.
A voltage regulator for a microelectronic device must provide a steady voltage and an ability to respond to dynamic current demands of the device. In order to respond appropriately to a dynamic current demand, a collection of decoupling capacitors is disposed in serial groups relative to the microelectronic device location. The closer the capacitor type is to the microelectronic device, the faster response it has. The farther the capacitor type is from the processor, the slower response it has, but the greater capacity it can bear.
In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. Understanding that these drawings depict only typical embodiments that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
The following description includes terms such as upper, lower, first, second, etc., that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. The terms “die” and “chip” generally refer to the physical object of semiconductive material that is the basic workpiece that is transformed by various process operations into the desired integrated circuit device. A die is usually singulated from a wafer, and wafers may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting materials. A board is typically a resin-impregnated fiberglass structure that acts as a mounting substrate for the die.
An embodiment relates to a voltage regulator on a chip that is embedded in a processor-package. The voltage regulator on a chip can be referred to as an embedded, integrated semiconductor voltage regulator (ISVR). Various operations will be described as multiple discrete operations performed in turn in a manner that is helpful in understanding the embodiments. However, the order of description should not be construed as to imply that these operations are necessarily performed in the order they are presented, or even order dependent. The repeated usage of the phrase “in an embodiment” does not necessarily refer to the same embodiment, although it may.
Embodiments relate to an embedded voltage regulator on a chip that is part of a chip package. Embedding the voltage regulator into a chip package allows the voltage regulator to be closer to a microelectronic device it is intended to service, which is also in the chip package. In various embodiments, as discussed below, embedding the voltage regulator on a chip into the chip package also simplifies thermal solutions and input/output solutions.
A voltage regulator on a chip that is embedded in a chip package provides and input/output (I/O) solution between a microelectronic device such as a central processing unit (CPU) and a system board such as a motherboard or an expansion card and others. In disclosed embodiments, the embedded voltage regulator on a chip is integrated into a chip package that includes a CPU. The embedded voltage regulator on a chip is comprised of integrated components that provide power at the relatively large rate required by a CPU, and yet the integrated components fit within the limited height of the chip package.
By embedding the voltage regulator on a chip into the chip package, the voltage regulator on a chip can be positioned as close as possible to, e.g., a CPU without actually being integrated into the CPU. The amount of power needed to regulate power to a CPU increases the farther away the voltage regulators are located. In disclosed embodiments, the embedded voltage regulator on a chip can be positioned very close the microelectronic device. Accordingly, the voltage regulator on a chip can provide power more efficiently and it does not need as much capacity as a non-voltage regulator on a chip that is located more remotely from the microelectronic device such as upon a motherboard.
Reference will now be made to the drawings wherein like structures will be provided with like reference designations. In order to show the structure and process embodiments most clearly, the drawings included herein are diagrammatic representations of embodiments. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the essential structures of embodiments. Moreover, the drawings show the structures helpful to understand the embodiments. Additional structures known in the art have not been included to maintain the clarity of the drawings.
In
The voltage regulator on a chip 120 includes an active surface 122. An “active surface” in an integrated device such as a silicon-based chip, means the surface of the chip upon which the various process operations have been accomplished to achieve transistors, capacitors, inductors, resistors, and circuits made thereof. A back surface represents the side of the chip that is substantially parallel to and opposite the active surface.
The microelectronic device 112 also includes an active surface 123 and a back surface 124. In an embodiment, the active surface 122 of the voltage regulator on a chip 120 faces the active surface 123 of the microelectronic device 112. This configuration allows for rapid communication between the microelectronic device 112 and the voltage regulator on a chip 120.
In an embodiment, the package 110 includes a ceramic material core 116 that is used to package a processor. By a “core” it is meant a structure that at least partially encompasses, in elevational cross-section, a device such as a microelectronic device. In many embodiments in this disclosure, the core 116 is a form factor that encompasses the voltage regulator on a chip 120 when viewed in elevational cross-section. In an embodiment, the core 116 includes ceramic material. In an embodiment, the core 116 includes an epoxy material. In an embodiment, the core 116 includes a combination of a ceramic and an epoxy. In an embodiment, the core 116 includes a metallic material. In an embodiment, a heat sink 126, disposed above the microelectronic device 112, includes metallic material.
In an embodiment, the voltage regulator on a chip 120 includes a decoupling capacitor capability that is integrated in the semiconductive material. The decoupling capacitor capability may include a plurality of decoupling capacitors that also may include inductors and resistors according to known voltage-regulator technique.
In an embodiment, the voltage regulator on a chip 120 includes capabilities such as a DC voltage converter and a Buck switching regulator to convert an input voltage VIN into an output voltage VOUT. In this manner, the VIN input voltage and a VOUT voltage can be regulated by solid-state logic on the voltage regulator on a chip 120. In an embodiment the voltage regulator on a chip 120 is regulated by logic on the microelectronic device 112.
In some embodiments, the voltage-regulator logic is used in a manner that, in general, causes the “on” times of two voltage regulators on chips to be shifted 180° apart. In other embodiments, the voltage-regulator logic directs a multiphase regulator scheme other than a two-phase regulator. Accordingly, the logic may direct two voltage regulators on chips generate signals to control operation of the microelectronic device 112 such that the switch control signals have the proper phase relationship between the two embedded voltage regulators on chips. Other examples include a three-phase regulation wherein three voltage regulators on chips control signals are 120° apart, a four-phase regulation wherein four voltage regulators on chips control signals are 90° apart, etc.
In addition to phase control capabilities in the voltage regulator on a chip 120, a DC power converter is also part of the voltage regulator on a chip 120 according to an embodiment. The DC power converter is used among other things to convert higher voltage such as 48 V, 12 V, 5 V, and others to Vcc. In an embodiment, where the microelectronic device 112 is a processor for a digital computer or the like, Vcc is in a range of about less than or equal to 3 V. In an embodiment, the Vcc is in a range from about 1 V to about 2 V. In an embodiment, Vcc is about 1.2 V.
Referring again to
In an embodiment, only one of the voltage regulator on a chip 120 is present in the package 110. In a contrasting embodiment, only one of the voltage regulator on a chip 120 is present along with the microelectronic device 112. In an embodiment, the microelectronic device 112 is a processor manufactured by Intel Corporation of Santa Clara, California. In an embodiment, the voltage regulator on a chip 120 and the microelectronic device 112 take up reversed positions as depicted in
The first BBUL 214 is disposed upon a core 216. In an embodiment, the core 216 includes any of the materials and material combinations set forth for the core 116 depicted and described in
In an embodiment, a voltage regulator on a chip 220 is disposed in the package 210. In
The voltage regulator on a chip 220 includes an active surface 222. The microelectronic device 212 also includes an active surface 213 and a back surface 224. In an embodiment, the active surface 222 of the voltage regulator on a chip 220 faces the active surface 213 of the microelectronic device 212.
In an embodiment, at least one of the microelectronic device 212 and the voltage regulator on a chip 220 is embedded in the package 210. In an embodiment, a portion of the core 216, which lies in the intersection of the bracket 238 as it is projected onto the core 216 is used as space for a decoupling capacitor. Consequently, the intersection is between the two embedded voltage regulators on chips 220, and the core in this intersection can be replaced and left open for a decoupling capacitor, such as a parallel-plate capacitor. In an embodiment, the decoupling capacitor that is locatable in the space left open by the intersection of the bracket 238 and the core 216, is controllable by logic, either on the voltage regulator on a chip 220 or on the microelectronic device 212.
In an embodiment, only one of the voltage regulator on a chip 220 is present. In an embodiment, only one of the voltage regulator on a chip 220 is present along with the microelectronic device 212. In an embodiment, the microelectronic device 212 is a processor. In an embodiment, the voltage regulator on a chip 220 and the microelectronic device 212 take up reverse positions as depicted in
In an embodiment, the first BBUL 214 also includes a bond pad 234 that is located on the periphery of the package 210, such that the bond pad 234 represents a pin-out capability that is above the first BBUL 214. Accordingly, the pin-out capability of the bond pad 234 is available for the voltage regulator on a chip 220 or the microelectronic device 212 if present, or both according to an embodiment.
In an embodiment, where the package 210 includes a pin-out capability below the first BBUL 214, the core 216 includes a pin-out via 236 that couples the BBUL 214 to the plurality of pins 232. Where as disclosed, the intersection of the bracket 238 as it is projected to the level of the core 216, is replaced with a decoupling capacitor, pin-out vias 236 can also be located within the capacitor.
In an embodiment, where the package 210 is a traditional substrate such as a printed wiring board and the active surfaces 213 and 222 of the respective microelectronic device 212 and voltage regulator on a chip 220 are bumped to the printed-wiring board package 210 by traditional methods instead of a BBUL package.
The first BBUL 314 is disposed upon a core 316. In an embodiment, the core 316 is disposed upon a second BBUL 318. In this embodiment, pin-out capabilities are enhanced due to the second BBUL 318.
In an embodiment, a voltage regulator on a chip 320 is disposed in the package 310. In
The voltage regulator on a chip 320 includes an active surface 322. The microelectronic device 312 also includes an active surface 313 and a back surface 324. In an embodiment, the active surface 322 of the voltage regulator on a chip 320 faces the active surface 313 of the microelectronic device 312.
In an embodiment, at least one of the microelectronic device 312 and the voltage regulator on a chip 320 is embedded in the package 310. In an embodiment, a portion of the core 316, which lies in the space created by the intersection of the projection of the bracket 338 onto the core 316, is between the two embedded voltage regulators on chips 320. This portion of the core 316 includes the intersection that can be replaced with a decoupling capacitor, such as a parallel-plate capacitor. In an embodiment, the decoupling capacitor that is locatable in the intersection of the core and the projection of the bracket 338 onto that portion of the core 316, is controllable by logic, either on the voltage regulator on a chip 320 or on the microelectronic device 312.
In an embodiment, only one of the voltage regulator on a chip 320 is present. In an embodiment, only one of the voltage regulator on a chip 320 is present along with the microelectronic device 312. In an embodiment, the microelectronic device 312 is a processor. In an embodiment, the voltage regulator on a chip 320 and the microelectronic device 312 take up reversed positions as depicted in
In an embodiment, the first BBUL 314 also includes a bond pad 334 that is located on the periphery of the package 310, such that the bond pad 334 represents a pin-out capability that is above the first BBUL 314, as well as above the second BBUL 318. Accordingly, the pin-out capability of the bond pad 334 is available for the voltage regulator on a chip 320 or the microelectronic device 312 if present, or both according to an embodiment.
In an embodiment, where the package 310 includes a pin-out capability below the first BBUL 314, the core 316 includes a pin-out via 336 that couples the first BBUL 314 to the plurality of pins 332.
For purposes of this disclosure, a computing system 500 embodying components in accordance with the claimed subject matter may include any system that utilizes an embedded ISVR, which may be coupled to a mounting substrate 520. In an embodiment, the embedded ISVR is in the package 510. In an embodiment, the embedded ISVR is in the package 510 and is coupled to a die, for example, as depicted in either of
Embodiments set forth in this disclosure can be applied to devices and apparatuses other than a traditional computer. For example, a die can be packaged with an embodiment of the embedded ISVR and placed in a portable device such as a wireless communicator or a hand-held device such as a personal digital assistant and the like. Another example is a die that can be packaged with an embedded ISVR and placed in a vehicle such as an automobile, a locomotive, a watercraft, an aircraft, or a spacecraft.
The Abstract is provided to comply with 37 C.F.R. § 1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the invention require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate preferred embodiment.
It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.
