Patent Application
20180233410
This invention relates to methods for the singulation of integrated circuit die from processed wafer substrates, also known as “wafer dicing”.
Integrated circuits (ICs) are almost universally fabricated as multiple units formed on wafer substrates. Common wafer substrates include silicon, sapphire, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), gallium arsenide, and various glasses, but a wide variety of other materials have been used. In general, multiple individual IC die, typically numbering in the hundreds to thousands, are formed as complex two-dimensional and three-dimensional patterns of insulating, semiconductive, and conductive materials on one side of a wafer substrate. IC functionality may include electronic, micromechanical, sensor, and/or other technologies.
Individual die are generally separated from other dies on a wafer substrate by cutting “streets” (also known as dicing “lanes” or kerfs). Die singulation, also known as wafer dicing, is part of the die preparation flow in the fabrication process that separates individual die on a finished wafer substrate for further packaging or direct usage. Wafer dicing is one of the most critical elements of the IC fabrication process, where reduction of defects and improvements in quality can make a significant contribution to final yield and per unit costs for the ICs. Defects may include chipped IC die edges and stress fractures that reduce IC die strength and increase the chance of breaking during later assembly steps or in actual use.
A number of mechanical-based and non-mechanical methods have been developed for singulating dies from a wafer substrate along cutting streets. Mechanical-based methods include, for example, diamond scribing to create cleave lines (followed by breaking, such as by bending the wafer substrate), and rotary blade saws to create partial-depth cleave lines or full-depth cuts through a wafer substrate. Non-mechanical methods include, for example, ablative lasers that essentially sublime and/or vaporize material, plasma etching that uses hot ions to essentially vaporize and “sand blast” material, and so-called stealth dicing based on use of infrared (IR) lasers to create subsurface sites suitable to form preferred cleaving planes. For purposes of this document, these and other singulation methods will be considered to generate a cut along cutting streets of a wafer substrate.
With respect to stealth dicing, a number of thin wafer substrate materials, such as silicon, are substantially transparent to infrared light. Stealth dicing IR lasers penetrate the backside surface of such wafer substrates and focused heating from the laser creates highly localized and brief melting, transforming crystalline material (e.g., silicon) into a modified material (e.g., polycrystalline silicon) surrounded by a field of concentrated stress and micro cracks. The IR laser is sequentially focused at different depths in a wafer substrate, so that stacked vertical planes of modified material are formed. These subsurface modified layers essentially create weakened cleaving planes that enable mechanical separation. Stealth dicing generally leaves no visible marks on the wafer's outer surface.
The chosen method of wafer dicing generally depends on such factors as wafer substrate material and thickness, presence of complicating materials (e.g., metal, test element groups (TEGs), etc.) within the cutting streets (“in-street structures”), metallization on the backside of a wafer substrate, defect type and degree, and kerf width produced by the singulating method (wide kerfs reduce the number of available dies from a wafer substrate). For example, the presence of metal and/or TEGs within cutting streets generally prohibits use of cutting saws, since such in-street structures may clog a saw. Rotary blade cutting and mechanical scribing can also cause die edge chipping or cracking, leading to lower yields, and both methods generally have relatively wide kerfs (e.g., greater than about 50 μm). Backside metallization may prohibit use of certain laser-based methods, or pose cutter alignment problems. Stealth dicing does not work for IC dies having in-street metal or TEGs on the patterned front side of a wafer substrate, since the subsurface modified layers do not cut the front-side structures, resulting in errant breaks in the metal and/or inability to separate dies.
Another problem of wafer dicing is developing efficient cutting plans for all wafer substrates. Most production wafer substrates are dedicated to same-size rectangular IC dies arrayed in a two-dimensional rectangular grid. Accordingly, most or all of such IC dies can be placed on a chuck and separated by making a first set of parallel straight-line cuts across a wafer substrate, followed by a second set of orthogonal parallel straight-line cuts across the wafer substrate (the cutter is generally affixed to a processing head that can be programmed with X-Y translation movements). However, some wafer substrates, referred to as multi-project wafers or multi-product wafers (MPWs), contain different size IC dies and/or non-uniform grid pattern layouts of ICs and/or non-rectangular ICs.
For example,
To deal with non-uniform grid layouts of ICs such as those shown in
Despite the various cutting methods that have been developed for various combinations of IC dies and wafer substrate characteristics, there is still a need for improved wafer dicing methods for certain types of wafer substrates that simplify the singulation process, improve device reliability and die strength, reduce cutting kerf and hence reduce cutting street width, and improve yield. The present invention addresses this need.
The present invention encompasses improved wafer dicing methods that simplify the singulation process for certain types of wafer substrates, improve device reliability and die strength, reduce the width of the cutting kerf, reduce cost and improve yield. Embodiments of the invention can effectively recover essentially all integrated circuit (IC) dies of different sizes on a wafer substrate without sacrificing any IC die of interest and can be used as well with wafer substrates having uniformly sized IC dies. The fine cuts available with the inventive methods allow extending dicing of ICs to as small as 0.4 mm of a die side size and allow singulation kerf widths to be essentially only limited by the focus spot diameter of an ablative laser.
A first method of dicing a wafer substrate (which may be an MPW) patterned on its front side with integrated circuit (IC) dies and having its backside adhered to a dicing tape (DT) includes the steps of:
A second method of dicing a wafer substrate (which may be an MPW) patterned on its front side with IC dies and having its backside adhered to a DT includes the steps of:
Variants of the above method include pre-singulation preparatory steps for the wafer substrate such as wafer thinning and dicing tape adherence, and post-singulation steps such as dicing tape adhesion release (e.g., with UV light) and die picking.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
The present invention encompasses improved wafer dicing methods that simplify the singulation process for certain types of wafer substrates, improve device reliability and die strength, reduce the width of the cutting kerf, reduce cost and improve yield. Embodiments of the invention can effectively recover essentially all integrated circuit (IC) dies of different sizes on a wafer substrate without sacrificing any IC die of interest. and can be used as well with wafer substrates having uniformly sized IC. The fine cuts available with the inventive methods allow extending dicing of ICs to as small as 0.4 mm of a die side size and allow singulation kerf widths to be essentially only limited by the focus spot diameter of an ablative laser.
Overview
The example process for “ablative scribing before stealth dicing” includes the steps of:
Variants of the above method include pre-singulation preparatory steps for the wafer substrate such as wafer thinning and dicing tape adherence, and post-singulation steps such as dicing tape adhesion release (e.g., with UV light) and die picking.
One or more layers 310 of various structures may be formed in known fashion within and/or on the front side of the bulk of the wafer substrate 300. The structures are generally two-dimensional and three-dimensional patterns of insulating, semiconductive, and conductive materials and may include electronic, micromechanical, sensor, and/or other technologies. The thickness of each of the formed layers 310 is generally relatively small (e.g., often less than about 1 um) compared to the thickness of the thinned wafer substrate 300 as a whole; the illustration exaggerates the vertical dimension of the formed layers 310 for purposes of clarity. In general, before singulation cutting commences, a protective coating or film 312 may be applied in known fashion to the front side of the wafer substrate 300 to prevent damage to the IC dies from the singulation process. For example, a compound including polyvinyl alcohol (PVA) may be applied to the front side of the wafer substrate 300 before laser ablation to protect the front surface from debris caused by the laser ablation process. After laser ablation, the PVA may be washed from the wafer surface.
Once the cutting plan is determined, an ablative laser is automatically guided by the cutting plan to make pre-scoring scribing passes around the target IC dies inside the mapped cutting streets, and thus all around the target IC dies. Ablation is a method that sublimes and/or vaporizes a solid workpiece by irradiating it with a focused laser beam (typically a UV laser having a wavelength of about 355 nm) for a short period of time (e.g., a laser pulse duration on the order of femto-seconds through nano-seconds, at a repetition rate of kilohertz through megahertz); multiple adjacent pulses provide for essentially continuous cutting. An ablative laser generally provides high-speed and high-quality cutting, and may be co-mounted with a mapping imaging system on the same processing head. In addition, by focusing the laser beam on a spot less than about 20 μm, and especially less than about 10 μm in diameter, a significant street-width reduction can be achieved in comparison to some other dicing processes, thus generally enabling an increase in the number of IC dies per wafer substrate by crowding the IC dies closer together. For comparison, the kerf of a wafer cutting saw is typically at least about 50 μm.
An important aspect of the process is that the pre-scoring scribing passes should be sufficient to clear surface material from a region of the cutting streets (e.g., cutting through metal features in the cutting streets) and help create stress lines within the front surface of the patterned wafer substrate 300. Thus, in general, one or more passes of the focused ablative laser beam 406 are made along the cutting plan lines 402 shown in
It has been found that deeper ablative cutting, into the original bulk material of the wafer substrate 300 (i.e., below the formed layers 310), generally has the beneficial effect of creating the beginnings of a cleavage plane in the wafer substrate 300 that, in combination with subsequent stealth dicing, further enhances die singulation. The cutting depth may vary with the type of wafer substrate material.
For wafer substrates 300 having IC dies patterned in a non-rectangular grid, such as the MPW of
All IC dies on the patterned front-side of the wafer substrate are mapped to determine the location of the front-side IC dies and ablative laser scribed cuts 404. For certain substrate types, such as silicon and sapphire, the IC dies formed on the front side of the wafer substrate 300 and the front-side ablative laser scribed cuts 404 are visible to an IR microscope imaging system from the backside of the wafer substrate 300 (for sapphire, the front-side ablative laser scribed cuts 404 may be visible at visible wavelengths as well). Accordingly, an IR imaging system may be used to scan the backside of the wafer substrate 300 and create a stealth dicing laser cutting plan, in known fashion. Alternatively, mapping may be performed by a microscope imaging system (visible light or IR) from the front side of the wafer substrate 300, and the coordinates transformed appropriately to a representation of the IC die and ablative laser scribed cut positions as they would be “seen” from the backside of the wafer substrate 300. Thus, such an imaging system may be used to scan the front side of the wafer substrate 300 and create a stealth dicing laser cutting plan, in known fashion. The heavy lines 502 in
Multiple passes of the IR stealth dicing laser beam 504 with different focal points may be made to create multiple subsurface modified layers 508 at different depths underneath the backside of the wafer substrate 300. Three such modified layers 508 are shown in the illustrated example, but more or fewer layers may be used, generally as a function of the thickness of the wafer substrate 300. (Note that the three black ovals representing the modified layers 508 are seen end-on in
Because the cutting plan for the IR stealth dicing laser beam 504 is based on the mapped positions of the front-side IC dies and ablative laser scribed cuts 404, the subsurface modified layers 508 created by stealth dicing passes around the target IC dies will be substantially aligned with the mapped front-side ablative laser scribed cuts 404. Such alignment enhances cleaving along planes defined by the front-side ablative laser scribed cuts 404 and the aligned modified layers 508 created through the backside of the wafer substrate 300 by the IR stealth dicing laser beam 504. For wafer substrates 300 having IC dies patterned in a non-uniform grid pattern, such as the MPW of
Of note, stealth dicing essentially has no kerf width and thus greatly contributes to street-width reduction, generally enabling an increase in the number of IC dies per wafer substrate by crowding the IC dies closer together.
The IC dies may be singulated from the wafer substrate 300 along the cleaving planes defined by the front-side ablative laser scribed cuts 404 and the aligned modified layers 508 created through the backside of the wafer substrate 300 by the IR stealth dicing laser beam 504. According to one method, the DT 410 on which the wafer substrate 300 is mounted is expanded in known fashion (e.g., centro-symmetric expansion), thereby mechanically stressing the cleaving planes until they break, thus singulating the IC dies.
For example,
Centro-symmetric expansion is particularly advantageous for MPWs, since the cleaving planes will not form sets of parallel and regular X-Y lines. However, other known mechanical methods of breaking the wafer substrate 300 along the cleaving planes may be used for wafer substrates having IC dies patterned in a rectangular grid. After singulation, the IC dies may be picked and placed in conventional fashion (e.g., to a tape-and-reel machine).
In an alternative embodiment, the process illustrated in
With the “stealth dicing before ablative scribing” method, mapping of target IC dies on the patterned front-side of the wafer substrate to determine the location of cutting streets before stealth dicing may be performed from the backside or front side of the wafer substrate. The mapping step need only be carried out once, in theory, if the stealth laser and the ablative laser are aligned or can be aligned to the same mapping system. Thus, as mentioned above, use of a single mapping is possible for both sequence orders of the two laser passes (i.e., ablative scribing, then stealth dicing, or stealth dicing, then ablative scribing), depending on accuracy of alignment of the laser cutting tool to the mapping tool. Optionally, the target IC dies on the patterned front-side of the wafer substrate can be separately re-mapped to determine the location of the front-side ablative laser scribed cuts.
In one experiment, multiple rectangular IC dies of various sizes were formed in an MPW configuration on a 200 μm thick wafer substrate, with cutting streets having metal of about 10-12 μm thickness. Three ablative laser scribing passes were made within the cutting streets using hasen cuts. The ablative cutting laser was focused to a spot diameter of about 13.25 μm, and made a scribed cut through the metal in the cutting streets and extending about 32.15 μm below the surface of the wafer substrate. After hasen cut stealth dicing, the IC dies, mounted on a dicing tape (DT), were separated by centro-symmetric expansion of the DT with no cracks or chipouts on their edges. Nearly 100% of the IC dies were recovered, even at IC die sizes as small as 0.4 mm square. This outcome was an unexpected result for at least two reasons. First, using stealth dicing alone, IC die sizes have been limited to no less than about 1.0 mm square, and there was no expectation that making scribing cuts on the front side of a wafer substrate would change that parameter. Second, the amount of force transferred from the expanding DT to the cleaving planes of each IC die is a function of die size, and thus it was expected that smaller IC dies would not break and separate as readily as large IC dies. However, using the current invention, the cleaving planes formed by the combination of front-side ablative laser scribed cuts 404 (particularly cuts extending into the bulk material of a wafer substrate 300 below the formed layers 310) and the aligned modified layers 508 created through the backside of the wafer substrate 300 by stealth dicing reduce the force needed to singulate the IC dies.
While the above examples have illustrated singulation of essentially all dies from a wafer substrate, in some cases, the same process may be used to singulate only selected target dies. For examples, referring to
In STEP 700a, a grinding tape 702 is adhered to the front side of a wafer substrate 704 which has been patterned on its front side with IC dies.
In STEP 700b, the backside of the wafer substrate 704 is ground down by a grinder 706 to achieve a desired thickness for the wafer substrate 704. Optionally, the backside of the wafer substrate 704 may be polished after grinding (not shown).
In STEP 700c, a dicing tape (DT) 708 transparent to infrared wavelengths is adhered to the backside of the thinned wafer substrate 704.
In STEP 700d, the grinding tape 702 is removed from the front side of the wafer substrate 704. Optionally, a protective coating may be applied to the front side of the wafer substrate 704.
In STEP 700e, the front side of the wafer substrate 704 is mapped to create a first cutting plan, as described above, and an ablative laser 706 makes scribed cuts on the front side of the wafer substrate 704 as determined by the first cutting plan. Hasen ablative cuts are used for MPWs.
In STEP 700f, the front side of the wafer substrate 704 is again mapped (from the backside, using an IR imaging system, or directly from the front side) to create a second cutting plan, as described above, and an IR laser 708 makes stealth dicing “cuts” (i.e., subsurface modified layers) as determined by the second cutting plan but from the backside of the wafer substrate 704. Hasen stealth dicing cuts are used for MPWs.
In STEP 700g, the wafer substrate 704 is expanded centro-symmetrically to break apart the IC dies along cleaving planes formed by the front-side ablative laser scribed cuts and the aligned modified layers created through the backside of the wafer substrate 704 by the IR laser 708. Expansion may be performed, for example, by an expansion chuck 710 pushing up on the bottom side of the DT to stretch the tape, in known fashion.
In STEP 700h, infrared energy from an emitter 712 (e.g., a far infrared, or FIR, emitter) may be used to “heat shrink” some or all of the DT, stabilizing the tape so as to hold the amount of expansion initiated during STEP 700g.
Other conventional post-singulation steps may be applied as well, such as dicing tape adhesion release (e.g., with UV light) and die picking.
By combining front-side ablative laser scribed cuts and aligned modified layers created through the backside of a wafer substrate by an IR stealth dicing laser, approximately 90-100% wafer substrate utilization can be achieved, even with MPWs. Using the example of
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion. It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
