Patent Application
20230377913
Integrated circuits comprising semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. A series of chemical and physical processes may be performed during the fabrication process flow, using equipment with processing chambers that are often maintained at low pressure or partial vacuum.
The integrated circuit industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area, thereby lowering the cost of integrated circuits. Maintaining a continual reduction in manufacturing cost requires a high efficiency integrated circuit fabrication facility and infrastructure that may give rise to additional problems that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments eliminate potential contamination from condensation which can develop after an ion cryo-implantation process. The cryo-implantation process is performed under heavy vacuum while a lesser vacuum is maintained in the incoming and outgoing load locks of the implantation system. Rather than heat the wafers back to a target post-processing temperature in the outgoing load lock where condensation can form on the implanted wafers when subjected to the lesser vacuum level, the wafers are heated back to the target post-processing temperature in a heating stage which is attached to the implantation system and has the same vacuum as the implantation system. As a result, contamination which can result from condensation is eliminated or reduced and wafer-to-wafer consistency and stability is increased.
The ion source 130 produces an ion beam from a selected species for implantation. The selected species may be any desired element or compound which is suitable for a particular purpose. For example, the species may be a p-type species, including boron, indium, gallium, fluoroboron (e.g., difluoroboron), and so forth, an n-type species, such as phosphorous, arsenic, antimony, phosphyne (e.g., diphosphyne), and so forth, or a conductively neutral species, such as nitrogen, carbon, fluorine, and so forth. The species is directed towards the mass analysis magnet in order to electromagnetically separate those ions having a desired charge-to-mass ratio for implantation from those ions having an undesired charge-to-mass ratio. Once a coherent ion beam of suitable charge-to-mass ratio is obtained, the coherent ion beam 125 is sent to the linear accelerator.
The linear accelerator is used to impart additional energy to the coherent ion beam 125 as it passes through the linear accelerator. The linear accelerator imparts this additional energy using a series of electrodes that generate an electromagnetic field which, when the coherent ion beam 125 passes through the field, works to accelerate the coherent ion beam 125. The linear accelerator may vary the electromagnetic fields periodically with time or may adjust the phase of the electromagnetic fields to accommodate ions with different atomic numbers as well as ions having different initial speeds.
After the coherent ion beam 125 is passed through the linear accelerator, the coherent ion beam 125 is passed through the converging unit, which is utilized to modify the convergence and divergence of the coherent ion beam 125 (which arrives from the linear accelerator as a substantially parallel beam). The converging unit may include one or more lenses or apertures to focus or spread the coherent ion beam 125 according to a desired implantation process. The coherent ion beam 125 may then be directed to the end unit, including the wafer handling unit 140, and a wafer 142 provided in the wafer handling unit 140. The coherent ion beam 125 may be directed to a desired implantation location of the wafer 142, including a portion of the wafer 142, or the entire wafer 142. The wafer handling unit 140 may be utilized to move the wafer 142 in relation to the coherent ion beam 125 so as to illuminate different implantation areas of the wafer 142 with the coherent ion beam 125 and/or to hold the wafer 142 at various angles to the coherent ion beam 125 so as to provide an angled implantation of ions into the wafer 142. For example, the wafer handling unit 140 may include motors which may be used to control the position of the wafer 142 in at least two directions, such as an x-direction and a y-direction, relative to the coherent ion beam 125.
The wafer handling unit 140 may include an implantation platen having an electrostatic chuck to securely hold the wafer 142 during implantation. In addition, the wafer handling unit 140 may include cooling features to keep the wafer 142 cold during the implantation process. For example, in some embodiments, the wafer handling unit 140 may keep the wafer 142 at a temperature between −100° C. and about −30° C., such as about −60° C.
The wafer implantation apparatus 100 includes a robot 150 which may include an articulated arm 152 and wafer transfer mechanism 154. The robot 150 can move wafers, such as wafer 142, within the wafer implantation apparatus 100 from station to station. Such stations include the wafer handling unit 140, an incoming load lock 160, cooling stage 170, heating stage 180, and an outgoing load lock 190.
The incoming load lock 160 is separated from the processing chamber no by a slit valve 155. The slit valve 155 allows the robot 150 to access wafers positioned in the incoming load lock 160 while keeping the atmosphere of the processing chamber no separate from the atmosphere of the incoming load lock 160. The slit valve 155 may be opened to retrieve a wafer and may be in a closed state before and after the wafer is being retrieved. The slit valve 155 allows for two different vacuum levels to be maintained between the incoming load lock 160 and the processing chamber no. In some embodiments, the incoming load lock 160 may hold a plurality of wafers for ion implantation. For example, the incoming load lock 160 may include a wafer holder (or wafer boat) which includes between one and twenty-six wafer slots, though any number of wafer slots is contemplated and may be used.
The cooling stage 170 may include a platform for holding a wafer and cooling the wafer to the desired implantation temperature prior to performing the implantation. The cooling stage 170 is attached to the processing chamber 110 and maintained at the same vacuum as the processing chamber no. In other words, there is no valve between the processing chamber no and the cooling stage 170.
After implantation, the heating stage 180 is used to heat the wafer to room temperature or to the ambient temperature of the outgoing load lock 190. The heating stage 180 may include a platform for holding a wafer and heating the wafer to the desired temperature after performing the implantation. The heating stage 180 is attached to the processing chamber no and maintained at the same vacuum as the processing chamber no. In some embodiments, there is no valve between the processing chamber no and the heating stage 180. In other embodiments, a slit valve may be between the processing chamber no and the heating stage 180, such as the valve 175 illustrated in
After a wafer is heated on the heating stage 180, the wafer can be transferred to the outgoing load lock 190. A slit valve 185 may separate the outgoing load lock 190 from the processing chamber no. The slit valve 185 allows the robot 150 to provide processed wafers into the outgoing load lock 190. The slit valve 185 may be opened to transfer a wafer from the processing chamber no to the outgoing load lock 190 and may be closed before and after the wafer is being transferred. The slit valve 185 allows for two different vacuum levels to be maintained between the outgoing load lock 190 and the processing chamber no. In some embodiments, the outgoing load lock 190 may hold a plurality of wafers after ion implantation. For example, the outgoing load lock 190 may include a wafer holder (or wafer boat) which includes between one and thirty wafer slots, though any number of wafer slots is contemplated and may be used. The incoming load lock 160 and outgoing load lock 190 may hold the same number of wafers or a different number of wafers.
The heating process advantageously brings the wafer 142 up to the ambient temperature of the outgoing load lock 190 while under the heavy vacuum of the processing chamber no. Rather than heat the wafer 142 in the outgoing load lock under the lighter vacuum level, heating the wafer 142 under the heavy (and same) vacuum of the processing chamber no substantially eliminates condensation from forming on the surface of the wafer 142. Condensation forms when moisture in the air condenses on an element in the environment which is colder than the surrounding elements and colder than the condensation point of the moisture. For example, if the ambient temperature of an environment is 25° C. and the pressure is between 1e−4 torr and 1e−3 torr, the condensation point is greater than the working temperature of the wafer for cryo implantation, causing condensation to form on the surface of the wafer. For example, the working temperature of the wafer may be about −60° C., while the condensation temperature at a pressure of about 1e−4 torr may be between −60° C. and −40° C. Condensation will therefore form on any object in the environment that has a surface temperature less than the condensation temperature.
To prevent condensation from forming on the wafer 142 during ion implantation when the wafer 142 is at −60° C., it is under the heavy vacuum provided by the cryo vacuum pumps 210. As a result of the heavy vacuum, the moisture content in the processing chamber no is substantially zero, driving the condensation temperature in the processing chamber to below −100° C., such as between about −150° C. to about −170° C., such as about −160° C. But, if the wafer were to be transferred to the lower vacuum (higher pressure) outgoing load lock 190 while still cold (at or near implantation temperature) and then warmed in the outgoing load lock 190, the moisture in the outgoing load lock 190 (which is held at a lesser vacuum level) would condense onto the wafer 142. In particular, the condensation temperature in the outgoing load lock 190 may be between about −60° C. and about −40° C. while the outgoing load lock 190 pressure is between about 10−4 and 10−3 torr. When the outgoing load lock 190 is vented and the pressure returns to 1 atm, the condensation temperature is about 0° C. In either case, one or more wafers in the outgoing load lock 190 may have condensation form because the condensation temperature is greater than the working implantation temperature. This resulting condensation may react with certain implanted species and may also attract particles to adhere to the front side of the wafer. For example, where phosphorous is implanted, condensation water may react with the phosphorous to produce phosphorous pentoxide (10H2O+P4→P4O10+10H2). The condensation may also attract particulate materials to stick to the wafer 142.
At process 320, the wafer 142 is transferred to the cooling stage 170 to pre-cool the wafer 142 to the target implantation temperature. At process 330, the wafer is cooled to the target implantation temperature which is a deep freezing level between −100° C. and −30° C., such as about −60° C. A cryo implantation of ions at deep freezing levels is an effective tool to enhance device performance. The cooling may be accomplished by placing the wafer on a cooling platform and circulating a cryogenic liquid through the cooling platform. Such cryogenic liquids include, for example, liquid argon, liquid helium, liquid hydrogen, liquid nitrogen, and liquid oxygen. In some embodiments, a cryogenic liquid may also or instead be sprayed onto the wafer 142. The wafer 142 may be placed on the cooling platform and cooled for a duration between about 60 sec and about 180 sec. Once the wafer 142 reaches the implantation temperature, the cooling platform may maintain the wafer 142 at the implantation temperature until the wafer 142 is moved to the wafer handling unit 140 for implantation.
At process 340, the wafer is transferred to the implantation platen of the wafer handling unit 140. At process 350, the wafer 142 is implanted with ions using an implantation process. The purpose for the implantation process may be for any suitable purpose. For example, the implantation process may be used to form amorphous regions in a crystalline structure or provide doped areas of a semiconductor substrate or other regions, such as ultra-shallow junctions, doped wells, or source/drain regions, though these are not intended to be limiting. The implantation process may target the entire wafer 142 or particular regions of the wafer 142 using lenses, masks, reticles, or the like. The implantation platen of the wafer handling unit 140 may include cooling features, such as a circulation system to circulate a cryogenic liquid, to keep the wafer 142 at the target implantation temperature during the implantation process. The implantation process may have a duration between about 120 sec and about 240 sec, though other values are contemplated and may be used.
At process 360, the wafer 142 is transferred to the heating stage 180 through an opening 186 between the heating stage 180 and the processing chamber 110. At process 370, the wafer 142 is heated to a target temperature. In some embodiments, the target temperature may be the same as the ambient temperature of the processing chamber 110 or the ambient temperature of the outgoing load locks 190. In some embodiments, the target temperature may be greater than the condensation temperature of the outgoing load locks 190, but less than an annealing temperature which would activate implanted dopants or recrystallize amorphous regions of the implanted regions. In some embodiments, the target temperature may be between about 20° C. and about 50° C. In some embodiments, the ambient temperature of the outgoing load locks 190 may be about room temperature, and may be between about 20° C. and 27° C. The wafer 142 may be heated by applying heat to the wafer through the heater 184 poised over the wafer 142 and/or through heating elements 187 disposed in the platform 182 of the heating stage 180. The wafer 142 may be placed on the platform 182 and heated for a duration between about 10 sec and about 30 sec. Once the wafer 142 reaches the target temperature, the platform 182 and heater 184 may maintain the wafer 142 at the target temperature until the wafer 142 is moved to the outgoing load lock 190.
At process 380, the wafer 142 is transferred to the outgoing load lock 190. The robot 150 provides the wafer 142 through the slit valve 185 to a wafer boat in the outgoing load lock 190 which may be unloaded by another robot outside the wafer implantation apparatus 100. The slit valve 185 allows for the vacuum level in the processing chamber no to be minimally influenced by the different vacuum level in the outgoing load lock 190 by reducing the amount of pressure leakage from the higher pressure (lower vacuum) outgoing load lock 190 to the lower pressure (higher vacuum) processing chamber 110.
Wafer W1, at time t1, is in the incoming load lock 160. At time t2, wafer W1 is transferred by the robot 150 into the cooling stage 170. At time t3, wafer W1 is cooled in the cooling stage 170 and wafer W2 is in the incoming load lock 160. At time t4, wafer W1 is transferred by the robot 150 to the wafer handling unit 140 and wafer W2 is transferred by the robot 150 to the cooling stage 170. At time t5, wafer W1 is implanted with ions at the wafer handling unit 140, wafer W2 is cooled in the cooling stage 170, and wafer W3 is in the incoming load locks 160. At time t6, wafer W1 is transferred by the robot 150 to the heating stage 180, wafer W2 is transferred by the robot 150 to the wafer handling unit 140, and wafer W3 is transferred by the robot to the cooling stage 170. At time t7, wafer W1 is heated in the heating stage 180, wafer W2 is implanted with ions at the wafer handling unit 140, wafer W3 is cooled in the cooling stage 170, and wafer W4 is in the incoming load lock 160. At time t8, wafer W1 is transferred by the robot 150 to the outgoing load lock 190, wafer W2 is transferred by the robot 150 to the heating stage 180, wafer W3 is transferred by the robot 150 to the wafer handling unit 140, and wafer W4 is transferred by the robot 150 to the cooling stage 170. At time t9 wafer W1 is in the outgoing load lock 190 (and may be removed from the outgoing load lock by another external process/robot), wafer W2 is heated in the heating stage 180, wafer W3 is implanted with ions at the wafer handling unit 140, wafer W4 is cooled in the cooling stage 170, and wafer W5 is in the incoming load lock 160. This process continues on until all the wafers are processed.
As noted in
In some embodiments, the substrate 600 may include a crystalline silicon substrate (e.g., wafer). The substrate 600 may be a p-type substrate, that is, substrate 600 may be doped with p-type dopants or an n-type substrate doped with n-type dopants. The implantation regions 630 may correspond to additional doped wells which are doped with ions of n-type or p-type dopants forming well regions comprising n-type doped wells and p-type doped wells depending on design requirements. In some embodiments, the substrate 600 may be a silicon on insulator (SOI) substrate. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 600 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.
The example of
In
In
Embodiments advantageously utilize a new heating stage attached to the implantation processing chamber which is maintained at the same vacuum level of the processing chamber while the outgoing load lock is at a lesser vacuum level (higher pressure). By heating one wafer at a time in the heating stage, condensation is eliminated or substantially reduced, thereby eliminating potential contamination from condensation. As a result, wafer-to-wafer consistency is improved.
One embodiment is an apparatus including a first load lock, a processing chamber, and a second load lock. The first load lock is configured to be maintained at a first pressure. The processing chamber includes: a cooling stage, the cooling stage configured to cool a wafer to a first temperature prior to ion implantation, the first temperature corresponding to a cryogenic temperature; an implantation platen, the implantation platen configured to retain the wafer during an ion implantation process; and a heating stage, the heating stage configured to heat the wafer after implantation to a second temperature. The second load lock is configured to be maintained at the first pressure, where the processing chamber is configured to be maintained at a second pressure lower than the first pressure. In an embodiment, the heating stage and the implantation platen are in a continuous vacuum space, where a first vacuum level surrounding the implantation platen and a second vacuum level surrounding the heating stage are the same. In an embodiment, the processing chamber includes a first vacuum pump of a first type, where the first load lock includes a second vacuum pump of a second type different than the first type. In an embodiment, the heating stage includes: an overhead electric heater, a heated platform, or a combination thereof. In an embodiment, the implantation platen is disposed in a first subchamber of the processing chamber, where the heating stage is disposed in a second subchamber of the processing chamber, and where the second subchamber is attached to a wall of the first subchamber. In an embodiment, the second subchamber includes a cryo pump attached to the second subchamber. In an embodiment, the apparatus further includes: a robot configured to move the wafer from the first load lock to the cooling stage, to move the wafer from the cooling stage to the implantation platen, to move the wafer from the implantation platen to the heating stage, and to move the wafer from the heating stage to the second load lock. In an embodiment, the apparatus further including two or more cryo pumps for providing a first vacuum level between 100 and 1000 times greater than a second vacuum level of the second load lock. In an embodiment, the second temperature is within 10° C. of a temperature of the second load lock.
Another embodiment is a method including retrieving a wafer from a first load lock. The method also includes moving the wafer to a cooling stage. The method also includes pre-cooling the wafer to an implantation temperature, the implantation temperature being between −100° C. and −30° C. The method also includes moving the wafer to an implantation platen. The method also includes implanting ions into the wafer. The method also includes moving the wafer to a heating stage. The method also includes heating the wafer to a target temperature. The method also includes moving the wafer to a second load lock, where the first load lock and the second load lock are maintained at a first pressure, where the cooling stage, implantation platen, and heating stage, are maintained at a second pressure, where the second pressure is less than the first pressure. In an embodiment, the target temperature corresponds to an ambient temperature of the second load lock. In an embodiment, heating the wafer includes applying heat to the wafer by an overhead heater, a heated platform, or a combination thereof. In an embodiment, following implanting the ions, the wafer is moved to the heating stage without breaking vacuum of the second pressure. In an embodiment, moving the wafer to the second load lock includes passing the wafer through a valve disposed between a processing chamber housing the implantation platen and the second load lock. In an embodiment, moving the wafer to the heating stage includes passing the wafer through an opening in a sidewall of the processing chamber.
Another embodiment is a method including implanting ions into a first wafer on an implantation platen, where the first wafer has an implantation temperature between −100° C. and −30° C. during implantation. The method also includes heating the first wafer under a first vacuum on a heating stage to a target temperature between 20° C. and 50° C. The method also includes transferring the first wafer to an outgoing load lock, where the outgoing load lock is under a second vacuum, where during transferring the first wafer is free of condensation, where a first pressure level of the first vacuum is 100 to 1000 times less than a second pressure level of the second vacuum. In an embodiment, prior to implanting ions into the first wafer, first wafer is pre-cooled to the implantation temperature in a pre-cooling stage. In an embodiment, while heating the first wafer, ions are implanted into a second wafer on the implantation platen and pre-cooling a third wafer in the pre-cooling stage. In an embodiment, an ambient temperature of the outgoing load lock is within 10° C. of the target temperature. In an embodiment, the implantation platen is under a third vacuum, where a third pressure level of the third vacuum is approximate to the first vacuum.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application is a divisional of U.S. application Ser. No. 16/934,762, filed on Jul. 21, 2020, which application is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16934762 | Jul 2020 | US |
| Child | 18364588 | US |
