The present disclosure relates to semiconductor devices, and in particular to wide bandgap semiconductor devices having high channel packing density that maintain a high blocking voltage and low on-state resistance.
Wide bandgap semiconductor devices are preferred for a variety of applications due to their ability to withstand high blocking voltages, provide low on-state resistance, and operate at higher frequencies and temperatures than their narrow bandgap counterparts. Those skilled in the art will appreciate that the significant advantages offered by wide bandgap semiconductor devices in some aspects of operation often come at the expense of disadvantages in other aspects of operation. One such disadvantage is that wide bandgap semiconductor devices suffer from very concentrated electric fields forming therein. These concentrated electric fields may cause damage to the device if they are not properly managed, and further may reduce the ability of wide bandgap semiconductor devices to block voltages above a certain level without failure. Accordingly, there is a need for wide bandgap semiconductor devices that reduce the concentration of electric fields therein.
In one embodiment, a metal-oxide-semiconductor field-effect transistor (MOSFET) includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the wide bandgap drift layer, and a junction field-effect transistor (JFET) region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region. By separating the JFET region into the first JFET sub-region and the second JFET sub-region, the trade-off between on-state resistance, blocking voltage, and peak electric field may be designed locally for the sub-regions, thereby improving the overall performance of the MOSFET device.
In one embodiment, the JFET gap within the first JFET sub-region is different than the JFET gap within the second JFET sub-region. In particular, the JFET gap within the first JFET sub-region may be smaller than the JFET gap within the second JFET sub-region. The doping concentration within the first JFET sub-region may be greater than the doping concentration within the second JFET sub-region. The doping concentration in the JFET region may vary in a linear, exponential, or step-wise manner between the first JFET sub-region and the second JFET sub-region.
In one embodiment, the MOSFET device provides an area normalized on-state resistance less than 2 mΩ-cm2 and is capable of blocking at least 650 V. The MOSFET device may have a MOS channel packing density greater than 370 mm/mm2.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As shown in
While the MOSFET cell 10 is shown in
While there are many design parameters of a MOSFET device that may affect the performance thereof, two of these design parameters are particularly notable with respect to the disclosure discussed herein. The first notable design parameter of the MOSFET cell 10 is the distance between the junction implants 18, or the JFET gap 26. Increasing the JFET gap 26 will decrease the on-state resistance of the MOSFET cell 10, but will also decrease the blocking voltage thereof. Further, increasing the JFET gap 26 will generally increase the peak electric field at a center of the JFET region 24. Decreasing the JFET gap 26 will increase the blocking voltage of the MOSFET cell 10, but will also increase the on-state resistance thereof. Further, decreasing the JFET gap 26 will generally decrease the peak electric field at the center of the JFET region 24. The second notable design parameter of the MOSFET cell 10 is the doping concentration of the JFET region 24. Increasing the doping concentration of the JFET region 24 will decrease the on-state resistance of the MOSFET cell 10, but will also increase the peak electric field at a center of the JFET region 24. Decreasing the doping concentration of the JFET region 24 will decrease the peak electric field at the center of the JFET region 24, but will also increase the on-state resistance of the MOSFET cell 10. Accordingly, both the JFET gap 26 and the doping concentration of the JFET region 24 must be appropriately chosen to meet a desired blocking voltage, on-state resistance, and peak electric field for the MOSFET cell 10. Notably, if the peak electric field at the center of the JFET region 24 becomes too high, it will rupture the gate oxide and destroy the MOSFET cell 10. As discussed above, the concentration of electric fields is especially problematic in wide bandgap material systems such as silicon carbide (SiC) devices, which generally have much higher electric fields than their narrow bandgap counterparts. In designing the MOSFET cell 10, the JFET gap 26 and doping concentration for the JFET region 24 are thus chosen to provide a desired relationship between on-state resistance, blocking voltage, and peak electric field.
Notably, the MOSFET cell 10 is so named because it is the smallest unit of a larger MOSFET device. A MOSFET device includes hundreds or thousands of MOSFET cells repeated in various geometric configurations. The MOSFET cell 10 shown in
The above is best visualized by viewing a MOSFET device from the top-down. Accordingly,
As discussed above, two notable design parameters of the MOSFET device 36 are a JFET gap 42 and the doping concentration of the JFET region 40. Choosing these parameters for the MOSFET device 36 such as the one described with respect to
As discussed above, increasing the JFET gap 50 increases a peak electric field at the center of the JFET region 48. Due to a relatively large second JFET gap 50B in the MOSFET device 44, the most concentrated electric field in the device forms around a center point of the second JFET gap 50B. Conventionally, the JFET region 48 has been a uniformly doped region. According to conventional design principles, the doping concentration of the JFET region 48 is adjusted to accommodate for the most concentrated electric field in the MOSFET device 44, which forms at the center point between junction implants 46 that are adjacent but do not have parallel faces. In particular, the doping concentration of the JFET region 48 is lowered to reduce the peak electric field in this area to an acceptable level to avoid damaging the MOSFET device 44 (e.g., by rupturing the gate oxide thereof).
Notably, the doping concentration necessary to reduce the peak electric field to an acceptable level in the portion of the JFET region 48 between the junction implants 46 that are adjacent but do not have parallel faces is significantly lower than the doping concentration necessary to reduce the peak electric field to an acceptable level in the portion of the JFET region 48 between junction implants 46 that are adjacent and have parallel faces. When the doping concentration of the JFET region 48 is uniform in the MOSFET device 44, only the areas of the MOSFET device 44 where the junction implants 46 are separated by the second JFET gap 50B are optimized for, since this is the portion of the device that the doping concentration of the JFET region 48 is chosen for. In other words, the uniform doping concentration of the JFET region 48 results in a sub-optimal tradeoff between on-state resistance, blocking voltage, and peak electric field in the areas of the MOSFET device 44 where the junction implants 46 are separated by the first JFET gap 50A. When using wide bandgap material systems such as SiC, conventional designs in which the JFET region 48 is uniformly doped preclude the MOSFET device 44 from achieving certain combinations of on-state resistance and blocking voltage because they are not achievable when the doping concentration of the JFET region 48 is lowered to a level at which damage to the device due to the peak electric field in the areas of the MOSFET device 44 where the junction implants 46 are separated by the second JFET gap 50B will no longer occur.
Accordingly,
Separating the JFET region 48 into the first JFET sub-region 48A and the second JFET sub-region 48B allows the trade-offs that occur between on-state resistance, blocking voltage, and peak electric field to be locally optimized within different parts of the MOSFET device 44. While only the first JFET sub-region 48A and the second JFET sub-region 48B are shown in
The principles of the present disclosure similarly apply to a MOSFET device 52 including a number of junction implants 54 arranged in a hexagonal cell configuration as shown in
As discussed above, conventional design principles in which the JFET region 56 is uniformly doped require lowering the doping concentration of the entire JFET region 56 in order to prevent the peak electric field in the second JFET sub-region 56B from damaging the MOSFET device 52. The resulting doping concentration of the JFET region 56 makes certain combinations of on-state resistance and blocking voltages impossible to achieve, especially when the MOSFET device 52 uses a wide bandgap material system such as SiC. Accordingly, the first JFET sub-region 56A has a doping concentration that is greater than a doping concentration of the second JFET sub-region 56B. In one embodiment, the doping concentration of the first JFET sub-region 56A is between 1×1016 cm−3 and 2×1017 cm−3, and the doping concentration of the second JFET sub-region 56B is between 1×1015 cm−3 and 5×1016 cm−3. In various embodiments, the doping concentration of the first JFET sub-region 56A may be between 2×1016 cm−3 and 2×1017 cm−3, between 3×1016 cm−3 and 2×1017 cm−3, between 4×1016 cm−3 and 2×1017 cm−3, between 5×1016 cm−3 and 2×1017 cm−3, between 6×1016 cm−3 and 2×1017 cm−3, between 7×1016 cm−3 and 2×1017 cm−3, between 8×1016 cm−3 and 2×1017 cm−3, between 9×1016 cm−3 and 2×1017 cm−3, between 1×1017 cm−3 and 2×1017 cm−3, between 2×1016 cm−3 and 1×1017 cm−3, between 2×1016 cm−3 and 9×1016 cm−3, between 2×1016 cm−3 and 8×1016 cm−3, between 2×1016 cm−3 and 7×1016 cm−3, between 2×1016 cm−3 and 6×1016 cm−3, between 2×1016 cm−3 and 5×1016 cm−3, between 2×1016 cm−3 and 4×1016 cm−3, and between 2×1016 cm−3 and 3×1016 cm−3. The doping concentration of the second JFET sub-region 56B may be between 2×1015 cm−3 and 5×1016, between 3×1015 cm−3 and 5×1016, between 4×1015 cm−3 and 5×1016, between 5×1015 cm−3 and 5×1016, between 6×1015 cm−3 and 5×1016, between 7×1015 cm−3 and 5×1016, between 8×1015 cm−3 and 5×1016, between 9×1015 cm−3 and 5×1016, between 1×1016 cm−3 and 5×1016, between 2×1016 cm−3 and 5×1016, between 3×1016 cm−3 and 5×1016, between 4×1016 cm−3 and 5×1016, between 2×1015 cm−3 and 4×1016, between 2×1015 cm−3 and 3×1016, between 2×1015 cm−3 and 2×1016, between 2×1015 cm−3 and 1×1016, between 2×1015 cm−3 and 9×1015, between 2×1015 cm−3 and 8×1015, between 2×1015 cm−3 and 7×1015, between 2×1015 cm−3 and 6×1015, between 2×1015 cm−3 and 5×1015, between 2×1015 cm−3 and 4×1015, between 2×1015 cm−3 and 3×1015. The doping concentration in the JFET region 56 may transition abruptly between the first JFET sub-region 56A and the second JFET sub-region 56B, or may transition gradually in a linear, exponential, step-wise, or any other manner. That is, the JFET region 56 may have a graded doping concentration (in the lateral direction, or both the lateral and vertical direction) such that transitions between the first JFET sub-region 56A and the second JFET sub-region 56B occur in a linear, exponential, step-wise, or any other manner. The doping concentration of the first JFET sub-region 56A and the second JFET sub-region 56B, as well as the transitions therebetween, may be obtained using masking before ion implantation of the sub-regions. The masking may require several steps, which may be reduced by using greyscale or pinhole masking.
As discussed above separating the JFET region 56 into the first JFET sub-region 56A and the second JFET sub-region 56B allows the trade-offs that occur between on-state resistance, blocking voltage, and peak electric field to be locally optimized within different parts of the MOSFET device 52. While only a first JFET sub-region 56A and a second JFET sub-region 56B are shown in
While discussed above with respect to rectangular and hexagonal cell designs, the principles of the present disclosure apply equally to any MOSFET device wherein the JFET gap is not uniform throughout the device. That is, the present disclosure may be applied to MOSET devices having cells of any shape or size.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Number | Name | Date | Kind |
---|---|---|---|
6207993 | Ishimura et al. | Mar 2001 | B1 |
8217448 | Stefanov | Jul 2012 | B2 |
20110095305 | Yamashita | Apr 2011 | A1 |
20170338313 | Bolotnikov et al. | Nov 2017 | A1 |
Number | Date | Country |
---|---|---|
H05299658 | Nov 1993 | JP |
2001144102 | May 2001 | JP |
2008004872 | Jan 2008 | JP |
Entry |
---|
International Search Report and Written Opinion for International Patent Application No. PCT/US2019/040712, dated Oct. 11, 2019, 16 pages. |
International Preliminary Report on Patentability for International Patent Application No. PCT/US2019/040712, dated Jan. 28, 2021, 10 pages. |
Number | Date | Country | |
---|---|---|---|
20200020793 A1 | Jan 2020 | US |