WIRING BODY, MOUNTING SUBSTRATE, WIRING-EQUIPPED WIRING TRANSFER PLATE, WIRING BODY INTERMEDIATE MATERIAL, METHOD FOR MANUFACTURING WIRING BODY, AND METHOD FOR MANUFACTURING MOUNTING SUBSTRATE

TECHNICAL FIELD

The present disclosure relates to a wiring body, a mounting substrate, a wiring-equipped wiring transfer plate, a wiring body intermediate material, a method for manufacturing a wiring body, and a method for manufacturing a mounting substrate, and in particular, to a wiring body or the like that can be used as a wiring layer or a redistribution layer (RDL) of a mounting substrate such as a semiconductor package substrate.

BACKGROUND ART

The demand for smaller, more highly integrated, and more sophisticated semiconductor devices has led to a variety of packaging techniques for semiconductor devices. In recent years, 2.5D semiconductor packages, in which a silicon interposer provided with a plurality of semiconductor devices of different types is mounted on a semiconductor package substrate, have become the mainstream packaging technique for semiconductor devices. In 2.5D semiconductor packages, signal connections between the plurality of semiconductor devices are connected by fine circuits on the silicon interposer, and the entire silicon interposer can be regarded as a single “system on chip” (SoC) with integrated functions.

The silicon interposer includes a silicon wafer. In a silicon interposer, a fine multilayer wiring layer is formed by a semiconductor process on the front of the silicon wafer where the semiconductor devices are mounted, and connection terminals and electrical circuits that are connected to the semiconductor package substrate are formed on the rear of the silicon wafer, and the circuits on the front and rear are electrically connected by “through silicon vias” (TSVs) that penetrate the silicon wafer.

However, silicon interposers, which require wafer-level manufacturing processes, are expensive to manufacture. As a result, silicon interposers are often limited to applications in servers, high-end PCs, high-end graphics, etc., where performance is more important than cost, which is an obstacle to their widespread use.

In addition, since silicon is a semiconductor, forming the wiring layer directly on the silicon wafer results in degradation of electrical characteristics. Furthermore, when semiconductor devices are mounted on a semiconductor package substrate with a silicon interposer, compared to when semiconductor devices are mounted directly on the semiconductor package substrate, the transmission distance from the semiconductor package substrate is longer by the size of the silicon interposer, and noise is easily added.

2.1D semiconductor package substrates have been proposed as a new packaging technique that is less expensive than silicon interposer. A 2.1D semiconductor package substrate is an organic semiconductor package substrate that does not require a silicon interposer by making the multilayer wiring layer on the device mounting side of a conventional organic semiconductor package substrate have a wiring density similar to that of a silicon interposer (for example, see PTL 1).

However, 2.1D semiconductor package substrates present a challenge in that they require the formation of multiple layers of thin-layer fine wiring similar to silicon interposers. For example, 2.1D semiconductor package substrates require thin-layer fine wiring with an L/S of at least 2/2 μm to 5/5 μm and a wiring layer thickness of 3 μm to 10 μm per layer.

In such cases, to form fine wiring using conventional techniques, it is necessary to polish and planarize, by chemical mechanical polishing (CMP), one layer of wiring on the top surface layer of the semiconductor device mounting surface of a semiconductor package substrate manufactured using a normal process by. However, polishing and planarizing by CMP is expensive, and thus difficult to simply apply to the field of semiconductor package substrates.

The semi additive process (SAP) and the modified semi additive process (MSAP) are examples of known technologies for using a plating method to form fine wiring of L/S =2/2 μm to 5/5 μm on mounting substrates, such as semiconductor package substrates, including multilayer wiring layers. However, when fine wiring is formed by SAP or MSAP, the physical stress caused by the roller laminator or the like when thermo-compression bonding the film-like insulating resin, which serves as the interlayer insulating layer, frequently causes the wiring to peel off, making it difficult to manufacture fine wiring with high yield.

Moreover, when the line width of wiring is miniaturized to 2 μm to 5 μm, the thickness of the interlayer insulating layer needs to be reduced from the viewpoint of impedance and fabrication, but when film-like insulating resin is used, either there is no insulating resin with the appropriate thickness, or even if there is, it is difficult to laminate and thermocompress the thin film-like insulating resin.

In view of this, in order to make the thickness of the interlayer insulating layer uniform, the use of liquid insulating resin instead of a film-like insulating resin as the insulating material of the interlayer insulating layer has been considered, but in such cases, it is difficult to maintain a constant thickness of the interlayer insulating layer because the thickness of the interlayer insulating layer, which is formed by curing a liquid insulating resin, is affected by the unevenness of the via electrodes and wiring. In order to mitigate the effect of such unevenness of the via electrodes and wiring, it is conceivable to use filled-via plating, in which plating is selectively deposited as via electrodes and wiring, but it is difficult to form via electrodes and wiring simultaneously by smooth plating due to the diameter of the via electrodes (via holes), width and thickness of the wiring, thickness of the interlayer insulating layer, etc.

CITATION LIST
Patent Literature
[PTL 1] Japanese Unexamined Patent Application Publication No. 2020-107681
SUMMARY OF INVENTION
Technical Problem

Thus, regarding semiconductor package substrates in which wiring bodies including via electrodes and wiring are used, it is difficult to make the lines of wiring finer and disposed at a narrower pitch using conventional manufacturing techniques such as SAP or MSAP. In particular, since the line width of fine wiring is smaller than the diameter of the via electrodes, the bottom portion of the wiring may be undercut by over-etching when forming the wiring by etching, resulting in wiring defects.

The present disclosure was conceived to overcome such problems and has an object to provide, for example, a wiring body and a mounting substrate, including via electrodes and wiring, in which the lines of the wiring can be made finer and disposed at a narrower pitch.

Solution to Problem

In order to achieve the above object, in one aspect, a wiring body according to the present disclosure is disposed above a substrate including a conductor and includes: a via electrode provided in a via hole formed in an insulating layer on the substrate, the via electrode connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A lower layer included in the via electrode and located above the insulating layer and a lower layer included in the wiring include the same material.

In one aspect, a mounting substrate according to the present disclosure includes the wiring body and a substrate on which the wiring body is disposed.

In one aspect, a wiring-equipped wiring transfer plate according to the present disclosure is a wiring transfer plate on which transfer wiring to be transferred to another component is formed, and includes: a base; a release layer formed on the base; a transfer plate insulating layer covering the base with an opening above the release layer; a plating film formed on the release layer, in the opening; and an adhesion film formed to cover the plating film and the transfer plate insulating layer. The plating film and the adhesion film are transfer wiring to be transferred to another component.

In one aspect, a wiring body intermediate material according to the present disclosure is an intermediate material for a wiring body disposed above a substrate including a conductor, and includes: an adhesion film formed on an insulating layer provided on the substrate to cover the conductor; and wiring formed on the adhesion film.

In one aspect, according to the present disclosure, a method for manufacturing a wiring body disposed above a substrate including a conductor includes: disposing, on an insulating layer on the substrate, an adhesion film and a wiring body layer above the adhesion film; after disposing the adhesion film and the wiring body layer, forming a via hole in the insulating layer so as to expose the conductor by removing a portion of the adhesion film and a portion of the insulating layer; after forming the via hole, forming a seed film to cover the conductor that is exposed, the adhesion film, and the wiring body layer; after forming the seed film, selectively forming a resist on the seed film so as to expose a portion of the seed film covering the conductor; after selectively forming the resist, forming a via electrode body layer on the seed film that is exposed; and after forming the via electrode body layer and after removing the resist, removing the seed film that is exposed and the adhesion film under the seed film that is exposed.

In one aspect, according to the present disclosure, a method for manufacturing a mounting substrate including a wiring body disposed above a substrate includes disposing the wiring body on the substrate. The wiring body is manufactured by the above method.

Advantageous Effects of Invention

In, for example, a wiring body and a mounting substrate, including via electrodes and wiring, the lines of the wiring can be made finer and disposed at a narrower pitch.

Brief Description of Drawings

FIG. 1 is a plan view illustrating one example of the wiring pattern of one wiring layer in a wiring body of a mounting substrate according to Embodiment 1.

FIG. 2 is a cross-sectional view of wiring between vias on the mounting substrate taken at line II-II in FIG. 1.

FIG. 3 is a cross-sectional view of a connection between layers on the mounting substrate taken at line III-III in FIG. 1.

FIG. 4 is a diagram illustrating a method for fabricating a wiring-equipped wiring transfer plate used in manufacturing the wiring body and mounting substrate according to Embodiment 1.

FIG. 5 is a diagram illustrating a method for fabricating a wiring transfer plate.

FIG. 6A is a cross-sectional view of a variation of the wiring transfer plate.

FIG. 6B is a cross-sectional view of wiring between vias on a mounting substrate according to the variation.

FIG. 6C is a cross-sectional view of a connection between layers on a mounting substrate according to the variation.

FIG. 7 illustrates the configuration of the wiring-equipped wiring transfer plate fabricated in FIG. 4 when cut in a different cross-section.

FIG. 8 illustrates a method for manufacturing the wiring body and a method for manufacturing the mounting substrate according to Embodiment 1 (illustrates a cross-sectional view of the portion corresponding to the wiring between vias in FIG. 2).

FIG. 9 illustrates a method for manufacturing the wiring body and a method for manufacturing the mounting substrate according to Embodiment 1 (illustrates a cross-sectional view of the portion corresponding to the connection between layers in FIG. 3).

FIG. 10 illustrates a conventional method for manufacturing a mounting substrate including a via electrode and wiring.

FIG. 11 is a cross-sectional view of mounting substrate according to Embodiment 1, showing a first wiring body application example.

FIG. 12 is a cross-sectional view of mounting substrate according to Embodiment 1, showing a second wiring body application example.

FIG. 13 is a cross-sectional view of mounting substrate according to Embodiment 1, showing a third wiring body application example.

FIG. 14 is a cross-sectional view of a mounting substrate according to Embodiment 2.

FIG. 15 illustrates a method for manufacturing a wiring body and a method for manufacturing the mounting substrate according to Embodiment 2.

FIG. 16 is a cross-sectional view of a mounting substrate according to Embodiment 3.

FIG. 17 illustrates a method for manufacturing a wiring body and a method for manufacturing the mounting substrate according to Embodiment 3.

FIG. 18 is a cross-sectional view of a mounting substrate according to Embodiment 4.

FIG. 19 is a diagram illustrating another example of a method for manufacturing a wiring transfer plate.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The embodiments described below each illustrate one specific example of the present disclosure. The numerical values, shapes, materials, elements, the arrangement and connection of the elements, etc., shown in the following embodiments are mere examples, and therefore do not limit the scope of the present disclosure. Therefore, among the elements in the following embodiments, those not recited in any of the independent claims defining the broadest concept of the present disclosure are described as optional elements.

Note that the drawings are represented schematically and are not necessarily precise illustrations. Accordingly, the scale, etc., is not necessarily the same in each figure. Additionally, like reference signs indicate like elements. As such, overlapping descriptions of like elements are omitted or simplified.

Embodiment 1

First, the configurations of wiring body 30 and mounting substrate 1 according to Embodiment 1 will be described with reference to FIG. 1 through FIG. 3. FIG. 1 is a plan view illustrating one example of the wiring pattern of one wiring layer in wiring body of mounting substrate 1 according to Embodiment 1. FIG. 2 is a cross-sectional view of wiring between vias on mounting substrate 1 taken at line II-II in FIG. 1. FIG. 3 is a cross-sectional view of a connection between layers on mounting substrate 1 taken at line III-III in FIG. 1.

For example, mounting substrate 1 is a semiconductor package substrate, and includes a plurality of wiring layers in which wiring is formed. Therefore, as illustrated in FIG. 1, mounting substrate 1 includes, as wiring body 30, via electrodes 31 for electrically connecting the wiring between wiring layers, and wiring 32, which is the wiring in one of the wiring layers. Wiring 32 is connected to via electrodes 31. As illustrated in FIG. 1, via electrodes 31 are formed, for example, but not limited to, at the end of the portions where wiring 32 extends. For example, via electrodes 31 may be formed in the middle of wiring 32.

A plurality of via electrodes 31 and a plurality of lines of wiring 32 are formed in each wiring layer. As one example, mounting substrate 1 is a small, ultra-high-density mounting substrate densely provided with wiring 32. Wiring 32 is, for example, fine wiring characterized by L/S =5/5 μm or less. Wiring 32 is therefore formed in a complex wiring pattern so as to pass between two via electrodes 31. In such a configuration, the space between via electrodes (via pitch) is narrow, so lines of wiring 32 are formed at a narrow pitch such that lines of wiring 32 can pass through the narrow space between via electrodes.

As illustrated in FIG. 2 and FIG. 3, mounting substrate 1 includes substrate 10, and insulating layer 20 and wiring body 30 above substrate 10. As described above, wiring body 30 includes at least via electrode 31 and wiring 32 as conductive components. Note that insulating layer 20 may be included in wiring body 30.

Substrate 10 includes conductor 11. Conductor 11 is, for example, wiring or an electrode formed in a different wiring layer than wiring 32. As one example, substrate 10 is a wiring substrate, which is a wiring-equipped substrate including wiring formed with, for example, copper foil, such as a build-up substrate, a multilayer wiring substrate, a double-sided wiring substrate, or a single-sided wiring substrate. Substrate 10 therefore includes a plurality of lines of wiring, etc., as conductors 11 over a single or a plurality of layers. Note that in FIG. 2 and FIG. 3, among conductors 11 included in substrate 10, only conductors 11 formed on the top surface layer of substrate 10 are illustrated for schematic purposes.

In the present embodiment, mounting substrate 1 is an ultra-high-density mounting substrate, and a build-up substrate is used as substrate 10. Substrate 10 is not limited to a wiring substrate such as a build-up substrate, and may be an IC package substrate or an IC chip itself, as long as it includes wiring or electrodes, etc., as conductors 11.

Insulating layer 20 is formed on substrate 10. More specifically, insulating layer 20 covers the entirety of substrate 10 so as to cover conductors 11 on the surface layer of substrate 10.

Insulating layer 20 is disposed between conductors 11 of substrate 10 and wiring 32. Accordingly, insulating layer 20 is an interlayer insulating layer. More specifically, as illustrated in FIG. 2 and FIG. 3, if the wiring layer in which conductors 11, i.e., wiring of the surface layer of substrate 10 is formed is first wiring layer WL1 and the wiring layer in which wiring 32 of wiring body 30 is formed is second wiring layer WL2, insulating layer 20 is an interlayer insulating layer between first wiring layer WL1 and second wiring layer WL2.

Via hole 21 is formed in insulating layer 20. Via hole 21 is a through-hole formed above conductor 11 of substrate 10. Via electrode 31 is formed in via hole 21. Via hole 21 has a truncated cone shape with a sloping (tapered) inner surface. Accordingly, the shape of the opening (the top view shape) of via hole 21 is circular, and the cross-sectional shape of via hole 21 is trapezoidal. Note that via hole 21 may have a polygonal frustum shape, such as a square frustum shape, or a columnar or prismatic shape.

Insulating layer 20 includes an insulating material. The insulating material of insulating layer 20 is, for example, an insulating resin. In such cases, the insulating resin material used to form insulating layer 20 may be a liquid insulating resin material with flowability including a photo-curable resin such as a UV-curable resin or a thermosetting resin, or a prepreg of a film-like insulating resin including a thermosetting resin or a thermoplastic resin. An insulating resin sheet can be used as the film-like insulating resin. In such cases, the insulating resin sheet should have adhesive properties. Note that the insulating material of insulating layer 20 is not limited to organic insulating materials such as insulating resin, and may also be an inorganic insulating material such as silicon oxide film or silicon nitride film.

Wiring body 30 is disposed above substrate 10 including conductors 11. More specifically, via electrodes 31 of wiring body 30 are disposed on conductors 11 of substrate 10, and wiring 32 of wiring body 30 is located above substrate 10 with insulating layer 20 interposed therebetween. More specifically, wiring 32 is disposed on insulating layer 20. As illustrated in FIG. 2, wiring 32 is disposed above conductor 11 functioning as the wiring of substrate 10, with insulating layer 20 interposed therebetween.

As will be described in detail below, wiring 32 is formed on insulating layer 20 by a transfer method using a wiring transfer plate.

Note that all of wiring 32 need not be located above the main surface of insulating layer 20; the bottom portion of wiring 32 may be located within insulating layer 20.

Via electrode 31 is connected to conductor 11 of substrate 10 through via hole 21 in insulating layer 20. Via electrode 31 is a plug that connects the top and bottom wiring that sandwiches insulating layer 20. More specifically, via electrode 31 connects the wiring (conductor 11) of first wiring layer WL1 located directly below insulating layer 20 and the wiring (wiring 32) of second wiring layer

WL2 located directly above insulating layer 20.

Via electrode 31 is at least partially provided in via hole 21. More specifically, via electrode 31 is seamlessly embedded in via hole 21. Via electrode 31 is formed not only inside via hole 21, but also protrudes out from the main surface of insulating layer 20. The height of via electrode 31 from the main surface of insulating layer is higher than the height of wiring 32 from the main surface of insulating layer 20.

As illustrated in FIG. 2, in the present embodiment, via electrode 31 is formed over conductor 11 of substrate 10 and insulating layer 20. Stated differently, via electrode 31 is formed to ride up from the inside of via hole 21 in insulating layer 20 onto the main surface of insulating layer 20. Accordingly, the plan view surface area of the portion of via electrode 31 protruding out from insulating layer 20 is larger than the surface area of the maximum diameter portion of via electrode 31 embedded in via hole 21.

The shape of the portion of via electrode 31 embedded in via hole 21 is the same as the shape of via hole 21. Therefore, in the present embodiment, the portion of via electrode 31 embedded in via hole 21 has a truncated cone shape with a sloping (tapered) side surface. The minimum diameter of the portion of via electrode 31 embedded in via hole 21 is larger than the width of wiring 32.

Via electrode 31 includes seed layer 31a, via electrode body layer 31b provided on seed layer 31a, and adhesion layer 31c. Via electrode 31 further includes electroless plating layer 31d between adhesion layer 31c and seed layer 31a. However, electroless plating layer 31d may be omitted.

Seed layer 31a is formed on conductor 11 of substrate 10 in via hole 21. More specifically, seed layer 31a is formed on the top surface of conductor 11 so as to contact conductor 11. Seed layer 31a is formed along the inner side surface of insulating layer 20 from on top of conductor 11 in via hole 21.

In the present embodiment, seed layer 31a is formed up to a location above the main surface of insulating layer 20. Stated differently, seed layer 31a is formed over conductor 11 of substrate and the main surface of insulating layer 20. Seed layer 31a has a constant thickness. Accordingly, seed layer 31a is formed so as to ride up from conductor 11 in via hole 21 onto the main surface of insulating layer 20.

Seed layer 31a is a seed electrode including conductive material for forming via electrode body layer 31b by a plating method. Seed layer 31a should therefore include a conductive material with low electrical resistance. In the present embodiment, seed layer 31a is, for example, a metal film of a metallic material including, for example, copper, which is a low-resistance material. In such cases, seed layer 31a does not include only copper, and may include another metal such as nickel in addition to copper. Seed layer 31a may be a single film including only one metal film, or a multilayer film including a plurality of stacked metal films.

Via electrode body layer 31b is a plating film stacked on seed layer 31a. In the present embodiment, via electrode body layer 31b is an electrolytic plating film formed by an electrolytic plating method. More specifically, via electrode body layer 31b is an electrolytic Cu plating film including copper.

Via electrode body layer 31b is formed so as to be located above seed layer 31a and fill via hole 21. In the present embodiment, via electrode body layer 31b is formed up to a location above insulating layer 20. More specifically, via electrode body layer 31b is formed on seed layer 31a, over conductor 11 and insulating layer 20. Stated differently, via electrode body layer 31b is formed to ride up from the inside of via hole 21 in insulating layer 20 onto the main surface of insulating layer 20.

Via electrode body layer 31b constitutes the majority of via electrode 31. In the present embodiment, via electrode body layer 31b constitutes 90% or more of via electrode 31 in the cross-sectional view of FIG. 2.

Adhesion layer 31c is formed on insulating layer 20. More specifically, adhesion layer 31c is provided between the portion of seed layer 31a located above insulating layer 20, and insulating layer 20. In the present embodiment, adhesion layer 31c is the lower layer, of via electrode 31, that is located on insulating layer 20. Stated differently, in the portion of via electrode 31 located above insulating layer 20, adhesion layer 31c, electroless plating layer 31d, seed layer 31a, and via electrode body layer 31b are stacked on insulating layer in this order. In the portion of via electrode 31 located above insulating layer 20, adhesion layer 31c is the lowest layer of the portion of via electrode 31 located above insulating layer 20. Note that in the portion of via electrode 31 that is within via hole 21 of insulating layer 20, seed layer 31a is the lowest layer of via electrode 31.

Adhesion layer 31c (first adhesion layer) of via electrode 31 is formed in the same layer as adhesion layer 32a (second adhesion layer) of wiring 32 to be described later. Stated differently, adhesion layer 31c of via electrode 31 and adhesion layer 32a of wiring 32 include the same material and are formed in the same process.

Electroless plating layer 31d is an electroless plating film formed by an electroless plating method. More specifically, electroless plating layer 31d is an electroless Cu plating film including copper. Thus, in via electrode 31, both via electrode body layer 31b and electroless plating layer 31d are Cu plating films, but electroless plating layer 31d is an electroless Cu plating film while via electrode body layer 31b is an electrolytic Cu plating film. Accordingly, the crystal grain size of the copper included in via electrode body layer 31b and the crystal grain size of the copper included in electroless plating layer 31d are different. More specifically, the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film, is larger than the average crystal grain size of the copper included in electroless plating layer 31d, which is an electroless plating film. Stated differently, the average crystal grain size of the copper included in electroless plating layer 31d, which is an electroless plating film, is smaller than the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film.

Wiring 32 includes adhesion layer 32a provided as a lower layer in wiring 32 and wiring body layer 32b provided on adhesion layer 32a. In the present embodiment, adhesion layer 32a is the lowest layer of wiring 32. Adhesion layer 32a is provided on the main surface of insulating layer 20.

Wiring 32 further includes conductive layer 32c provided on wiring body layer 32b, and electroless plating layer 32d provided between adhesion layer 32a and wiring body layer 32b. Stated differently, wiring 32 has a stacked structure in which adhesion layer 32a, electroless plating layer 32d, wiring body layer 32b, and conductive layer 32c are stacked in this order in the direction leading away from insulating layer 20. The bottom portion of wiring body layer 32b has the same line width as adhesion layer 32a.

Adhesion layer 32a is provided to facilitate adhesion between wiring 32 and insulating layer 20. Stated differently, adhesion layer 32a has a function or structure for enhancing the adhesion between wiring 32 and insulating layer 20. In the present embodiment, adhesion layer 32a has, as a structure for enhancing the adhesion between wiring 32 and insulating layer 20, a fine-textured structure. Although the entire layer of adhesion layer 32a has a fine-textured structure, adhesion layer 32a is not limited to such a configuration;

when only a portion of adhesion layer 32a has a fine-textured structure, the fine-textured structure is formed on the side of adhesion layer 32a that faces insulating layer 20. In this way, by providing adhesion layer 32a with a fine-textured structure, adhesion layer 32a can more easily adhere to insulating layer 20 via an anchoring effect.

The fine-textured structure of adhesion layer 32a is, for example, a needle-like uneven shape with a height of 500 nm or less. As one example, adhesion layer 32a includes a metal film containing copper. In such cases, the fine-textured structure of adhesion layer 32a includes copper and/or copper oxide. More specifically, the fine-textured structure can be formed by roughening the copper surface by forming copper oxide with needle-like crystals. Instead of forming copper oxide, micro-roughening etching may be used to roughen the copper surface by slightly etching the surface to form a fine-textured structure. Note that adhesion layer 32a may include metallic elements other than copper.

As described above, adhesion layer 32a of wiring 32 and adhesion layer 31c of via electrode 31 are formed in the same layer. Stated differently, adhesion layer 32a, which is the lower layer in wiring 32, and adhesion layer 31c, which is the lower layer located above insulating layer 20 in via electrode 31, include the same material and have the same fine-textured structure. Note that adhesion layer 32a may be formed on electroless plating layer 32d.

Wiring body layer 32b is a plating film stacked below conductive layer 32c. In the present embodiment, wiring body layer 32b is an electroless plating film formed by an electroless plating method. More specifically, wiring body layer 32b is an electroless Cu plating film including copper.

Thus, wiring body layer 32b of wiring 32 and via electrode body layer 31b of via electrode 31 are both Cu plating films, but wiring body layer 32b is an electroless Cu plating film and via electrode body layer 31b is an electrolytic Cu plating film. Accordingly, the crystal grain size of the copper included in via electrode body layer 31b and the crystal grain size of the copper included in wiring body layer 32b are different. More specifically, the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film, is larger than the average crystal grain size of the copper included in wiring body layer 32b, which is an electroless plating film. Stated differently, the average crystal grain size of the copper included in wiring body layer 32b, which is an electroless plating film, is smaller than the average crystal grain size of the copper included in via electrode body layer 31b, which is an electrolytic Cu plating film.

Moreover, wiring body layer 32b of wiring 32 and via electrode body layer 31b of via electrode 31 are both plating films, but wiring 32 does not include a seed layer as a lower layer. Stated differently, via electrode 31 includes seed layer 31a as a lower layer, but wiring 32 does not include a seed layer as a lower layer.

Wiring body layer 32b of wiring 32 constitutes the majority of wiring 32. In the present embodiment, wiring body layer 32b constitutes 90% or more of wiring 32 in the cross-sectional view of FIG. 2.

Conductive layer 32c formed on top of wiring body layer 32b functions as part of the conductor of wiring 32 and as a protective layer that protects wiring body layer 32b. Stated differently, conductive layer 32c inhibits wiring body layer 32b from being etched and reduced when the seed film is etched and patterned to form seed layer 31a of via electrode 31. Stated differently, wiring body layer 32b can be protected by conductive layer 32c when etching the seed film. Thus, conductive layer 32c functions as a protective layer that protects wiring body layer 32b during etching.

Like wiring body layer 32b, conductive layer 32c is also an electroless plating film. However, conductive layer 32c includes a different material or structure than wiring body layer 32b. In the present embodiment, conductive layer 32c includes a different conductive material than wiring body layer 32b. More specifically, since wiring body layer 32b includes copper, conductive layer 32c includes a conductive material other than copper. For example, conductive layer 32c includes a material containing any of nickel (Ni), palladium (Pd), platinum (Pt), or silver (Ag). Stated differently, conductive layer 32c is an electroless plating film containing any of these materials.

Just like wiring body layer 32b, electroless plating layer 32d is an electroless plating film formed by an electroless plating method. More specifically, electroless plating layer 32d is an electroless Cu plating film including copper. However, the electroless plating film in wiring body layer 32b and the electroless plating film in electroless plating layer 32d are deposited in separate processes. The electroless plating film in wiring body layer 32b is the type that is selectively deposited on an electrode, and the electroless plating film in electroless plating layer 32d is the type that can be formed uniformly over the entire surface, even on the insulating layer. Next, the method for manufacturing wiring body 30 and the method for manufacturing mounting substrate 1 according to the present embodiment will be described with reference to FIG. 4 through FIG. 9. FIG. 4 is a diagram illustrating a method for fabricating wiring-equipped wiring transfer plate 200 used in manufacturing wiring body and mounting substrate 1 according to Embodiment 1. FIG. 5 is a diagram illustrating a method for fabricating wiring transfer plate 100. FIG. 6A is a cross-sectional view of a variation of the wiring transfer plate. FIG. 6B is a cross-sectional view of wiring between vias on a mounting substrate according to the variation. FIG. 6C is a cross-sectional view of a connection between layers on a mounting substrate according to the variation. FIG. 7 illustrates the configuration of wiring-equipped wiring transfer plate 200 fabricated in FIG. 4 when cut in a different cross-section. FIG. 8 and FIG. 9 illustrate the method for manufacturing wiring body 30 and the method for manufacturing mounting substrate 1 according to Embodiment 1. FIG. 8 illustrates the method for manufacturing the portion corresponding to the wiring between vias illustrated in FIG. 2, and FIG. 9 illustrates the method for manufacturing the portion corresponding to the connection between layers illustrated in FIG. 3.

In the present embodiment, wiring body 30 and mounting substrate 1 are fabricated using wiring transfer plate 100. Wiring transfer plate 100 is a wiring pattern plate for forming a predetermined pattern of wiring (transfer wiring) to be transferred to another component (transfer target component). More specifically, wiring transfer plate 100 according to the present embodiment is a pattern plate used in a plating process for forming an electroless plating film as the transfer wiring. The electroless plating film formed by wiring transfer plate 100 becomes at least part of the wiring that is transferred to another component.

Hereinafter, the method for manufacturing wiring body 30 and mounting substrate 1 using wiring transfer plate 100 will be described.

First, as illustrated in FIG. 4, wiring-equipped wiring transfer plate 200 is fabricated in advance using wiring transfer plate 100. Wiring-equipped wiring transfer plate 200 is equivalent to wiring transfer plate 100 on which transfer wiring is formed. In other words, wiring-equipped wiring transfer plate 200 is equivalent to wiring transfer plate 100 in a state in which transfer wiring is formed thereon. Transfer wiring 36 to be transferred to components included in mounting substrate 1 is formed on wiring-equipped wiring transfer plate 200 according to the present embodiment.

More specifically, as illustrated in (a) in FIG. 4, wiring transfer plate 100 is prepared. Wiring transfer plate 100 is fabricated in advance as illustrated in FIG. 5.

Next, the method for fabricating wiring transfer plate 100 will be described with reference to FIG. 5.

First, as illustrated in (a) in FIG. 5, a plating-base-material-equipped base, which includes plating base material layer 130 formed on base 110 that serves as a support substrate, is received. A rigid substrate such as a glass or metal substrate should be used as base 110. In the present embodiment, a SUS metal substrate is used as base 110. Plating base material layer 130 is a catalyst base material layer for forming an electroless plating film. One or more materials selected from nickel (Ni), palladium (Pd), platinum (Pt), chromium (Cr), iron (Fe), etc., can be used as the plating base material included in plating base material layer 130. As one example, plating base material layer 130 is a nickel film.

Then, as illustrated in (b) in FIG. 5, insulating layer 120, which is the transfer plate insulating layer, is formed on top of plating base material layer 130. For example, a photoresist can be used as insulating layer 120.

Then, as illustrated in (c) and (d) in FIG. 5, insulating layer 120, which is a photoresist, is exposed and developed to form a plurality of openings 121 in insulating layer 120 to expose plating base material layer 130. Stated differently, insulating layer 120 covers base 110 including openings 121 above plating base material layer 130.

Then, as illustrated in (e) in FIG. 5, baking is performed. This completes wiring transfer plate 100.

Note that in wiring transfer plate 100 fabricated in this way, plating base material layer 130 functions as a release layer, but a release treatment may be performed on plating base material layer 130 to provide additional releasing properties. To give plating base material layer 130 releasing properties is to weaken the catalytic reaction effect of plating base material layer 130. For example, plating base material layer 130 exposed from insulating layer 120 can be oxidized to give plating base material layer 130 releasing properties. The release treatment of plating base material layer 130 is not limited to oxidation.

Moreover, in FIG. 5, plating base material layer 130 is a continuous film, but plating base material layer 130 is not limited to this example. For example, as in wiring transfer plate 100A illustrated in FIG. 6A, plating base material layer 130 may be patterned and separated to form plating base material layer 130A per opening 121.

Next, using wiring transfer plate 100 fabricated in this way, wiring 32, which will be the transfer wiring, is formed on wiring transfer plate 100.

More specifically, first, as illustrated in (b) and (c) in FIG. 4, an electroless plating film (electroless plating layer) is formed on plating base material layer 130 by an electroless plating method. For example, an electroless plating film is formed on plating base material layer 130 in openings 121 of insulating layer 120 of wiring transfer plate 100 by depositing and growing metal by catalytic reaction of plating base material layer 130. Here, conductive layer 32c and wiring body layer 32b including different materials are stacked as an electroless plating film on top of plating base material layer 130. In such cases, in the present embodiment, since plating base material layer 130 is a nickel film, conductive layer 32c including an electroless Ni plating film, an electroless silver plating film, an electroless Pt plating film, or an electroless Pd plating film is formed on plating base material layer 130, and wiring body layer 32b including an electroless Cu plating film is stacked on conductive layer 32c. Conductive layer 32c is preferably an electroless plating film. By making conductive layer 32c an electroless plating film, conductive layer 32c can be formed thin and uniform in thickness. However, conductive layer 32c may be an electrolytic plating film instead of an electroless plating film.

Note that when conductive layer 32c is an electroless Ni film or an electroless silver plating film, since the electroless Ni film or the electroless silver plating film can be removed with almost no erosion of Cu when making the wiring body in a later process, the wiring body can be easily structured only of Cu. If electroless Ni film remains, there is concern that the wiring resistance of the wiring body will increase because the electroless Ni film generally includes substances such as boron and phosphorus, which have high resistance. There is also concern that the high-frequency characteristics, etc., will be degraded due to the electroless Ni film being magnetic. In addition, there is concern that reliability characteristics may be degraded because silver is a metal that is prone to ion migration. Therefore, if conductive layer 32c is an electroless Ni film or an electroless silver plating film, conductive layer 32c may be removed. In such cases, regarding wiring body 30A of the mounting substrate according to the variation where conductive layer 32c is removed, a cross-sectional view of wiring between vias in the mounting substrate corresponding to line II-II in FIG. 1 is illustrated in FIG. 6B, and a cross-sectional view of the connection between layers in the mounting substrate corresponding to line III-III in FIG. 1 is FIG. 6C. As illustrated in FIG. 6B, although conductive layer 32c will remain in the connection area between via electrode 31A and wiring 32A, if an electroless Ni film or an electroless silver plating film is used as conductive layer 32c, good connection characteristics can be obtained between seed layer 31a, which will be an electroless Cu film, and the electroless Ni film or the electroless silver plating film.

However, when conductive layer 32c is an electroless Pd film or an electroless Pt film, since the electroless Pd film or the electroless Pt film generally contains few impurities, the surface resistance of the wiring can be kept low, and it is also advantageous in regard to high-frequency characteristics because it is not magnetic. Moreover, the Pd or Pt included in the electroless Pd or the electroless Pt film is a stable metal compared to Cu, so it can also function as a barrier layer to inhibit ion migration.

As described in Embodiment 2 below, depending on the material of plating base material layer 130, it is possible to form only wiring body layer 32b including an electroless Cu plating film, without forming conductive layer 32c. Stated differently, at least wiring body layer 32b should be formed on plating base material layer 130. Conductive layer 32c is preferably an electroless plating film. By making conductive layer 32c an electroless plating film, conductive layer 32c can be formed uniform in thickness. However, conductive layer 32c may be an electrolytic plating film instead of an electroless plating film.

Next, as illustrated in (d) in FIG. 4, electroless plating film 33 is formed by an electroless plating method. For example, an electroless Cu plating film is formed as electroless plating film 33. Here, electroless plating film 33 is formed not only on the metal but also on the insulating material, so electroless plating film 33 is formed on wiring body layer 32b and on insulating layer 120. In such cases, electroless plating film 33 on wiring body layer 32b is thinner than the electroless plating film on insulating layer 120 because electroless plating film 33 is difficult to self-grow on copper.

Next, as illustrated in (e) in FIG. 4, adhesion film 34 is formed. Adhesion film 34 is formed so as to cover electroless plating film 33. More specifically, adhesion film 34 is formed over the entire upper surface of base 110. For example, adhesion film 34 can be formed by forming a metal film such as a copper film over the entire upper surface of base 110 and performing an adhesion treatment to give this metal film adhesive properties. In such cases, adhesion film 34 with a fine-textured structure can be formed by, as the adhesion treatment, roughening the metal film.

As illustrated in (d) in FIG. 4, this completes wiring-equipped wiring transfer plate 200 including transfer wiring 36 formed on wiring transfer plate 100 conductive layer 32c, where transfer wiring 36 includes wiring body layer 32b, electroless plating film 33, and adhesion film 34. In the area of the connection between layers, wiring-equipped wiring transfer plate 200 has the structure illustrated in FIG. 7.

Wiring-equipped wiring transfer plate 200 fabricated in this way allows transfer wiring 36 to be transferred to other components. Stated differently, conductive layer 32c, wiring body layer 32b, electroless plating film 33, and adhesion film 34 constitute transfer wiring 36, which is to be transferred to another component.

Note that wiring transfer plate 100 after transferring transfer wiring 36 of wiring-equipped wiring transfer plate 200 to another component returns to the state illustrated in (a) in FIG. 4, and can be used repeatedly. Stated differently, wiring transfer plate 100 can be reused. More specifically, as illustrated in (b) through (e) in FIG. 4, an electroless plating film or the like is deposited on wiring transfer plate 100 to once again form transfer wiring 36, which can then be transferred to another component.

In the present embodiment, wiring-equipped wiring transfer plate 200 is used to fabricate wiring body 30 and mounting substrate 1. This will be described next with reference to FIG. 8, which illustrates a cross-section of wiring between vias of mounting substrate 1, and FIG. 9, which illustrates a cross-section of a connection between layers of mounting substrate 1.

First, as illustrated in (a) through (c) in FIG. 8 and (a) through (c) in FIG. 9, transfer wiring 36 is disposed above substrate 10 with insulating layer 20 interposed therebetween. In the present embodiment, transfer wiring 36 is formed by a transfer method using wiring-equipped wiring transfer plate 200 that is prepared in advance.

More specifically, as illustrated in (a) in FIG. 8 and (a) in FIG. 9, substrate 10 including conductor 11 is prepared. For example, as substrate 10, a build-up substrate with wiring and electrodes, etc., formed as conductor 11 on the top layer is prepared.

Next, as illustrated in (b) in FIG. 8 and (b) in FIG. 9, an insulating material is disposed between substrate 10 including conductor 11 and wiring-equipped wiring transfer plate 200 to form insulating layer 20 between substrate 10 and wiring-equipped wiring transfer plate 200.

More specifically, an insulating material that will become insulating layer 20 is disposed on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is placed on top of the insulating material. Stated differently, the insulating material of insulating layer 20 is inserted between substrate 10 and wiring-equipped wiring transfer plate 200. Here, wiring-equipped wiring transfer plate 200 is arranged so that the exposed transfer wiring 36 is on the insulating layer 20 side.

For example, when a fluid liquid insulating resin material is used as the insulating material for insulating layer 20, the liquid insulating resin material is applied on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is disposed on top thereof and the liquid insulating resin material is cured. If the liquid insulating resin material is a thermosetting resin, it is cured by heating or drying, and if the liquid insulating resin material is a photo-curable resin, it is cured by light irradiation. This allows insulating layer 20 to be formed between substrate 10 and wiring-equipped wiring transfer plate 200.

When a film-like insulating resin sheet is used as the insulating material for insulating layer 20, the film-like insulating resin sheet is disposed on substrate 10 including conductor 11, and wiring-equipped wiring transfer plate 200 is disposed on top thereof and thermocompression bonded. At this time, wiring-equipped wiring transfer plate 200 is pressed toward substrate 10. This allows insulating layer 20 to be formed between substrate 10 and wiring-equipped wiring transfer plate 200.

Next, as illustrated in (c) in FIG. 8 and (c) in FIG. 9, wiring transfer plate 100 included in wiring-equipped wiring transfer plate 200 is separated from insulating layer 20. Stated differently, wiring transfer plate 100 is separated from insulating layer 20. This transfers transfer wiring 36 of wiring-equipped wiring transfer plate 200 to the substrate 10 side, away from plating base material layer 130 (the release layer). More specifically, transfer wiring 36 of wiring-equipped wiring transfer plate 200 is transferred to insulating layer 20, thereby forming transfer wiring 36 on insulating layer 20. In the present embodiment, conductive layer 32c, wiring body layer 32b, electroless plating film 33, and adhesion film 34 are transferred to insulating layer 20.

In the present embodiment, transfer wiring 36 is easily separated from plating base material layer 130 of wiring transfer plate 100 because plating base material layer 130 has releasing properties, and transfer wiring 36 easily adheres to insulating layer 20 because it includes adhesion film 34. This allows transfer wiring 36 to be easily transferred to insulating layer 20. Stated differently, the stacked body (stacked wiring) of conductive layer 32c and wiring body layer 32b, electroless plating film 33, and adhesion film 34 can be easily transferred to insulating layer 20.

When a film-like insulating resin sheet is used as the insulating material for insulating layer 20, the insulating resin sheet should have adhesive properties. This makes it easier for adhesion film 34 of transfer wiring 36 to adhere to insulating layer 20, so transfer wiring 36 can be transferred to insulating layer 20 more easily.

Thus, the component to which transfer wiring 36 is transferred onto substrate 10 including conductor 11 is wiring body intermediate material 300 for the wiring body, which is an intermediate material for wiring body 30 disposed above substrate 10. Therefore, wiring body intermediate material 300 includes adhesion film 34 formed on insulating layer 20 and including a fine-textured structure, electroless plating film 33 formed on adhesion film 34, conductive layer 32c, and wiring body layer 32b.

Next, as illustrated in (d) in FIG. 8 and (d) in FIG. 9, via hole 21 is formed in insulating layer 20 so as to expose conductor 11 by removing a portion of electroless plating film 33, adhesion film 34, and insulating layer 20. For example, via hole 21 can be formed by removing a portion of electroless plating film 33, adhesion film 34, and insulating layer 20 by irradiating a laser from above conductor 11. In this way, conductor 11 of substrate 10 is exposed by forming via hole 21 in electroless plating film 33, adhesion film 34, and insulating layer 20.

Next, as illustrated in (e) in FIG. 8 and (e) in FIG. 9, seed film is formed so as to cover exposed conductor 11, electroless plating film 33, and wiring body layer 32b. More specifically, after desmearing and removing the residue of insulating layer 20 by laser treatment, seed film is formed over the entire upper surface of substrate 10 by an electroless plating method or sputtering. In the present embodiment, conductive layer 32c is located on wiring body layer 32b, so seed film is stacked on each of conductor 11, electroless plating film 33, and conductive layer 32c.

Seed film is a seed electrode for forming via electrode body layer 31b of via electrode 31 by an electrolytic plating method, but by covering not only conductor 11 but also wiring body layer 32b and conductive layer 32c with this seed film 35, wiring body layer 32b and conductive layer 32c can be protected by seed film 35 until seed film 35 is removed in a subsequent process. Note that seed film 35 covers not only the top of conductive layer 32c but also the sides of wiring body layer 32b and conductive layer 32c. Therefore, a small amount of seed film 35 components (Pd, etc.) will be present on the top and sides of wiring body layer 32b and conductive layer 32c.

Note that in the present embodiment, seed film 35 is, for example, a metal film of a metallic material including copper. In such cases, seed film 35 may include only copper, and, alternatively, may include copper and another metal such as nickel.

Next, as illustrated in (f) in FIG. 8 and (f) in FIG. 9, resist 40 is selectively formed on seed film 35 so as to expose the portion of seed film 35 covering conductor 11. More specifically, opening 41 is formed in resist 40 above conductor 11. Resist 40 covers wiring body layer 32b. For example, dry film resist (DFR) can be used as resist 40.

Next, as illustrated in (g) in FIG. 8 and (g) in FIG. 9, via electrode body layer 31b is formed on the exposed seed film 35. More specifically, via electrode body layer 31b is formed so as to fill opening 41 in resist 40. In the present embodiment, as via electrode body layer 31b, an electrolytic plating film is formed on seed film 35 in opening 41 via an electrolytic plating method. As one example, via electrode body layer 31b is an electrolytic Cu plating film.

As illustrated in (g) in FIG. 9, in the area of the connection between layers, a portion of via electrode body layer 31b is formed so as to ride up over the edge of transfer wiring 36. More specifically, a portion of via electrode body layer 31b is formed on seed film 35 stacked on transfer wiring 36.

Next, as illustrated in (h) in FIG. 8 and (h) in FIG. 9, resist 40 is removed. More specifically, resist 40, which is dry film resist, is peeled off. This exposes the portion of seed film 35 that was covered by resist 40.

Next, as illustrated in (i) in FIG. 8 and (i) in FIG. 9, exposed seed film 35 is removed, and electroless plating film 33 and adhesion film 34 that are under exposed seed film 35 are removed. Stated differently, the portion of seed film 35 that covers wiring body layer 32b is removed, and the portions of electroless plating film 33 and adhesion film 34 not covered by wiring body layer 32b and via electrode body layer 31b are removed. More specifically, exposed seed film 35 and electroless plating film 33 and adhesion film 34 that are under exposed seed film 35 are removed by etching using an etchant.

At this time, since seed film 35 and conductive layer 32c of transfer wiring 36 include different conductive materials, seed film 35 can be selectively etched without etching conductive layer 32c. By etching seed film 35, electroless plating film 33, and adhesion film 34 in this way, seed film 35, electroless plating film 33, and adhesion film 34 remain under via electrode body layer 31b, and the remaining seed film 35 becomes seed layer 31a, the remaining electroless plating film 33 becomes electroless plating layer 31d, and the remaining adhesion film 34 becomes adhesion layer 31c. As a result, via electrode 31 including seed layer 31a, electroless plating layer 31d, via electrode body layer 31b, and adhesion layer 31c is formed.

In the part corresponding to transfer wiring 36, by etching seed film 35, electroless plating film 33, and adhesion film 34, electroless plating film 33 and adhesion film 34 remain under wiring body layer 32b, and the remaining electroless plating film 33 becomes electroless plating layer 32d, and the remaining adhesion film 34 becomes adhesion layer 32a, whereby wiring 32 including adhesion layer 32a, electroless plating layer 32d, wiring body layer 32b, and conductive layer 32c is formed.

Note that as described above, electroless plating film 33 stacked on wiring body layer 32b is thinner than the electroless plating film stacked on insulating layer 120, so the thickness of electroless plating layer 32d in wiring 32 is less than the thickness of electroless plating layer 31d in via electrode 31. Stated differently, the thickness of electroless plating layer 31d in via electrode 31 is greater than the thickness of electroless plating layer 32d in wiring 32.

In this way, wiring body 30 including via electrode 31 and wiring 32 is formed and mounting substrate 1 including wiring body can be fabricated. Stated differently, it is possible to fabricate wiring body 30 on substrate 10 including conductor 11 and also to fabricate mounting substrate 1 including wiring body 30 disposed above substrate 10.

Next, the features of the method for manufacturing wiring body and the method for manufacturing mounting substrate 1 according to the present embodiment will be explained by comparison with a conventional method for manufacturing mounting substrate 1X, with reference to FIG. 10. FIG. 10 illustrates a conventional method for manufacturing mounting substrate 1X including via electrode 31X and wiring 32X, and illustrates a typical modified semi-additive process (MSAP) method.

In the conventional method for manufacturing mounting substrate 1X, as illustrated in (a) in FIG. 10, insulating layer 20 is first formed between substrate 10 including conductor 11 and base 110X including a carrier foil on which metal film 33X including an ultra-thin copper foil is formed.

Next, as illustrated in (b) in FIG. 10, base 110X is peeled off from metal film 33X and metal film 33X is transferred to insulating layer 20.

Next, as illustrated in (c) in FIG. 10, metal film 33X and part of insulating layer 20 are removed by laser to form via hole 21 above conductor 11 so as to expose conductor 11.

Next, after desmearing, seed film 35X including an electroless plating film is formed over the entire upper surface of substrate 10 by an electroless plating method, as illustrated in (d) in FIG. 10. This forms seed film 35X on exposed conductor 11.

Next, as illustrated in (e) in FIG. 10, resist 40X including openings 41X and 42X is formed. Opening 41X is formed at the portion corresponding to via electrode 31X, and opening 42X is formed at the portion corresponding to wiring 32X. Note that dry film resist can be used as resist 40X.

Next, as illustrated in (f) in FIG. 10, an electrolytic plating film is formed on seed film 35X in openings 41X and 42X by an electrolytic plating method. As a result, an electrolytic plating film that will become via electrode body layer 31b is formed on seed film 35X covering conductor 11 in opening 41X, and an electrolytic plating film that will become wiring body layer 32b is formed on seed film 35X in opening 42X. Stated differently, via electrode body layer 31b and wiring body layer 32b are formed simultaneously. Note that via electrode body layer 31b and wiring body layer 32b are, for example, electrolytic Cu plating films including copper.

Next, as illustrated in (g) in FIG. 10, resist 40X is removed to expose seed film 35X.

Next, the exposed seed film 35X and metal film 33X under seed film 35X are removed by etching. This leaves seed film 35X and metal film 33X under via electrode body layer 31b and the remaining seed film 35X becomes seed layer 31a, forming via electrode 31X, as illustrated in (h) in FIG. 10. Seed film 35X and metal film 33X under wiring body layer 32b remain to form wiring 32X including metal film 33X, seed film 35X, and wiring body layer 32b.

In this way, mounting substrate 1X including via electrode 31X and wiring 32X can be fabricated.

However, because the line width of wiring 32X is smaller than the diameter of via electrode 31X, with the conventional method for manufacturing mounting substrate 1X, the lower layer of wiring 32X is undercut by over-etching in the process of removing seed film 35X and metal film 33X, as illustrated in (g) in FIG. 10. Stated differently, the line width of the lower layer of wiring 32X decreases when etching seed film 35X. More specifically, metal film 33X and seed film 35X in wiring 32X are undercut, thereby reducing the line width. As a result, wiring defects may occur in wiring 32X. Therefore, it is difficult to make wiring 32X finer in the conventional method for manufacturing mounting substrate 1X. In such cases, seed film 35X thickness could be made thinner to prevent undercutting of the bottom portion of wiring 32X, but in order to maintain the connection reliability of via electrode 31X, seed film 35X thickness cannot be reduced.

In contrast, in wiring body 30 according to the present embodiment, adhesion layer 31c, which is the lower layer located above insulating layer 20 in via electrode 31, and adhesion layer 32a, which is the lower layer in wiring 32, include the same material, but seed layer 31a, which is the lower layer of via electrode 31 in via hole 21, and adhesion layer 32a, which is the lower layer in wiring 32, include different conductive materials or have different uneven shapes. In such cases, in the present embodiment, seed layer 31a of via electrode 31 and adhesion layer 32a of wiring 32 both include copper, but include different conductive materials. Stated differently, seed layer 31a and adhesion layer 32a are metal films including copper as the same metal element, but at least one of seed layer 31a or adhesion layer 32a includes a metal film including a metal element other than copper or having a different structure, and seed layer 31a and adhesion layer 32a include different conductive materials or have different uneven shapes. Thus, in the present embodiment, the lower layer of wiring 32 is adhesion layer 32a, i.e., wiring 32, unlike via electrode 31, does not include a seed layer as a lower layer. Via electrode 31, however, does include adhesion layer 31c on insulating layer 20 but does not include an adhesion layer as a lower layer in via hole 21.

In wiring body 30 and mounting substrate 1 according to the present embodiment, in the portion of via electrode 31 located above insulating layer 20, via electrode 31 includes both adhesion layer 31c including a fine-textured structure and seed layer 31a. This improves the adhesion between via electrode 31 and insulating layer 20.

In wiring body 30 according to the present embodiment, adhesion layer 31c of via electrode 31 or adhesion layer 32a of wiring 32 is formed on electroless plating layer 31d or electroless plating layer 32d, but the thickness of electroless plating layer 31d of via electrode 31 and the thickness of electroless plating layer 32d of wiring 32 are different. More specifically, the thickness of electroless plating layer 31d of via electrode 31 is greater than the thickness of electroless plating layer 32d of wiring 32. This inhibits undercutting of the lower layer of wiring 32 by the etching when seed layer 31a of via electrode 31 is patterned by etching seed film 35 and adhesion film 34 with an etchant. This inhibits the line width of the lower layer of wiring 32 from decreasing. Therefore, with wiring body 30 and mounting substrate 1 according to the present embodiment, wiring 32 can be made finer and disposed at a narrower pitch even if it includes via electrode 31.

The method for manufacturing wiring body 30 and the method for manufacturing mounting substrate 1 according to the present embodiment include: disposing, on insulating layer 20 on substrate 10, adhesion film 34 including a fine-textured structure and wiring body layer 32b above adhesion film 34; after disposing adhesion film 34 and wiring body layer 32b, forming via hole 21 in insulating layer so as to expose conductor 11 by removing a portion of adhesion film 34 and a portion of insulating layer 20; after forming via hole 21, forming seed film 35 to cover conductor 11 that is exposed, adhesion film 34, and wiring body layer 32b; after forming seed film 35, selectively forming resist 40 on seed film 35 so as to expose a portion of seed film 35 covering conductor 11; after selectively forming resist 40, forming via electrode body layer 31b on seed film 35 that is exposed; and after forming via electrode body layer 31b and after removing resist 40, removing seed film 335 that is exposed and adhesion film 34 under seed film 35 that is exposed.

With this, since wiring body layer 32b can be protected by seed film 35 to form via electrode body layer 31b, even with wiring body 30 and mounting substrate 1 including via electrode 31, wiring 32 including wiring body layer 32b can be made finer and disposed at a narrower pitch. For example, wiring 32 that is finer and disposed at a narrower pitch can be built into the same wiring layer as via electrode 31.

In the present embodiment, at least wiring body layer 32b is formed by a transfer method in the disposing of wiring body layer 32b and adhesion film 34. More specifically, wiring body layer 32b is formed using wiring-equipped wiring transfer plate 200, which is wiring transfer plate 100 including transfer wiring 36 formed thereon.

Wiring-equipped wiring transfer plate 200 includes: base 110; a release layer (plating base material layer 130) formed on base 110; insulating layer 120 (transfer plate insulating layer) covering base 110 with openings 121 above the release layer; wiring body layer 32b, which is an electroless plating film formed on release layer 131, in openings 121,; and adhesion film 34 that is formed to so as cover wiring body layer 32b and insulating layer 120 and includes a fine-textured structure. Wiring body layer 32b, which is an electroless plating film, and adhesion film 34 constitute transfer wiring 36 that is transferred to another component.

In this way, by using wiring-equipped wiring transfer plate 200, fine wiring body layer 32b can be formed with high precision even if the surface (transfer target surface) of substrate 10, which is the transfer target component, has unevenness due to, for example, wiring or electrodes. Stated differently, when wiring is formed by a photolithography method, if there is unevenness on the surface of the portion where wiring is formed, the focus is shifted and fine wiring cannot be formed precisely. However, by forming wiring body layer 32b using a transfer method using wiring-equipped wiring transfer plate 200 like in the present embodiment, even if the surface of the area where wiring body layer 32b has unevenness, i.e., is not flat, the effect that unevenness has can be reduced. This allows fine wiring body layer 32b to be formed with high precision.

Moreover, by using a rigid glass substrate or metal plate as base 110 of wiring-equipped wiring transfer plate 200, wiring body layer 32b can be formed with high positioning accuracy.

In the present embodiment, wiring body layer 32b and adhesion film 34 are transferred simultaneously by a transfer method in the disposing of wiring body layer 32b and adhesion film 34. Stated differently, not only wiring body layer 32b is transferred using wiring transfer plate 100, but adhesion film 34 is also transferred together with wiring body layer 32b.

This enables efficient formation of not only wiring body layer 32b but also via electrode 31 and adhesion film 34, which is part of wiring 32.

In the present embodiment, via electrode 31 includes seed layer 31a formed over conductor 11 and insulating layer 20, and via electrode body layer 31b formed on seed layer 31a and over conductor 11 and insulating layer 20. Adhesion layer 31c in via electrode 31 is provided between insulating layer 20 and a portion of seed layer 31a located above insulating layer 20.

This configuration allows via electrode body layer 31b to be easily formed by electrolytic plating.

In the present embodiment, wiring 32 further includes conductive layer 32c provided on wiring body layer 32b and including conductive material different from that of wiring body layer 32b.

This allows conductive layer 32c to protect wiring body layer 32b when seed layer 31a of via electrode 31 is patterned by etching seed film 35. Stated differently, selective etching using the etching rate difference between seed film 35 and wiring body layer 32b becomes possible. This can inhibit the line width of wiring 32 from changing due to the thinning of film when etching seed film 35.

In the present embodiment, conductive layer 32c is also transferred by wiring transfer plate 100. Stated differently, in addition to wiring body layer 32b and adhesion film 34, conductive layer 32c is also transferred at the same time. This allows efficient formation of wiring body layer 32b as well as conductive layer 32c and adhesion film 34.

In the present embodiment, the crystal grain size of the copper included in via electrode body layer 31b and the crystal grain size of the copper included in wiring body layer 32b are different.

This allows via electrode body layer 31b and wiring body layer 32b to be formed using different manufacturing methods according to required characteristics other than low resistance. For example, via electrode body layer 31b and wiring body layer 32b can be formed by different plating methods.

In such cases, via electrode body layer 31b of via electrode 31 is an electrolytic plating film formed by an electrolytic plating method and constitutes 90% or more of via electrode 31 in a cross-sectional view.

Thus, by making via electrode body layer 31b a comparatively low-stress electrolytic plating film, it is possible to inhibit the occurrence of plating peeling and cracks in via electrode 31 due to internal stress.

In contrast, wiring body layer 32b of wiring 32 is an electroless plating film formed by an electroless plating method and constitutes 90% or more of wiring 32 in a cross-sectional view.

By using an electroless plating method, it is easy to form a plurality of lines of wiring 32 with a large surface area and uniform film thickness. This allows the formation of a plurality of lines of wiring 32 with high film thickness uniformity and uniform wiring resistance. Stated differently, it is possible to realize wiring body 30 and mounting substrate 1 including wiring 32 with uniform wiring resistance in all regions.

The line width of wiring 32 according to the present embodiment should be 5 μm or less, and more preferably 2 μm or less. By making wiring 32 fine wiring as described above, it is possible to pass a large number of lines of fine wiring between vias, enabling high-density mounting with a small number of wiring layers. Furthermore, variation in the thickness of wiring 32 according to the present embodiment is less than ±10% or ±1 μm. By forming wiring 32, which is fine wiring with such thickness variation, it is possible to inhibit variation in characteristic impedance.

Wiring body 30 fabricated in this way can be used as a wiring layer or redistribution layer (RDL) in a semiconductor package substrate.

For example, as illustrated in FIG. 11, wiring body 30 can be used as a redistribution layer in mounting substrate 1A, which is a 2.1D semiconductor package substrate (organic interposer), and as illustrated in FIG. 12, wiring body 30 can be used as a redistribution layer in mounting substrate 1B, which is a 2.3D semiconductor package substrate (organic interposer). In FIG. 11 and FIG. 12, substrate 10 is a build-up substrate.

As illustrated in FIG. 13, wiring body 30 can be used as a redistribution layer in mounting substrate 1C, which is a 2.5D semiconductor package substrate (Si or glass interposer).

As another example, wiring body 30 can be used as a redistribution layer in a mounting substrate that is a Fan Out-Wafer Level Package (FO-WLP).

Mounting substrates 1A, 1B, and 1C illustrated in FIG. 11 through FIG. 13 can also be applied to Embodiments 2 and 3 below.

Moreover, wiring body 30 can also be applied to a build-up layer (wiring layer) of a typical build-up substrate, rather than the redistribution layer. For example, wiring body 30 can be applied to the wiring layer of substrate 10, which is the build-up substrate illustrated in FIG. 11 through FIG. 13. As a result, it is possible to realize an embodiment in which fine wiring 32 of 5 μm or less, which was conventionally difficult, is formed, whereby a semiconductor package substrate that does not require an interposer or redistribution layer can be obtained. Furthermore, such a structure improves electrical characteristics because the wiring distance from electronic components formed in the core, such as inductors or capacitors, to the semiconductors is shortened, and also eliminates the need for an interposer or a redistribution layer, resulting in an inexpensive semiconductor package.

Embodiment 2

Next, the configurations of wiring body 30D and mounting substrate 1D according to Embodiment 2 will be described with reference to FIG. 14. FIG. 14 is a cross-sectional view of mounting substrate 1D according to Embodiment 2.

In wiring 32 in Embodiment 1 described above, conductive layer 32c is formed on top of wiring body layer 32b, but as illustrated in FIG. 14, wiring 32D, which is included in wiring body 30D and mounting substrate 1D according to the present embodiment, does not include conductive layer 32c on top of wiring body layer 32b. More specifically, wiring 32D includes only adhesion layer 32a, electroless plating layer 32d, and wiring body layer 32b.

In wiring body 30 and mounting substrate 1 in Embodiment 1 described above, seed layer 31a of via electrode 31 and wiring body layer 32b of wiring 32 included the same metal, but in wiring body 30D and mounting substrate 1D according to the present embodiment, seed layer 31aD of via electrode 31D and wiring body layer 32b of wiring 32D include different types of metals. More specifically, in Embodiment 1 described above, both seed layer 31a and wiring body layer 32b are metal films including copper, but in the present embodiment, wiring body layer 32b is a metal film including only copper, while seed layer 31aD is a metal film including a metal other than copper. Stated differently, in the present embodiment, wiring body layer 32b of wiring 32D is the same as in Embodiment 1 described above, but seed layer 31aD of via electrode 31D includes a metal other than copper, unlike in Embodiment 1 described above.

Note that wiring body 30D and mounting substrate 1D according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above except that wiring 32D does not include conductive layer 32c and that seed layer 31aD and wiring body layer 32b include different types of metals.

Wiring body 30D and mounting substrate 1D configured as described above are manufactured by the method illustrated in FIG. 15. FIG. 15 illustrates the method for manufacturing wiring body 30D and the method for manufacturing mounting substrate 1D according to Embodiment 2.

Wiring-equipped wiring transfer plate 200D, in which transfer wiring 36D is formed on wiring transfer plate 100, is also used in the present embodiment as well. Stated differently, in the present embodiment as well, wiring 32D is formed by a transfer method using wiring-equipped wiring transfer plate 200D that is prepared in advance. However, in wiring-equipped wiring transfer plate 200D, transfer wiring 36D does not include conductive layer 32c. More specifically, transfer wiring 36D includes wiring body layer 32b, electroless plating film 33, and adhesion film 34.

First, as illustrated in (a) through (c) in FIG. 15, transfer wiring 36D is disposed above substrate 10 with insulating layer 20 interposed therebetween.

More specifically, as illustrated in (a) in FIG. 15, substrate 10 including conductor 11 is prepared, just as in the process illustrated in (a) in FIG. 8.

Next, as illustrated in (b) in FIG. 15, just as in the process illustrated in (b) in FIG. 8, an insulating material is disposed between substrate 10 including conductor 11 and wiring-equipped wiring transfer plate 200D to form insulating layer 20 between substrate 10 and wiring-equipped wiring transfer plate 200D.

Next, as illustrated in (c) in FIG. 15, just as in the process illustrated in (c) in FIG. 8, wiring transfer plate 100 included in wiring-equipped wiring transfer plate 200D is separated from insulating layer 20. This transfers transfer wiring 36D of wiring-equipped wiring transfer plate 200D to the substrate 10 side, away from release layer 131. More specifically, transfer wiring 36D of wiring-equipped wiring transfer plate 200D is transferred to and thus formed on insulating layer 20. In the present embodiment, wiring body layer 32b, electroless plating film 33, and adhesion film 34 are transferred to insulating layer 20.

Next, as illustrated in (d) in FIG. 15, just as in the process illustrated in (d) in FIG. 8, via hole 21 is formed in insulating layer 20 by laser so as to expose conductor 11 by removing a portion of electroless plating film 33, adhesion film 34, and insulating layer 20. Stated differently, a laser is used to form via hole 21 in insulating layer 20 to expose conductor 11 of substrate 10.

Next, as illustrated in (e) in FIG. 15, just as in the process illustrated in (e) in FIG. 8, seed film 35D is formed so as to cover exposed conductor 11, electroless plating film 33, and wiring body layer 32b. More specifically, seed film 35D is formed over the entire upper surface of substrate 10. Seed film 35D includes a different type of metal than wiring body layer 32b. More specifically, wiring body layer 32b includes only copper, but seed film 35D includes a metal other than copper.

Next, as illustrated in (f) in FIG. 15, just as in the process illustrated in (f) in FIG. 8, resist 40 is selectively formed on seed film 35D so as to expose the portion of seed film 35D covering conductor 11.

Next, as illustrated in (g) in FIG. 15, just as in the process illustrated in (g) in FIG. 8, via electrode body layer 31b is formed on the exposed seed film 35D. More specifically, via electrode body layer 31b is formed so as to fill opening 41 in resist 40. In the present embodiment as well, via electrode body layer 31b is an electrolytic plating film that is stacked on seed film 35D in opening 41 by an electrolytic plating method. More specifically, via electrode body layer 31b is an electrolytic Cu plating film.

Next, as illustrated in (h) in FIG. 15, just as in the process illustrated in (h) in FIG. 8, resist 40 is removed. This exposes the portion of seed film 35D that was covered by resist 40.

Next, as illustrated in (i) in FIG. 15, just as in the process illustrated in (i) in FIG. 8, exposed seed film 35D as well as electroless plating film 33 and adhesion film 34 that are under the exposed seed film 35D are removed by etching using an etchant. Stated differently, the portion of seed film 35D that covers wiring body layer 32b is removed, and the portions of electroless plating film 33 and adhesion film 34 not covered by wiring body layer 32b and via electrode body layer 31b are removed.

In the present embodiment, since wiring body layer 32b of transfer wiring 36D includes a different metal than seed film 35D, seed film 35D can be selectively etched without etching wiring body layer 32b. By etching seed film 35D as well as electroless plating film 33 and adhesion film 34 in this manner, via electrode 31D including seed layer 31aD, via electrode body layer 31b, electroless plating layer 31d, and adhesion layer 31c is formed, as well as is wiring 32D including adhesion layer 32a, electroless plating layer 32d, and wiring body layer 32b.

In this way, wiring body 30D including via electrode 31D and wiring 32D is formed and mounting substrate 1D including wiring body 30D can be fabricated. Stated differently, it is possible to fabricate wiring body 30D on substrate 10 including conductor 11 and also to fabricate mounting substrate 1D including wiring body 30D disposed above substrate 10.

Thus, in wiring body 30D according to the present embodiment as well, just as in wiring body 30 according the embodiment described above, adhesion layer 31c, which is the lower layer located above insulating layer 20 in via electrode 31D, and adhesion layer 32a, which is the lower layer in wiring 32D, include the same material, but seed layer 31aD, which is the lower layer of via electrode 31D in via hole 21, and adhesion layer 32a, which is the lower layer in wiring 32D, include different conductive materials. Moreover, in the present embodiment as well, the lower layer of wiring 32D is adhesion layer 32a, and wiring 32D does not include a seed layer as a lower layer.

Via electrode 31D does include adhesion layer 31c on insulating layer but does not include an adhesion layer as a lower layer in via hole 21.

This inhibits the undercutting of the lower layer of wiring 32D in the etching and patterning of seed film 35D to form seed layer 31aD, which becomes the lower layer of via electrode 31D, and thus inhibits the line width of the lower layer of wiring 32D from being reduced.

Therefore, in wiring body 30D and mounting substrate 1D according to the present embodiment as well, wiring 32D can be made finer and disposed at a narrower pitch.

In the present embodiment, although wiring 32D does not include conductive layer 32c, and wiring body layer 32b is not protected by conductive layer 32c when seed film 35D is etched, since seed film 35D and wiring body layer 32b include different types of metals, it is possible to selectively etch using the etching rate difference between seed film 35D and wiring body layer 32b. Stated differently, although conductive layer 32c is not formed on top of wiring body layer 32b, when seed layer 31aD is etched with an etchant, wiring body layer 32b can be prevented from being removed by the etchant. This can inhibit the line width of wiring 32D from changing due to the thinning of film when etching seed film 35D.

In the present embodiment, wiring 32D does not include conductive layer 32c, but wiring 32D may include conductive layer 32c.

Embodiment 3

Next, the configurations of wiring body 30E and mounting substrate 1E according to Embodiment 3 will be described with reference to FIG. 16. FIG. 16 is a cross-sectional view of mounting substrate 1E according to Embodiment 3.

In Embodiment 1 described above, via electrode 31 includes seed layer 31a, via electrode body layer 31b, which is an electrolytic plating film stacked on seed layer 31a, electroless plating layer 31d, and adhesion layer 31c, but this example is non-limiting.

More specifically, as illustrated in FIG. 16, in wiring body 30E and mounting substrate 1E according to the present embodiment, via electrode 31E does not include seed layer 31a, and includes only via electrode body layer 31bE, electroless plating layer 31d, and adhesion layer 31c. Moreover, in the present embodiment, via electrode body layer 31bE is formed by conductive paste such as silver paste instead of electrolytic plating film.

Note that except for the configuration of via electrode 31E, wiring body 30E and mounting substrate 1E according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above.

Wiring body 30E and mounting substrate 1E configured as described above are manufactured by the method illustrated in FIG. 17. FIG. 17 illustrates the method for manufacturing wiring body 30E and the method for manufacturing mounting substrate 1E according to Embodiment 3.

Wiring-equipped wiring transfer plate 200, in which transfer wiring 36 is formed on wiring transfer plate 100, is also used in the present embodiment as well. Stated differently, in the present embodiment as well, wiring 32 is formed by a transfer method using wiring-equipped wiring transfer plate 200 that is prepared in advance.

First, as illustrated in (a) through (c) in FIG. 17, transfer wiring 36 is disposed above substrate 10 with insulating layer 20 interposed therebetween. In the present embodiment, the processes illustrated in (a) through (c) in FIG. 17 are the same as the processes illustrated in (a) through (c) in FIG. 8.

Next, as illustrated in (d) in FIG. 17, just as in the process illustrated in (d) in FIG. 8, conductor 11 of substrate 10 is exposed by forming via hole 21 in insulating layer 20 by removing a portion of adhesion film 34 and insulating layer 20 by laser.

Next, as illustrated in (e) in FIG. 17, via electrode body layer 31bE is formed so as to cover the exposed conductor 11, and then electroless plating film 33 and adhesion film 34 are removed by etching. This allows the formation of via electrode 31E. Note that via electrode body layer 31bE can be formed by applying conductive paste, for example.

In this way, wiring body 30E including via electrode 31E and wiring 32 is formed and mounting substrate 1E including wiring body 30E can be fabricated. Stated differently, it is possible to fabricate wiring body 30E on substrate 10 including conductor 11 and also to fabricate mounting substrate 1E including wiring body 30E disposed above substrate 10.

Thus, in wiring body 30E according to the present embodiment, just as in wiring body 30 according to Embodiment 1 above, adhesion layer 31c, which is the lower layer located above insulating layer 20 in via electrode 31E, and adhesion layer 32a, which is the lower layer in wiring 32, include the same material, but the lower layer of via electrode 31E in via hole 21 and the lower layer in wiring 32 include different conductive materials. More specifically, in the present embodiment, the lower layer of via electrode 31E in via hole 21 is part of via electrode body layer 31bE, which includes conductive paste, and includes a different conductive material than adhesion layer 32a, which is the lower layer in wiring 32.

Thus, since there is no seed layer in via electrode 31E, there is no need to etch the seed layer when forming via electrode 31E.

Therefore, the lower layer of wiring 32 is not undercut in a seed layer etching process, and the line width of the lower layer of wiring 32 is not reduced.

Therefore, in wiring body 30E and mounting substrate 1E according to the present embodiment as well, wiring 32E can be made finer and disposed at a narrower pitch.

Embodiment 4

Next, the configurations of wiring body 30F and mounting substrate 1F according to Embodiment 4 will be described with reference to FIG. 18. FIG. 18 is a cross-sectional view of mounting substrate 1F according to Embodiment 4.

In Embodiment 1 described above, wiring 32 includes adhesion layer 32a including a fine-textured structure, electroless plating layer 32d (a seed layer), which is an electroless plating film of Cu, wiring body layer 32b, which is an electroless plating film of Cu, and conductive layer 32c (a protective layer), which is an electroless plating film of Cu.

More specifically, as illustrated in FIG. 18, in wiring body 30F and mounting substrate 1F according to the present embodiment, wiring 32F does not include conductive layer 32c, which is a protective layer, and includes adhesion layer 32aF, electroless plating layer 32d, and wiring body layer 32bF.

In the present embodiment, adhesion layer 32aF is not a fine-textured structure formed by copper oxide treatment, etc., but an organic thin film formed by organic adhesion treatment. For example, by introducing an organic component having high adhesion strength with the resin included in insulating layer 20 onto the surface of the copper included in wiring body layer 32bF, an organic thin film including an organic component chemically bonded to the resin included in insulating layer 20 and an organic component chemically bonded to the copper included in wiring body layer 32bF can be formed as adhesion layer 32aF. When adhesion layer 32a is formed by copper oxide treatment, there is a possibility that electroless plating layer 32d (the seed layer) formed in the copper oxide treatment will peel off or wiring 32 will peel off during etching because copper oxide is weak against acid. However, by forming adhesion layer 32aF by organic adhesion treatment as in the present embodiment, such defects can be inhibited.

In the present embodiment, wiring body layer 32bF is an electroplating film, not an electroless plating film. More specifically, wiring body layer 32bF is an electroplating film including copper. This eliminates the need for conductive layer 32c as a protective layer as in Embodiment 1, since there is etching selectivity between wiring body layer 32bF, which is an electroplating film, and electroless plating layer 32d, which is an electroless plating film.

Note that except for the configuration of wiring 32F, wiring body 30F and mounting substrate 1F according to the present embodiment are the same as wiring body 30 and mounting substrate 1 according to Embodiment 1 described above. The present embodiment can be applied not only to Embodiment 1 described above, but also to Embodiments 2 and 3 described above.

[Variation]

Hereinbefore, the wiring body and mounting substrate according to the present disclosure have been described based on embodiments, but the present disclosure is not limited to Embodiments 1 through 4 described above.

For example, in Embodiments 1 through 4 described above, insulating layer 120 that serves as the transfer plate insulating layer in wiring transfer plate 100 is a resist, but this is non-limiting. For example, insulating layer 120 may be an insulating resin material including an inorganic material such as SiO₂. In such cases, wiring transfer plate 100B including insulating layer 120B can be fabricated by the method illustrated in FIG. 19.

First, as illustrated in (a) in FIG. 19, a plating-base-material-equipped base, which includes plating base material layer 130 formed on base 110 that serves as a support substrate, is received. Then, as illustrated in (b) in FIG. 19, insulating layer 12013 (the transfer plate insulating layer) including SiO₂is formed on top of plating base material layer 130. Then, resist 140 is formed on top of insulating layer 1206, as illustrated in (c) in FIG. 19. Next, as illustrated in (d) in FIG. 19, resist 140 is exposed and developed, etc., to form openings 141 in resist 140 by patterning resist 140 to expose insulating layer 1206. Next, as illustrated in (e) in FIG. 19, plasma etching is performed using resist 140 including openings 141 as a mask to form openings 121 in insulating layer 12013 to expose plating base material layer 130. Next, as illustrated in (f) in FIG. 19, resist 140 is removed. This completes wiring transfer plate 100B.

In Embodiments 1 through 4 described above, the electroless plating film may be an electroplating film, and the electroplating film may be an electrolytic plating film. Stated differently, the electroless plating film and the electroplating film may simply be plating films without distinction.

For example, embodiments arrived at by a person of skill in the art making various modifications to the above embodiments as well as embodiments realized by arbitrarily combining elements and functions in the embodiments which do not depart from the essence of the present disclosure are included in the present disclosure.

INDUSTRIAL APPLICABILITY

The wiring body according to the present disclosure is applicable as a wiring layer or the like in mounting substrates such as semiconductor package substrates.

REFERENCE SIGNS LIST

1, 1A, 1B, 1C, 1D, 1E, 1F mounting substrate

10 substrate

11 conductor

20 insulating layer

21 via hole

30, 30A, 30D, 30E, 30F wiring body

31, 31A, 31D, 31E via electrode

31
a,
31
aD seed layer

31
b,
31
bE via electrode body layer

31
c adhesion layer

31
d electroless plating layer

32, 32A, 32D, 32E, 32F wiring

32
a,
32
aF adhesion layer

32
b,
32
bF wiring body layer

32
c conductive layer

32
d electroless plating layer

33 electroless plating film

34 adhesion film

35, 35D seed film

36, 36D transfer wiring

40 resist

41, 141 opening

100, 100A, 100B wiring transfer plate

110 base

120, 120B insulating layer

121 opening

130, 130A plating base material layer

131 release layer

140 resist

200, 200D wiring-equipped wiring transfer plate

300 wiring body intermediate material

WIRING BODY, MOUNTING SUBSTRATE, WIRING-EQUIPPED WIRING TRANSFER PLATE, WIRING BODY INTERMEDIATE MATERIAL, METHOD FOR MANUFACTURING WIRING BODY, AND METHOD FOR MANUFACTURING MOUNTING SUBSTRATE

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CPC

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Abstract

Description

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Priority Claims (1)

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