Patent Application
20130299966
Integrated circuits, also referred to as “IC's” or “semiconductor chips” or simply “chips,” are electronic circuits made by diffusion of trace elements into the surface of thin substrates of semiconductor material such as silicon. Semiconductor chips are typically mass produced in the form of a single wafer that contains a large number of identical integrated circuits. The wafer is cut (“singulated”) into a number of individual semiconductor chips referred to as “dies” or “dice.”
Dies are usually “packaged” to prevent damage to the dies and to facilitate attachment of the dies to circuit boards. Various packaging materials and processes have been used to package integrated circuit dies. One conventional packaging method involves mounting individual dies in a predetermined pattern on a substrate strip. The dies mounted on the substrate strip are then encapsulated in a protective material such as plastic. The encapsulated dies are next singulated into individual integrated circuit packages by cutting the encapsulated die/substrate strip in accordance with the predetermined die mounting pattern. Typical cutting tools include saws and punches. Each integrated circuit package generally includes at least one die and the underlying portion of the substrate strip on which it was mounted, as well as encapsulating material which typically covers the die. The underlying substrate strip is sometimes a lead frame to which the die is electrically connected and which, in turn, is adapted to be connected to a printed circuit board (“PC” board).
Over the years, integrated circuits and the circuit boards to which they are attached have become physically smaller and more complex. One relatively new technology is known alternately as “wafer scale packaging,” “wafer level chip scale packaging,” “wafer level chip size packaging,” or other similar names. The phrase “wafer scale packaging” (“WSP”) will be used herein. Using WSP packaging, unpackaged dies, i.e., dies with no surrounding layer of protective encapsulation, may be directly mounted on printed circuit boards. The structure needed for electrical connection of dies to a printed circuit board is usually fabricated on a first surface of the dies while the dies are still integrally connected together in a single wafer. For example, in one form of WSP packaging, various layers including electrical contact pads, solder bumps and intermediate layers are formed on a first surface of dies at the wafer level. WSP eliminates conventional packaging steps such as die bonding, wire bonding, and die level flip chip attach processes to a package substrate by using the IC die itself as the electrical connection substrate. Use of the die itself as the WSP substrate significantly reduces the footprint to the IC die as compared to the same IC die attached to a package substrate.
WSP can be embodied as direct-bump WSP or redistribution layer (“RDL”) WSP which unlike direct-bump WSP adds an RDL that functions as a rewiring layer. This rewiring layer enables repositioning of external terminals at desired positions. (A redistribution layer is sometimes referred to in the art as a “redirect layer.”)
In a typical RDL WSP production flow, during back end of the line (BEOL) wafer fab processing, the IC die is provided with die pads (also known as bond pads or die bond pads) and a passivation layer. A first WSP dielectric (e.g., a polyimide) is then deposited over the passivation layer and die pads. Lithography/etching are used to form first vias in the first WSP dielectric over the die pads, followed by deposition and patterning of an RDL, including a plurality of RDL traces, which contact the die pads and extend laterally therefrom. A second WSP dielectric (e.g., a polyimide) is then deposited on the RDL and second vias are formed that reach the RDL in RDL capture pad positions. The positions of the RDL capture pads are laterally spaced from the positions of the die pads. Under bump metallization (UBM) pads commonly referred to as “ball pads” or “bump pads” are formed over the second vias and are coupled to and generally enclosed by RDL capture pads, followed by forming metal (e.g., solder) balls, pillars or other bonding connectors on the UBM pads. The area of the RDL capture pads is generally larger than the area of the UBM pad thereon to absorb stresses and thus improve structural reliability. The WSP wafer is singulated to form a plurality of singulated WSP die, commonly for use on circuit boards for portable devices where the board area is precious.
WSP dies (also referred to as WSP “chips”) are often connected to external circuitry, e.g. printed circuit (“PC”) boards, wiring substrates or other chips, using ball grid arrays. A ball grid array is formed on a front (top) face of each die and is placed in electrical contact with corresponding connectors on the external circuitry. WSP dies that have such ball grid arrays are sometimes referred to in the art as “flip chips” because the ball grid array is simply “flipped over” to a front (top) face down orientation to connect it to the external circuitry. In designing WSP dies with ball grid arrays there are conflicting considerations. The size of each ball, and thus the diameter of the under bump metal (UBM) layer to which the ball is attached, cannot be reduced because of mechanical reliability considerations. However, large balls are generally undesirable when the balls carry RF signals because the associated large UBM layer and corresponding large redistribution layer (RDL) capture pad to which the UBM is attached create capacitance related parasitic effects. These parasitic effects manifest themselves in lower transmission power, poorer signal matching, and/or lower band width of operation, etc. for a typical wireless transceiver. In typical WSP dies the RDL capture pad has a larger footprint than the UBM pad. Reducing the size of the RDL capture pad would reduce the capacitance/parasitic effects. However, reducing the size of the RDL capture pad creates other problems as illustrated by
In describing the various features of a WSP die, applicants have used terms of positional/directional reference such as “up,” “down,” “bottom”, “top,” “above,” “below,” “lateral” and “vertical” which are sometimes used in reference to an orientation with respect to the surface of the earth. Such terms are not used in that sense in this application. Rather, terms such as up, down, etc. are used in a relative sense to indicate the position of a die layer or surface, etc. with respect to other layers or surfaces, etc. in a structure which initially is oriented as shown in the drawings. As used in this sense the “top” of a car would still be referred to as the “top” of the car, even when the car is subsequently positioned upside down in a ditch. Also, it will be understood by those skilled in the art that, for the most part, various layers of a die are arranged in parallel planes that are separated vertically, i.e., in a direction perpendicular to the planes, by very small distances, e.g. 0.1-10 μm. When a first layer is positioned over a second layer in this manner, a portion of the first layer, which projects laterally outwardly from a vertical projection of the second layer that is superimposed onto the first layer, will simply be referred to as projecting laterally outwardly from the second layer and vice verse, even though the two layers are positioned in different planes.
Referring to
A top view of the UBM pad 60 and its relative position with respect to RDL 40 is illustrated in
One advantage of having a portion 70 of the RDL capture pad 41 projecting beyond the periphery 67 of the UBM pad 60 is illustrated in
Although in the illustrated embodiment, the RDL capture pad 41 and UBM pad 60 each have a circular outer periphery, in other embodiments the structures may have polygonal or other shapes so long as the central axes RR, UU thereof are radially offset. In some embodiments the portion of the RDL capture pad 41 positioned below the UBM pad 60 has a smaller area than the outer peripheral edge of the UBM pad 60 and a portion of the RDL capture pad projects outwardly from the area of overlap with the UBM pad. As discussed above, the actual direction in which projecting portion 70 of the RDL capture pad 41 projects will depend upon the structure of the die 10.
Although certain embodiments of a WSP die have been described in detail herein, it is to be understood that a WSP die is not limited to such embodiments and such detail and that it may be otherwise constructed and arranged without departing from the spirit and scope of this description. Many alternative embodiments will be apparent to those skilled in the art after reading this disclosure. It is intended that the appended claims be construed to encompass such alternative embodiments, except to the extent limited by the prior art.
