Artisan Components, Inc.

Organization

Sunnyvale, CA, US

SEMICONDUCTORS & RELATED DEVICES
Business Address
141 CASPIAN COURT SUNNYVALE CA 94089 4087345600
Mailing Address
141 CASPIAN COURT SUNNYVALE CA 94089
State Location
CA
State of Incorporation
DE

Organizations

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Patents Grantslast 30 patents

Information Patent Grant
System and method for assured built in self repair of memories
- Patent number 6,973,605
- Issue date Dec 6, 2005
- Artisan Components, Inc.
- Mark Templeton
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory column redundancy circuitry and method for implementing the...
- Patent number 6,966,012
- Issue date Nov 15, 2005
- Artisan Components, Inc.
- Dhrumil Gandhi
- G11 - INFORMATION STORAGE
Information Patent Grant
Yield maximization in the manufacture of integrated circuits
- Patent number 6,957,402
- Issue date Oct 18, 2005
- Artisan Components, Inc.
- Mark Templeton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for reducing bitline voltage offsets in memory devices
- Patent number 6,944,582
- Issue date Sep 13, 2005
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage current reduction in standard cells
- Patent number 6,941,525
- Issue date Sep 6, 2005
- Artisan Components, Inc.
- Dhrumil Gandhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing write power consumption in random...
- Patent number 6,934,213
- Issue date Aug 23, 2005
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage tolerant circuit for protecting an input buffer
- Patent number 6,924,687
- Issue date Aug 2, 2005
- Artisan Components, Inc.
- Brian Reed
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memories having reduced bitline voltage offsets
- Patent number 6,915,251
- Issue date Jul 5, 2005
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Negatively charged wordline for reduced subthreshold current
- Patent number 6,865,119
- Issue date Mar 8, 2005
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for identification of faulty or weak functional logic elemen...
- Patent number 6,862,721
- Issue date Mar 1, 2005
- Artisan Components, Inc.
- Mark Templeton
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for row decode in a multiport memory
- Patent number 6,833,624
- Issue date Dec 21, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for low area self-timing in memory devices
- Patent number 6,788,615
- Issue date Sep 7, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for voltage clamping in feedback amplifiers us...
- Patent number 6,750,712
- Issue date Jun 15, 2004
- Artisan Components Inc.
- Chinh L. Hoang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage differential signaling circuit with mid-point bias
- Patent number 6,731,135
- Issue date May 4, 2004
- Artisan Components, Inc.
- Michael J. Brunolli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-voltage differential I/O device
- Patent number 6,696,852
- Issue date Feb 24, 2004
- Artisan Components, Inc.
- Michael J. Brunolli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dense metal programmable ROM with the terminals of a programmed mem...
- Patent number 6,674,661
- Issue date Jan 6, 2004
- Artisan Components, Inc.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for identification of faulty or weak memory cells...
- Patent number 6,667,917
- Issue date Dec 23, 2003
- Artisan Components, Inc.
- Mark Templeton
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing process-induced charge buildup
- Patent number 6,639,286
- Issue date Oct 28, 2003
- Artisan Components, Inc.
- Ali Akbar Iranmanesh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for setup and hold characterization in integrated...
- Patent number 6,640,330
- Issue date Oct 28, 2003
- Artisan Components, Inc.
- Hemant Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero power fuse sensing circuit for redundancy applications in memo...
- Patent number 6,618,311
- Issue date Sep 9, 2003
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Load independent single ended sense amplifier
- Patent number 6,597,613
- Issue date Jul 22, 2003
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell architecture with local interconnect and method for making same
- Patent number 6,594,813
- Issue date Jul 15, 2003
- Artisan Components, Inc.
- Dhrumil Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a dense metal programmable ROM
- Patent number 6,569,714
- Issue date May 27, 2003
- Artisan Components, Inc.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip input/output cell design and automated generatio...
- Patent number 6,550,047
- Issue date Apr 15, 2003
- Artisan Components, Inc.
- Scott T. Becker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a dense metal programmable ROM
- Patent number 6,542,396
- Issue date Apr 1, 2003
- Artisan Components, Inc.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a dense metal programmable ROM
- Patent number 6,525,954
- Issue date Feb 25, 2003
- Artisan Components, Inc.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for designing standard cell transistor structures
- Patent number 6,477,695
- Issue date Nov 5, 2002
- Artisan Components, Inc.
- Dhrumil Gandhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for eliminating bitline voltage offsets in mem...
- Patent number 6,470,304
- Issue date Oct 22, 2002
- Artisan Components, Inc.
- James C. Mali
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell architecture with local interconnect and method for making same
- Patent number 6,448,631
- Issue date Sep 10, 2002
- Artisan Components, Inc.
- Dhrumil Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Input/output cell generator
- Patent number 6,446,250
- Issue date Sep 3, 2002
- Artisan Components, Inc.
- Scott T. Becker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Dynamically adaptable memory
- Publication number 20050237823
- Publication date Oct 27, 2005
- Artisan Components, Inc.
- Robert C. Aitken
- G11 - INFORMATION STORAGE
Information Patent Application
Feed-forward circuit for reducing delay through an input buffer
- Publication number 20050156642
- Publication date Jul 21, 2005
- Artisan Components, Inc.
- Scott T. Becker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual port memory core cell architecture with matched bit line capac...
- Publication number 20050121810
- Publication date Jun 9, 2005
- Artisan Components, Inc.
- Jim Mali
- G11 - INFORMATION STORAGE
Information Patent Application
I/O buffer with wide range voltage translator
- Publication number 20050068070
- Publication date Mar 31, 2005
- ARTISAN COMPONENTS, INC.
- Jan C. Diffenderfer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Yield maximization in the manufacture of integrated circuits
- Publication number 20050066294
- Publication date Mar 24, 2005
- Artisan Components, Inc.
- Mark Templeton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage tolerant circuit for protecting an input buffer
- Publication number 20050024101
- Publication date Feb 3, 2005
- Artisan Components, Inc.
- Brian Reed
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for reducing write power consumption in random...
- Publication number 20040252572
- Publication date Dec 16, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Application
Leakage current reduction in standard cells
- Publication number 20040243946
- Publication date Dec 2, 2004
- Artisan Components, Inc.
- Dhrumil Gandhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for row decode in a multiport memory
- Publication number 20040155343
- Publication date Aug 12, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Application
High density beta ratio independent core cell
- Publication number 20040156228
- Publication date Aug 12, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR LOW AREA SELF-TIMING IN MEMORY DEVICES
- Publication number 20040156261
- Publication date Aug 12, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Application
Negatively charged wordline for reduced subthreshold current
- Publication number 20040156244
- Publication date Aug 12, 2004
- Artisan Components, Inc.
- Scott T. Becker
- G11 - INFORMATION STORAGE
Information Patent Application
Method for identification of faulty or weak functional logic elemen...
- Publication number 20040062095
- Publication date Apr 1, 2004
- Artisan Components, Inc.
- Mark Templeton
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR IDENTIFICATION OF FAULTY OR WEAK MEMORY CELLS...
- Publication number 20040004872
- Publication date Jan 8, 2004
- Artisan Components, Inc.
- Mark Templeton
- G11 - INFORMATION STORAGE
Information Patent Application
Memories having reduced bitline voltage offsets
- Publication number 20020056071
- Publication date May 9, 2002
- ARTISAN COMPONENTS, INC.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for reducing bitline voltage offsets in memory devices
- Publication number 20020056072
- Publication date May 9, 2002
- ARTISAN COMPONENTS, INC.
- Scott T. Becker
- H01 - BASIC ELECTRIC ELEMENTS

Trademarklast 30 trademarks

Information Trademark
75432315 - PROCESS-PERFECTION
- Serial number 75432315
- Filing date Feb 11, 1998
- Artisan Components, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
75432316 - ARTISAN COMPONENTS
- Serial number 75432316
- Registration number 2301489
- Filing date Feb 11, 1998
- Artisan Components, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
75432318 - ARTISAN
- Serial number 75432318
- Registration number 2601372
- Filing date Feb 11, 1998
- Artisan Components, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments
Information Trademark
75432317 - PROCESS-PERFECT
- Serial number 75432317
- Registration number 2605064
- Filing date Feb 11, 1998
- Artisan Components, Inc.
- 9 - Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, signalling, checking (supervision), life-saving and teaching apparatus and instruments

Artisan Components, Inc.

Organization

Business Address

Mailing Address

State Location

State of Incorporation

Patents Grantslast 30 patents

System and method for assured built in self repair of memories

Memory column redundancy circuitry and method for implementing the...

Yield maximization in the manufacture of integrated circuits

Methods for reducing bitline voltage offsets in memory devices

Leakage current reduction in standard cells

Method and apparatus for reducing write power consumption in random...

Voltage tolerant circuit for protecting an input buffer

Memories having reduced bitline voltage offsets

Negatively charged wordline for reduced subthreshold current

Method for identification of faulty or weak functional logic elemen...

System and method for row decode in a multiport memory

System and method for low area self-timing in memory devices

Method and apparatus for voltage clamping in feedback amplifiers us...

Low voltage differential signaling circuit with mid-point bias

Low-voltage differential I/O device

Dense metal programmable ROM with the terminals of a programmed mem...

System and method for identification of faulty or weak memory cells...

Method and apparatus for reducing process-induced charge buildup

System and method for setup and hold characterization in integrated...

Zero power fuse sensing circuit for redundancy applications in memo...

Load independent single ended sense amplifier

Cell architecture with local interconnect and method for making same

Method and apparatus for a dense metal programmable ROM

Semiconductor chip input/output cell design and automated generatio...

Method and apparatus for a dense metal programmable ROM

Method and apparatus for a dense metal programmable ROM

Methods for designing standard cell transistor structures

Method and apparatus for eliminating bitline voltage offsets in mem...

Cell architecture with local interconnect and method for making same

Input/output cell generator

Patents Applicationslast 30 patents

Dynamically adaptable memory

Feed-forward circuit for reducing delay through an input buffer

Dual port memory core cell architecture with matched bit line capac...

I/O buffer with wide range voltage translator

Yield maximization in the manufacture of integrated circuits

Voltage tolerant circuit for protecting an input buffer

Method and apparatus for reducing write power consumption in random...

Leakage current reduction in standard cells

System and method for row decode in a multiport memory

High density beta ratio independent core cell

SYSTEM AND METHOD FOR LOW AREA SELF-TIMING IN MEMORY DEVICES

Negatively charged wordline for reduced subthreshold current

Method for identification of faulty or weak functional logic elemen...

SYSTEM AND METHOD FOR IDENTIFICATION OF FAULTY OR WEAK MEMORY CELLS...

Memories having reduced bitline voltage offsets

Methods for reducing bitline voltage offsets in memory devices

Trademarklast 30 trademarks

75432315 - PROCESS-PERFECTION

75432316 - ARTISAN COMPONENTS

75432318 - ARTISAN

75432317 - PROCESS-PERFECT