Anand Murthy

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-all-around integrated circuit structures having embedded GeSnB...
- Patent number 12,272,727
- Issue date Apr 8, 2025
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned interconnect structures and methods of fabrication
- Patent number 12,266,570
- Issue date Apr 1, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures having germanium-based channels
- Patent number 12,255,234
- Issue date Mar 18, 2025
- Intel Corporation
- Siddharth Chouksey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 12,237,420
- Issue date Feb 25, 2025
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having nanowires with...
- Patent number 12,206,027
- Issue date Jan 21, 2025
- Intel Corporation
- Glenn Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual contact process with stacked metal layers
- Patent number 12,170,319
- Issue date Dec 17, 2024
- Intel Corporation
- Kevin Cook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having germanium-dope...
- Patent number 12,166,124
- Issue date Dec 10, 2024
- Intel Corporation
- Ryan Hickey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having source or drai...
- Patent number 12,159,901
- Issue date Dec 3, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a placeholder for backside contact formation for transistor...
- Patent number 12,148,751
- Issue date Nov 19, 2024
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance approaches for fabricating contacts and the resultin...
- Patent number 12,119,387
- Issue date Oct 15, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial source/drain regions for NMOS
- Patent number 12,094,881
- Issue date Sep 17, 2024
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for achieving multiple transistor fin dimensions on a si...
- Patent number 12,046,600
- Issue date Jul 23, 2024
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures including a titanium silicide material
- Patent number 12,046,654
- Issue date Jul 23, 2024
- Intel Corporation
- Dan S. Lavric
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned 3-D epitaxial structures for MOS device fabrication
- Patent number 12,046,517
- Issue date Jul 23, 2024
- Tahoe Research, LTD.
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with low resistivity
- Patent number 12,027,585
- Issue date Jul 2, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with high germanium concentration cappin...
- Patent number 12,027,417
- Issue date Jul 2, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for achieving multiple transistor fin dimensions on a si...
- Patent number 12,021,081
- Issue date Jun 25, 2024
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 12,021,149
- Issue date Jun 25, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors with gate electrode self-aligned to semico...
- Patent number 11,996,447
- Issue date May 28, 2024
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having embedded GeSnB...
- Patent number 11,990,513
- Issue date May 21, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel structures with sub-fin dopant diffusion blocking layers
- Patent number 11,984,449
- Issue date May 14, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having germanium nano...
- Patent number 11,978,784
- Issue date May 7, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures for germanium N-channel devices
- Patent number 11,973,143
- Issue date Apr 30, 2024
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit contact structures
- Patent number 11,942,526
- Issue date Mar 26, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with vertical trenches
- Patent number 11,935,887
- Issue date Mar 19, 2024
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top gate recessed channel CMOS thin film transistor in the back end...
- Patent number 11,929,320
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures having germanium-based channels
- Patent number 11,923,421
- Issue date Mar 5, 2024
- Intel Corporation
- Siddharth Chouksey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with isolation below source and drain
- Patent number 11,923,410
- Issue date Mar 5, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Publication number 20250112120
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...
- Publication number 20250113595
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH...
- Publication number 20250113550
- Publication date Apr 3, 2025
- Intel Corporation
- Glenn GLASS
Information Patent Application
TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER
- Publication number 20250113559
- Publication date Apr 3, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Publication number 20250107175
- Publication date Mar 27, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Publication number 20250107107
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Publication number 20250107108
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
- Publication number 20250107156
- Publication date Mar 27, 2025
- Intel Corporation
- Chiao-Ti Huang
Information Patent Application
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Publication number 20250104760
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
- Publication number 20250107212
- Publication date Mar 27, 2025
- Intel Corporation
- Yang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...
- Publication number 20250095693
- Publication date Mar 20, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
- Publication number 20250096114
- Publication date Mar 20, 2025
- Intel Corporation
- Robin Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...
- Publication number 20250098179
- Publication date Mar 20, 2025
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
- Publication number 20250098260
- Publication date Mar 20, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
- Publication number 20250087530
- Publication date Mar 13, 2025
- Intel Corporation
- Chiao-Ti Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE
- Publication number 20250089310
- Publication date Mar 13, 2025
- Intel Corporation
- Ting-Hsiang Hung
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...
- Publication number 20250048698
- Publication date Feb 6, 2025
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR...
- Publication number 20250022878
- Publication date Jan 16, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED L...
- Publication number 20250006806
- Publication date Jan 2, 2025
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH ANTIMONY AND PHOSPHORUS DOPED EPITAXIAL SOURCE/DRA...
- Publication number 20250006790
- Publication date Jan 2, 2025
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL FLOATING BODY MEMORY
- Publication number 20250008723
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT
- Publication number 20240431092
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
Information Patent Application
MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS
- Publication number 20240431117
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...
- Publication number 20240429162
- Publication date Dec 26, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION
- Publication number 20240379453
- Publication date Nov 14, 2024
- Tahoe Research, Ltd.
- Glenn A. GLASS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...
- Publication number 20240347610
- Publication date Oct 17, 2024
- Intel Corporation
- Koustav GANGULY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES INCLUDING A TITANIUM SILICIDE MATERIAL
- Publication number 20240332392
- Publication date Oct 3, 2024
- Intel Corporation
- Dan S. LAVRIC
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240332394
- Publication date Oct 3, 2024
- Intel Corporation
- David N. GOLDSTEIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT
- Publication number 20240321859
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LONG CHANNEL FIN TRANSISTORS IN NANORIBBON-BASED DEVICES
- Publication number 20240321987
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS

Anand Murthy

Person

Patents Grantslast 30 patents

Gate-all-around integrated circuit structures having embedded GeSnB...

Self-aligned interconnect structures and methods of fabrication

Integrated circuit structures having germanium-based channels

Fin smoothing and integrated circuit structures resulting therefrom

Gate-all-around integrated circuit structures having nanowires with...

Dual contact process with stacked metal layers

Gate-all-around integrated circuit structures having germanium-dope...

Gate-all-around integrated circuit structures having source or drai...

Use of a placeholder for backside contact formation for transistor...

Low resistance approaches for fabricating contacts and the resultin...

Interconnect techniques for electrically connecting source/drain re...

Arsenic-doped epitaxial source/drain regions for NMOS

Techniques for achieving multiple transistor fin dimensions on a si...

Integrated circuit structures including a titanium silicide material

Self-aligned 3-D epitaxial structures for MOS device fabrication

Source or drain structures with low resistivity

Source or drain structures with high germanium concentration cappin...

Techniques for achieving multiple transistor fin dimensions on a si...

Fin smoothing and integrated circuit structures resulting therefrom

Field effect transistors with gate electrode self-aligned to semico...

Three-dimensional integrated circuits (3DICs) including bottom gate...

Gate-all-around integrated circuit structures having embedded GeSnB...

Channel structures with sub-fin dopant diffusion blocking layers

Gate-all-around integrated circuit structures having germanium nano...

Source or drain structures for germanium N-channel devices

Integrated circuit contact structures

Source or drain structures with vertical trenches

Top gate recessed channel CMOS thin film transistor in the back end...

Integrated circuit structures having germanium-based channels

Transistor with isolation below source and drain

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING

MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH...

TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS

STACKED MEMORY LAYERS WITH UNIFORM ACCESS

MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION

DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS

STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE

AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...

VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING

MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...

INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS

LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES

THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...

USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR...

HIGH CONDUCTIVITY TRANSISTOR CONTACTS COMPRISING GALLIUM ENRICHED L...

TRANSISTORS WITH ANTIMONY AND PHOSPHORUS DOPED EPITAXIAL SOURCE/DRA...

THREE-DIMENSIONAL FLOATING BODY MEMORY

MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT

MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS

INTEGRATED CIRCUIT DEVICES WITH CONDUCTIVE LINES EXTENDING OVER SCR...

SELF-ALIGNED 3-D EPITAXIAL STRUCTURES FOR MOS DEVICE FABRICATION

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...

INTEGRATED CIRCUIT STRUCTURES INCLUDING A TITANIUM SILICIDE MATERIAL

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT

LONG CHANNEL FIN TRANSISTORS IN NANORIBBON-BASED DEVICES