Anand Murthy

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integration methods to fabricate internal spacers for nanowire devices
- Patent number 12,363,967
- Issue date Jul 15, 2025
- Sony Group Corporation
- Seiyon Kim
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Device, method and system to provide a stressed channel of a transi...
- Patent number 12,349,420
- Issue date Jul 1, 2025
- Intel Corporation
- Rishabh Mehandru
Information Patent Grant
Source or drain structures with vertical trenches
- Patent number 12,342,611
- Issue date Jun 24, 2025
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact resistance reduction in transistor devices with metallizati...
- Patent number 12,342,574
- Issue date Jun 24, 2025
- Intel Corporation
- Koustav Ganguly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanoribbon sub-fin isolation by backside Si substrate removal etch...
- Patent number 12,328,920
- Issue date Jun 10, 2025
- Intel Corporation
- William Hsu
Information Patent Grant
Low resistance and reduced reactivity approaches for fabricating co...
- Patent number 12,328,927
- Issue date Jun 10, 2025
- Intel Coporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having doped epitaxial region and its methods...
- Patent number 12,294,027
- Issue date May 6, 2025
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High aspect ratio source or drain structures with abrupt dopant pro...
- Patent number 12,288,808
- Issue date Apr 29, 2025
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with isolation below source and drain
- Patent number 12,288,803
- Issue date Apr 29, 2025
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having embedded GeSnB...
- Patent number 12,272,727
- Issue date Apr 8, 2025
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned interconnect structures and methods of fabrication
- Patent number 12,266,570
- Issue date Apr 1, 2025
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures having germanium-based channels
- Patent number 12,255,234
- Issue date Mar 18, 2025
- Intel Corporation
- Siddharth Chouksey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 12,237,420
- Issue date Feb 25, 2025
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having nanowires with...
- Patent number 12,206,027
- Issue date Jan 21, 2025
- Intel Corporation
- Glenn Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual contact process with stacked metal layers
- Patent number 12,170,319
- Issue date Dec 17, 2024
- Intel Corporation
- Kevin Cook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having germanium-dope...
- Patent number 12,166,124
- Issue date Dec 10, 2024
- Intel Corporation
- Ryan Hickey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having source or drai...
- Patent number 12,159,901
- Issue date Dec 3, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a placeholder for backside contact formation for transistor...
- Patent number 12,148,751
- Issue date Nov 19, 2024
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance approaches for fabricating contacts and the resultin...
- Patent number 12,119,387
- Issue date Oct 15, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial source/drain regions for NMOS
- Patent number 12,094,881
- Issue date Sep 17, 2024
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for achieving multiple transistor fin dimensions on a si...
- Patent number 12,046,600
- Issue date Jul 23, 2024
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures including a titanium silicide material
- Patent number 12,046,654
- Issue date Jul 23, 2024
- Intel Corporation
- Dan S. Lavric
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned 3-D epitaxial structures for MOS device fabrication
- Patent number 12,046,517
- Issue date Jul 23, 2024
- Tahoe Research, LTD.
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with low resistivity
- Patent number 12,027,585
- Issue date Jul 2, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with high germanium concentration cappin...
- Patent number 12,027,417
- Issue date Jul 2, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin smoothing and integrated circuit structures resulting therefrom
- Patent number 12,021,149
- Issue date Jun 25, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for achieving multiple transistor fin dimensions on a si...
- Patent number 12,021,081
- Issue date Jun 25, 2024
- Intel Corporation
- Glenn A. Glass
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistors with gate electrode self-aligned to semico...
- Patent number 11,996,447
- Issue date May 28, 2024
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC GATE WALL AND DIELE...
- Publication number 20250227988
- Publication date Jul 10, 2025
- Intel Corporation
- Mohit K. HARAN
Information Patent Application
CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...
- Publication number 20250227956
- Publication date Jul 10, 2025
- Intel Corporation
- Koustav GANGULY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH VARIED EPITAXIAL SOURCE OR DRAIN...
- Publication number 20250220870
- Publication date Jul 3, 2025
- Intel Corporation
- Chang Wan HAN
Information Patent Application
METAL-ALL-AROUND CONTACT STRUCTURE COUPLED WITH A SOURCE OR DRAIN R...
- Publication number 20250212463
- Publication date Jun 26, 2025
- Intel Corporation
- Robin Chao
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH DIELECTRIC CUT AT N-P BOUNDARY
- Publication number 20250204035
- Publication date Jun 19, 2025
- Intel Corporation
- Yang Zhang
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE CONTACTS AND ASYMMETRIC...
- Publication number 20250194179
- Publication date Jun 12, 2025
- Tao Chu
Information Patent Application
CONDUCTIVE VIA WITH FRONT-SIDE AND BACK-SIDE CONNECTIONS WITH A SOU...
- Publication number 20250194211
- Publication date Jun 12, 2025
- Intel Corporation
- Ting-Hsiang Hung
Information Patent Application
UNIAXIAL DUAL STRAIN IN RIBBONIZED CHANNEL
- Publication number 20250194223
- Publication date Jun 12, 2025
- Intel Corporation
- Dan S. Lavric
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH TRANSISTOR GATE-CHANNEL ARRANGEM...
- Publication number 20250194070
- Publication date Jun 12, 2025
- Tao Chu
Information Patent Application
BACK-SIDE NANORIBBON REMOVAL
- Publication number 20250176255
- Publication date May 29, 2025
- Intel Corporation
- Chiao-Ti Huang
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES
- Publication number 20250169130
- Publication date May 22, 2025
- Intel Corporation
- Tao Chu
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS
- Publication number 20250159953
- Publication date May 15, 2025
- Intel Corporation
- Tahir Ghani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20250142870
- Publication date May 1, 2025
- Intel Corporation
- Cory BOMBERGER
Information Patent Application
INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS
- Publication number 20250142948
- Publication date May 1, 2025
- Intel Corporation
- Robin Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING
- Publication number 20250112120
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...
- Publication number 20250113595
- Publication date Apr 3, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH...
- Publication number 20250113550
- Publication date Apr 3, 2025
- Intel Corporation
- Glenn GLASS
Information Patent Application
TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER
- Publication number 20250113559
- Publication date Apr 3, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS
- Publication number 20250107175
- Publication date Mar 27, 2025
- Intel Corporation
- Tao CHU
Information Patent Application
STACKED MEMORY LAYERS WITH UNIFORM ACCESS
- Publication number 20250107107
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION
- Publication number 20250107108
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS
- Publication number 20250107156
- Publication date Mar 27, 2025
- Intel Corporation
- Chiao-Ti Huang
Information Patent Application
STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE
- Publication number 20250104760
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT
- Publication number 20250107212
- Publication date Mar 27, 2025
- Intel Corporation
- Yang Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...
- Publication number 20250095693
- Publication date Mar 20, 2025
- Intel Corporation
- Abhishek A. Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING
- Publication number 20250096114
- Publication date Mar 20, 2025
- Intel Corporation
- Robin Chao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...
- Publication number 20250098179
- Publication date Mar 20, 2025
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS
- Publication number 20250098260
- Publication date Mar 20, 2025
- Intel Corporation
- Guowei XU
Information Patent Application
LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
- Publication number 20250087530
- Publication date Mar 13, 2025
- Intel Corporation
- Chiao-Ti Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE
- Publication number 20250089310
- Publication date Mar 13, 2025
- Intel Corporation
- Ting-Hsiang Hung

Anand Murthy

Person

Patents Grantslast 30 patents

Integration methods to fabricate internal spacers for nanowire devices

Device, method and system to provide a stressed channel of a transi...

Source or drain structures with vertical trenches

Contact resistance reduction in transistor devices with metallizati...

Nanoribbon sub-fin isolation by backside Si substrate removal etch...

Low resistance and reduced reactivity approaches for fabricating co...

Semiconductor device having doped epitaxial region and its methods...

High aspect ratio source or drain structures with abrupt dopant pro...

Transistor with isolation below source and drain

Gate-all-around integrated circuit structures having embedded GeSnB...

Self-aligned interconnect structures and methods of fabrication

Integrated circuit structures having germanium-based channels

Fin smoothing and integrated circuit structures resulting therefrom

Gate-all-around integrated circuit structures having nanowires with...

Dual contact process with stacked metal layers

Gate-all-around integrated circuit structures having germanium-dope...

Gate-all-around integrated circuit structures having source or drai...

Use of a placeholder for backside contact formation for transistor...

Low resistance approaches for fabricating contacts and the resultin...

Interconnect techniques for electrically connecting source/drain re...

Arsenic-doped epitaxial source/drain regions for NMOS

Techniques for achieving multiple transistor fin dimensions on a si...

Integrated circuit structures including a titanium silicide material

Self-aligned 3-D epitaxial structures for MOS device fabrication

Source or drain structures with low resistivity

Source or drain structures with high germanium concentration cappin...

Fin smoothing and integrated circuit structures resulting therefrom

Techniques for achieving multiple transistor fin dimensions on a si...

Field effect transistors with gate electrode self-aligned to semico...

Three-dimensional integrated circuits (3DICs) including bottom gate...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC GATE WALL AND DIELE...

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...

INTEGRATED CIRCUIT STRUCTURE WITH VARIED EPITAXIAL SOURCE OR DRAIN...

METAL-ALL-AROUND CONTACT STRUCTURE COUPLED WITH A SOURCE OR DRAIN R...

INTEGRATED CIRCUIT DEVICE WITH DIELECTRIC CUT AT N-P BOUNDARY

INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE CONTACTS AND ASYMMETRIC...

CONDUCTIVE VIA WITH FRONT-SIDE AND BACK-SIDE CONNECTIONS WITH A SOU...

UNIAXIAL DUAL STRAIN IN RIBBONIZED CHANNEL

INTEGRATED CIRCUIT STRUCTURES WITH TRANSISTOR GATE-CHANNEL ARRANGEM...

BACK-SIDE NANORIBBON REMOVAL

INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENT NANORIBBON THICKNESSES

INTEGRATED CIRCUIT DEVICES WITH ANGLED TRANSISTORS

FIN SMOOTHING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

INTEGRATED CIRCUIT DEVICES WITH SELF-ALIGNED VIA-TO-JUMPER CONNECTIONS

INTEGRATED CIRCUIT STRUCTURE WITH DEEP VIA BAR WIDTH TUNING

MULTIPLE VOLTAGE THRESHOLD INTEGRATED CIRCUIT STRUCTURE WITH LOCAL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NANOWIRES WITH...

TRENCH CONTACT STRUCTURE WITH ETCH-STOP LAYER

INTEGRATED CIRCUIT STRUCTURES HAVING REDUCED LOCAL LAYOUT EFFECTS

STACKED MEMORY LAYERS WITH UNIFORM ACCESS

MEMORY LAYERS BONDED TO LOGIC LAYERS WITH INCLINATION

DIELECTRIC ISOLATION BETWEEN EPITAXIAL REGIONS AND SUBFIN REGIONS

STACKED MEMROY LAYERS WITH GLOBAL BIT LINE OR GLOBAL WORD LINE

AIRGAP SPACER BETWEEN GATE ELECTRODE AND SOURCE OR DRAIN CONTACT

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO...

VIA STRUCTURE WITH IMPROVED SUBSTRATE GROUNDING

MEMORY LAYERS AT OPPOSING SIDES OF A COMPLEMENTARY METAL-OXIDE SEMI...

INTEGRATED CIRCUIT STRUCTURES WITH PATCH SPACERS

LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES

THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE