Dale Wong

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical storage architecture for reconfigurable logic configur...
- Patent number 7,502,920
- Issue date Mar 10, 2009
- Intel Corporation
- Christopher E. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array core cell with efficient logic packing
- Patent number 7,009,421
- Issue date Mar 7, 2006
- Agate Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection network for a field programmable gate array
- Patent number 6,940,308
- Issue date Sep 6, 2005
- Leopard Logic Inc.
- Dale Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable interface for field programmable gate array cores
- Patent number 6,888,371
- Issue date May 3, 2005
- Leopard Logic, Inc.
- Dale Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable gate array core cell with efficient logic packing
- Patent number 6,801,052
- Issue date Oct 5, 2004
- Leopard Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for compiling high level programming languages into embedded...
- Patent number 6,708,325
- Issue date Mar 16, 2004
- Intel Corporation
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnection network for a field programmable gate array
- Patent number 6,693,456
- Issue date Feb 17, 2004
- Leopard Logic Inc.
- Dale Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable logic for table lookup
- Patent number 6,389,579
- Issue date May 14, 2002
- Chameleon Systems
- Christopher E. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Behavioral silicon construct architecture and mapping
- Patent number 6,298,472
- Issue date Oct 2, 2001
- Chameleon Systems, Inc.
- Christopher E. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated processor and programmable data path chip for reconfigur...
- Patent number 6,282,627
- Issue date Aug 28, 2001
- Chameleon Systems, Inc.
- Dale Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated processor and programmable data path chip for reconfigur...
- Patent number 5,970,254
- Issue date Oct 19, 1999
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for compiling high level programming languages into an integ...
- Patent number 5,966,534
- Issue date Oct 12, 1999
- Laurence H. Cooke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for regular placement of data path components in VLSI circuits
- Patent number 5,359,538
- Issue date Oct 25, 1994
- VLSI Technology, Inc.
- Siu-Tong Hui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimally placing components of a VLSI circuit
- Patent number 5,349,536
- Issue date Sep 20, 1994
- VLSI Technology, Inc.
- Sunil V. Ashtaputre
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for placement of connectors used interconnecting circuit com...
- Patent number 5,309,370
- Issue date May 3, 1994
- VLSI Technology, Inc.
- Dale M. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for placement of circuit components in an integrated circuit
- Patent number 5,208,759
- Issue date May 4, 1993
- VLSI Technology, Inc.
- Dale M. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for partitioning of connected circuit components before plac...
- Patent number 5,202,840
- Issue date Apr 13, 1993
- VLSI Technology, Inc.
- Dale M. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptable topologies used in routing of ground and power networks o...
- Patent number 5,187,864
- Issue date Feb 23, 1993
- VLSI Technology, Inc.
- Daniel R. Brasen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Hierarchical storage architecture for reconfigurable logic configur...
- Publication number 20050204122
- Publication date Sep 15, 2005
- Christopher E. Phillips
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Field programmable gate array core cell with efficient logic packing
- Publication number 20050040849
- Publication date Feb 24, 2005
- Leopard Logic, Inc.
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection network for a field programmable gate array
- Publication number 20040150422
- Publication date Aug 5, 2004
- Leopard Logic, Inc.
- Dale Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Via programmable gate array interconnect architecture
- Publication number 20040105207
- Publication date Jun 3, 2004
- Leopard Logic, Inc.
- Dieter Spaderna
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interface architecture for embedded field programmable gate array c...
- Publication number 20030212940
- Publication date Nov 13, 2003
- Dale Wong
- G01 - MEASURING TESTING
Information Patent Application
Programmable interface for field programmable gate array cores
- Publication number 20030098710
- Publication date May 29, 2003
- Dale Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Field programmable gate array core cell with efficient logic packing
- Publication number 20030085733
- Publication date May 8, 2003
- Daniel J. Pugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical mux based integrated circuit interconnect architecture...
- Publication number 20030039262
- Publication date Feb 27, 2003
- Leopard Logic Inc.
- Dale Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD FOR COMPILING HIGH LEVEL PROGRAMMING LANGUAGES
- Publication number 20030014743
- Publication date Jan 16, 2003
- LAURENCE H. COOKE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure intellectual property for a generated field programmable gat...
- Publication number 20020150252
- Publication date Oct 17, 2002
- Leopard Logic, Inc.
- Dale Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnection network for a Field Progammable Gate Array
- Publication number 20020113619
- Publication date Aug 22, 2002
- Leopard Logic, Inc.
- Dale Wong
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Hierarchical storage architecture for reconfigurable logic configur...

Field programmable gate array core cell with efficient logic packing

Interconnection network for a field programmable gate array

Programmable interface for field programmable gate array cores

Field programmable gate array core cell with efficient logic packing

Method for compiling high level programming languages into embedded...

Interconnection network for a field programmable gate array

Reconfigurable logic for table lookup

Behavioral silicon construct architecture and mapping

Integrated processor and programmable data path chip for reconfigur...

Integrated processor and programmable data path chip for reconfigur...

Method for compiling high level programming languages into an integ...

Method for regular placement of data path components in VLSI circuits

Method for optimally placing components of a VLSI circuit

Method for placement of connectors used interconnecting circuit com...

Method for placement of circuit components in an integrated circuit

Method for partitioning of connected circuit components before plac...

Adaptable topologies used in routing of ground and power networks o...

Patents Applicationslast 30 patents

Hierarchical storage architecture for reconfigurable logic configur...

Field programmable gate array core cell with efficient logic packing

Interconnection network for a field programmable gate array

Via programmable gate array interconnect architecture

Interface architecture for embedded field programmable gate array c...

Programmable interface for field programmable gate array cores

Field programmable gate array core cell with efficient logic packing

Hierarchical mux based integrated circuit interconnect architecture...

METHOD FOR COMPILING HIGH LEVEL PROGRAMMING LANGUAGES

Secure intellectual property for a generated field programmable gat...

Interconnection network for a Field Progammable Gate Array