Dominique D'Inverno

Person

Villeneuve Loubet, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Dirty cache line write back policy based on stack size trend inform...
- Patent number 8,539,159
- Issue date Sep 17, 2013
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor computing system having a JAVA stack machine and a...
- Patent number 8,429,383
- Issue date Apr 23, 2013
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro-sequence based security model
- Patent number 8,190,861
- Issue date May 29, 2012
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-aware scheduling of application execution
- Patent number 8,032,891
- Issue date Oct 4, 2011
- Texas Instruments Incorporated
- Gerard Chauvel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Data processing apparatus, system and method
- Patent number 7,941,790
- Issue date May 10, 2011
- Texas Instruments Incorporated
- Gilbert Cabillic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed stack-based RISC processor
- Patent number 7,840,782
- Issue date Nov 23, 2010
- Texas Instruments Incorporated
- Gerard Chauvel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Test and skip processor instruction having at least one register op...
- Patent number 7,840,784
- Issue date Nov 23, 2010
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tasks distribution in a multi-processor including a translation loo...
- Patent number 7,716,673
- Issue date May 11, 2010
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stack register reference control bit in source operand of instruction
- Patent number 7,634,643
- Issue date Dec 15, 2009
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded garbage collection
- Patent number 7,565,385
- Issue date Jul 21, 2009
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saturated arithmetic in a processing unit
- Patent number 7,543,014
- Issue date Jun 2, 2009
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing device driver memory in programming language representation
- Patent number 7,496,930
- Issue date Feb 24, 2009
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory allocation in a multi-processor system
- Patent number 7,434,021
- Issue date Oct 7, 2008
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management of stack-based memory usage in a processor
- Patent number 7,330,937
- Issue date Feb 12, 2008
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management of local variables
- Patent number 7,203,797
- Issue date Apr 10, 2007
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature field controlled scheduling for processing systems
- Patent number 7,174,194
- Issue date Feb 6, 2007
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JAVA DSP acceleration by byte-code optimization
- Patent number 7,146,613
- Issue date Dec 5, 2006
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priority arbitration based on current task and MMU
- Patent number 7,120,715
- Issue date Oct 10, 2006
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to automatically stack and unstack Java local var...
- Patent number 7,069,415
- Issue date Jun 27, 2006
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task based adaptative profiling and debugging
- Patent number 7,062,304
- Issue date Jun 13, 2006
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency in a multi-processor system
- Patent number 6,996,683
- Issue date Feb 7, 2006
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic hardware control for energy management systems using task a...
- Patent number 6,901,521
- Issue date May 31, 2005
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic hardware configuration for energy management systems using...
- Patent number 6,889,330
- Issue date May 3, 2005
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart cache
- Patent number 6,826,652
- Issue date Nov 30, 2004
- Texas Instruments Incorporated
- Gérard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache with multiple fill modes
- Patent number 6,792,508
- Issue date Sep 14, 2004
- Texas Instruments Incorporated
- Gérard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interruptible an re-entrant cache clean range instruction
- Patent number 6,772,326
- Issue date Aug 3, 2004
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache with selective write allocation
- Patent number 6,769,052
- Issue date Jul 27, 2004
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MMU descriptor having big/little endian bit to control the transfer...
- Patent number 6,760,829
- Issue date Jul 6, 2004
- Texas Instruments Incorporated
- Serge Lasserre
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple microprocessors with a shared cache
- Patent number 6,751,706
- Issue date Jun 15, 2004
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with shared translation lookaside buffer
- Patent number 6,742,103
- Issue date May 25, 2004
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Pack instruction
- Publication number 20060026397
- Publication date Feb 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Gilbert Cabillic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unpack instruction
- Publication number 20060026398
- Publication date Feb 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Gilbert Cabillic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically changing the semantic of an instruction
- Publication number 20050033945
- Publication date Feb 10, 2005
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Saturated arithmetic in a processing unit
- Publication number 20050027774
- Publication date Feb 3, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory allocation in a multi-processor system
- Publication number 20040268076
- Publication date Dec 30, 2004
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Embedded garbage collection
- Publication number 20040260732
- Publication date Dec 23, 2004
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accessing device driver memory in programming language representation
- Publication number 20040261085
- Publication date Dec 23, 2004
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unresolved instruction resolution
- Publication number 20040260911
- Publication date Dec 23, 2004
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test and skip processor instruction having at least one register op...
- Publication number 20040153885
- Publication date Aug 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory management of local variables
- Publication number 20040078523
- Publication date Apr 22, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-processor computing system having a JAVA stack machine and a...
- Publication number 20040078550
- Publication date Apr 22, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache coherency in a multi-processor system
- Publication number 20040078528
- Publication date Apr 22, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method to automatically stack and unstack java local var...
- Publication number 20040059893
- Publication date Mar 25, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor that accommodates multiple instruction sets and multiple...
- Publication number 20040024990
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test with immediate and skip processor instruction
- Publication number 20040024997
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mixed stack-based RISC processor
- Publication number 20040024989
- Publication date Feb 5, 2004
- Texas Instruments Incorporated
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Write back policy for memory
- Publication number 20040024792
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for managing memory
- Publication number 20040024969
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Micro-sequence execution in a processor
- Publication number 20040024999
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concurrent task execution in a multi-processor, single operating sy...
- Publication number 20040025161
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for managing memory
- Publication number 20040024970
- Publication date Feb 5, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Application execution profiling in conjunction with a virtual machine
- Publication number 20040010785
- Publication date Jan 15, 2004
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Energy-aware scheduling of application execution
- Publication number 20030217090
- Publication date Nov 20, 2003
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JAVA DSP acceleration by byte-code optimization
- Publication number 20030101208
- Publication date May 29, 2003
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache with selective write allocation
- Publication number 20030101320
- Publication date May 29, 2003
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interruptible and re-entrant cache clean range instruction
- Publication number 20030097550
- Publication date May 22, 2003
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data processing apparatus, system and method
- Publication number 20030079213
- Publication date Apr 24, 2003
- Gilbert Cabillic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Traffic controller using priority and burst control for reducing ac...
- Publication number 20020194441
- Publication date Dec 19, 2002
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple microprocessors with a shared cache
- Publication number 20020073282
- Publication date Jun 13, 2002
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multilevel cache architecture and data transfer
- Publication number 20020069341
- Publication date Jun 6, 2002
- Gerard Chauvel
- G06 - COMPUTING CALCULATING COUNTING

Dominique D'Inverno

Person

Patents Grantslast 30 patents

Dirty cache line write back policy based on stack size trend inform...

Multi-processor computing system having a JAVA stack machine and a...

Micro-sequence based security model

Energy-aware scheduling of application execution

Data processing apparatus, system and method

Mixed stack-based RISC processor

Test and skip processor instruction having at least one register op...

Tasks distribution in a multi-processor including a translation loo...

Stack register reference control bit in source operand of instruction

Embedded garbage collection

Saturated arithmetic in a processing unit

Accessing device driver memory in programming language representation

Memory allocation in a multi-processor system

Management of stack-based memory usage in a processor

Memory management of local variables

Temperature field controlled scheduling for processing systems

JAVA DSP acceleration by byte-code optimization

Priority arbitration based on current task and MMU

System and method to automatically stack and unstack Java local var...

Task based adaptative profiling and debugging

Cache coherency in a multi-processor system

Dynamic hardware control for energy management systems using task a...

Dynamic hardware configuration for energy management systems using...

Smart cache

Cache with multiple fill modes

Interruptible an re-entrant cache clean range instruction

Cache with selective write allocation

MMU descriptor having big/little endian bit to control the transfer...

Multiple microprocessors with a shared cache

Processing system with shared translation lookaside buffer

Patents Applicationslast 30 patents

Pack instruction

Unpack instruction

Dynamically changing the semantic of an instruction

Saturated arithmetic in a processing unit

Memory allocation in a multi-processor system

Embedded garbage collection

Accessing device driver memory in programming language representation

Unresolved instruction resolution

Test and skip processor instruction having at least one register op...

Memory management of local variables

Multi-processor computing system having a JAVA stack machine and a...

Cache coherency in a multi-processor system

System and method to automatically stack and unstack java local var...

Processor that accommodates multiple instruction sets and multiple...

Test with immediate and skip processor instruction

Mixed stack-based RISC processor

Write back policy for memory

Methods and apparatuses for managing memory

Micro-sequence execution in a processor

Concurrent task execution in a multi-processor, single operating sy...

Methods and apparatuses for managing memory

Application execution profiling in conjunction with a virtual machine

Energy-aware scheduling of application execution

JAVA DSP acceleration by byte-code optimization

Cache with selective write allocation

Interruptible and re-entrant cache clean range instruction

Data processing apparatus, system and method

Traffic controller using priority and burst control for reducing ac...

Multiple microprocessors with a shared cache

Multilevel cache architecture and data transfer