Don R. Weiss

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sidecar SRAM for high granularity in floor plan aspect ratio
- Patent number 9,575,891
- Issue date Feb 21, 2017
- Advanced Micro Devices, Inc.
- John R. Riley
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing complimentary state retention
- Patent number 9,159,409
- Issue date Oct 13, 2015
- Advanced Micro Devices, Inc.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
Error detection device and methods thereof
- Patent number 8,276,039
- Issue date Sep 25, 2012
- GlobalFoundries Inc.
- John J. Wuu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SRAM bit cell with self-aligned bidirectional local interconnects
- Patent number 8,076,236
- Issue date Dec 13, 2011
- GLOBALFOUNDRIES Inc.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sensing device for floating body cell memory and method thereof
- Patent number 7,724,578
- Issue date May 25, 2010
- GlobalFoundries Inc.
- Michael A. Dreesen
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for avoiding attempts to access a defective porti...
- Patent number 7,430,145
- Issue date Sep 30, 2008
- Hewlett-Packard Development Company, L.P.
- Donald R. Weiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable weak write test mode (PWWTM) bias generation having lo...
- Patent number 7,133,319
- Issue date Nov 7, 2006
- Hewlett-Packard Development Company, L.P.
- John Wuu
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for calibrating weak write test mode (WWTM)
- Patent number 7,076,376
- Issue date Jul 11, 2006
- Hewlett-Packard Development Company, L.P.
- Donald R Weiss
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for instruction fetch unit
- Patent number 6,832,308
- Issue date Dec 14, 2004
- Intel Corporation
- William G. Sicaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self test for content addressable memory
- Patent number 6,550,034
- Issue date Apr 15, 2003
- Hewlett-Packard Development Company, L.P.
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible cache architecture using modular arrays
- Patent number 6,493,855
- Issue date Dec 10, 2002
- Hewlett-Packard Company
- Donald R Weiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory (SRAM) array central global decoder sys...
- Patent number 6,366,526
- Issue date Apr 2, 2002
- Samuel D Naffziger
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetric RAM cell
- Patent number 6,363,006
- Issue date Mar 26, 2002
- Hewlett-Packard Company
- Samuel D. Naffziger
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-bit comparator
- Patent number 6,292,093
- Issue date Sep 18, 2001
- Hewlett-Packard Company
- Shyang-Tai Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for enabling/disabling SRAM banks for memory access
- Patent number 6,285,579
- Issue date Sep 4, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy programming using addressable scan paths to reduce the n...
- Patent number 6,249,465
- Issue date Jun 19, 2001
- Hewlett-Packard Company
- Donald R Weiss
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed decode system and method for improving static random ac...
- Patent number 6,243,287
- Issue date Jun 5, 2001
- Hewlett-Packard Company
- Samuel D Naffziger
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetric ram cell
- Patent number 6,240,009
- Issue date May 29, 2001
- Hewlett-Packard Company
- Samuel D. Naffziger
- G11 - INFORMATION STORAGE
Information Patent Grant
Register structure with a dual-ended write mechanism
- Patent number 6,226,217
- Issue date May 1, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-ported register structure utilizing a pulse write mechanism
- Patent number 6,208,565
- Issue date Mar 27, 2001
- Hewlett-Packard Company
- Reid James Riedlinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated weak write test mode (WWWTM)
- Patent number 6,192,001
- Issue date Feb 20, 2001
- Hewlett-Packard Company
- Donald R Weiss
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for improving read/write stability of a single...
- Patent number 5,986,923
- Issue date Nov 16, 1999
- Hewlett-Packard Company
- Kevin Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for improving a random access memory (RAM)
- Patent number 5,787,041
- Issue date Jul 28, 1998
- Hewlett-Packard Co.
- J. Michael Hill
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO
- Publication number 20150364168
- Publication date Dec 17, 2015
- Advanced Micro Devices, Inc.
- John R. Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Alternating Wordline Connection in 8T Cells for Improving Resilienc...
- Publication number 20130083591
- Publication date Apr 4, 2013
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH ACTIVE MEMORY AND PASSIVE VARIABLE RESISTIV...
- Publication number 20130083048
- Publication date Apr 4, 2013
- Advanced Micro Devices, Inc.
- Donald R. Weiss
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DIRECT BACKUP OF MEMORY CIRCUITS
- Publication number 20130070513
- Publication date Mar 21, 2013
- Advanced Micro Devices, Inc.
- Donald R. Weiss
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH ON-DIE DISTRIBUTED PROGRAMMABLE PASSIVE VAR...
- Publication number 20130070514
- Publication date Mar 21, 2013
- Advanced Micro Devices, Inc.
- Donald R. Weiss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING COMPLIMENTARY STATE RETENTION
- Publication number 20130069964
- Publication date Mar 21, 2013
- Advanced Micro Devices, Inc.
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH BACKSIDE PASSIVE VARIABLE RESISTANCE MEMORY...
- Publication number 20130051115
- Publication date Feb 28, 2013
- Advanced Micro Devices, Inc.
- William G. En
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICALLY INTEGRATED PASSIVE VARIABLE RESI...
- Publication number 20130051117
- Publication date Feb 28, 2013
- Advanced Micro Devices, Inc.
- William G. En
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT WITH FACE-TO-FACE BONDED PASSIVE VARIABLE RESIST...
- Publication number 20130051116
- Publication date Feb 28, 2013
- Advanced Micro Devices, Inc.
- William G. En
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A RED...
- Publication number 20120173921
- Publication date Jul 5, 2012
- Advanced Micro Devices, Inc.
- John J. WUU
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS
- Publication number 20120037996
- Publication date Feb 16, 2012
- GLOBALFOUNDRIES INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS
- Publication number 20100301482
- Publication date Dec 2, 2010
- GLOBALFOUNDRIES INC.
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ERROR DETECTION DEVICE AND METHODS THEREOF
- Publication number 20100223525
- Publication date Sep 2, 2010
- Advanced Micro Devices, Inc.
- John J. Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sensing device for floating body cell memory and method thereof
- Publication number 20080144367
- Publication date Jun 19, 2008
- Advanced Micro Devices, Inc.
- Michael A. Dreesen
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced bitline leakage current
- Publication number 20070081409
- Publication date Apr 12, 2007
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for avoiding attempts to access a defective porti...
- Publication number 20070079184
- Publication date Apr 5, 2007
- Donald R. Weiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Banked cache with multiplexer
- Publication number 20070014137
- Publication date Jan 18, 2007
- Todd W. Mellinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CALIBRATING WEAK WRITE TEST MODE (WWTM)
- Publication number 20060142962
- Publication date Jun 29, 2006
- Donald R. Weiss
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing power in SRAMs while maintaining cell stability
- Publication number 20060133135
- Publication date Jun 22, 2006
- Jonathan E. Lachman
- G11 - INFORMATION STORAGE
Information Patent Application
Shift redundancy encoding for use with digital memories
- Publication number 20050050400
- Publication date Mar 3, 2005
- John J. Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable weak write test mode (PWWTM) bias generation having lo...
- Publication number 20040260986
- Publication date Dec 23, 2004
- John Wuu
- G11 - INFORMATION STORAGE
Information Patent Application
Bias generation having adjustable range and resolution through meta...
- Publication number 20040257882
- Publication date Dec 23, 2004
- Blaine Stackhouse
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for reducing silent data corruption in storage a...
- Publication number 20040148559
- Publication date Jul 29, 2004
- Eric S. Fetzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data-shifting scheme for utilizing multiple redundant elements
- Publication number 20030026135
- Publication date Feb 6, 2003
- J. Michael Hill
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetric ram cell
- Publication number 20010043486
- Publication date Nov 22, 2001
- Samuel D. Naffziger
- G11 - INFORMATION STORAGE
Information Patent Application
Static random access memory (SRAM) array central global decoder sys...
- Publication number 20010010642
- Publication date Aug 2, 2001
- Samuel D. Naffziger
- G11 - INFORMATION STORAGE

Don R. Weiss

Person

Patents Grantslast 30 patents

Sidecar SRAM for high granularity in floor plan aspect ratio

Method and apparatus for providing complimentary state retention

Error detection device and methods thereof

SRAM bit cell with self-aligned bidirectional local interconnects

Sensing device for floating body cell memory and method thereof

System and method for avoiding attempts to access a defective porti...

Programmable weak write test mode (PWWTM) bias generation having lo...

System and method for calibrating weak write test mode (WWTM)

Apparatus and method for instruction fetch unit

Built-in self test for content addressable memory

Flexible cache architecture using modular arrays

Static random access memory (SRAM) array central global decoder sys...

Asymmetric RAM cell

Multi-bit comparator

System and method for enabling/disabling SRAM banks for memory access

Redundancy programming using addressable scan paths to reduce the n...

Distributed decode system and method for improving static random ac...

Asymmetric ram cell

Register structure with a dual-ended write mechanism

Multi-ported register structure utilizing a pulse write mechanism

Integrated weak write test mode (WWWTM)

Method and apparatus for improving read/write stability of a single...

System and method for improving a random access memory (RAM)

Patents Applicationslast 30 patents

SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO

Alternating Wordline Connection in 8T Cells for Improving Resilienc...

INTEGRATED CIRCUIT WITH ACTIVE MEMORY AND PASSIVE VARIABLE RESISTIV...

METHOD AND APPARATUS FOR DIRECT BACKUP OF MEMORY CIRCUITS

INTEGRATED CIRCUIT WITH ON-DIE DISTRIBUTED PROGRAMMABLE PASSIVE VAR...

METHOD AND APPARATUS FOR PROVIDING COMPLIMENTARY STATE RETENTION

INTEGRATED CIRCUIT WITH BACKSIDE PASSIVE VARIABLE RESISTANCE MEMORY...

INTEGRATED CIRCUIT WITH VERTICALLY INTEGRATED PASSIVE VARIABLE RESI...

INTEGRATED CIRCUIT WITH FACE-TO-FACE BONDED PASSIVE VARIABLE RESIST...

REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A RED...

SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS

SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS

ERROR DETECTION DEVICE AND METHODS THEREOF

Sensing device for floating body cell memory and method thereof

Reduced bitline leakage current

System and method for avoiding attempts to access a defective porti...

Banked cache with multiplexer

SYSTEM AND METHOD FOR CALIBRATING WEAK WRITE TEST MODE (WWTM)

Reducing power in SRAMs while maintaining cell stability

Shift redundancy encoding for use with digital memories

Programmable weak write test mode (PWWTM) bias generation having lo...

Bias generation having adjustable range and resolution through meta...

Method and circuit for reducing silent data corruption in storage a...

Data-shifting scheme for utilizing multiple redundant elements

Asymmetric ram cell

Static random access memory (SRAM) array central global decoder sys...