Patent Application
20130051116
This application is related to co-pending application having docket number 00100.10.0562, filed on even date, having inventors William En et al., titled “INTEGRATED CIRCUIT WITH BACKSIDE PASSIVE VARIABLE RESISTANCE MEMORY AND METHOD FOR MAKING THE SAME”, owned by instant assignee; and co-pending application having docket number 00100.10.0564, filed on even date, having inventors William En et al., titled “INTEGRATED CIRCUIT WITH VERTICALLY INTEGRATED PASSIVE VARIABLE RESISTANCE MEMORY AND METHOD FOR MAKING THE SAME”, owned by instant assignee.
The disclosure relates generally to an integrated circuit and to a method for making the same.
Dynamic random access memory (DRAM) and flash memory are two dominant memory technologies generally accepted to be nearing the end of their scaling lifetime, and the search is on for a replacement that can scale beyond DRAM and flash memory, while maintaining low latency and energy efficiency. Passive variable resistance memory, also known as resistive non-volatile memory, is emerging as a ubiquitous next generation of flash replacement technology (FRT). Passive variable resistance memory includes but is not limited to memristors, phase-change memory, and magnetoresistive memory (e.g., spin-torque transfer magnetoresistive memory). The key behind the passive variable resistance memory is storing state in the form of resistance instead of charge.
Similar to DRAM and flash memory, passive variable resistance memory may be used as on-chip memory integrated with processors, such as central processing units (CPUs) or graphic processing units (GPUs), in the forms of cache memory and/or main memory. It is known to place the passive variable resistance memory either laterally on the same die of the processor or on a separate die connected laterally to the processor die through a circuit board. Either implementation, however, has issues with cost and distance of the memory to where it is needed on the processor. As the passive variable resistance memory and the processor are laterally arranged, the die area and packaging size may be increased, and the memory access may be slowed down due to the relative long lateral connection distance.
Accordingly, there exists a need for an improved integrated circuit with passive variable resistance memory and a method for making the same.
The embodiments will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:
Briefly, in one example, an integrated circuit includes two integrated circuit dies that are face-to-face mounted together. The first integrated circuit die includes passive variable resistance memory, and the second integrated circuit die includes memory control logic (e.g., CMOS logic circuit). The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory on the first integrated circuit die is electrically connected to the memory control logic on the second integrated circuit die through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic on the second integrated circuit die operatively coupled to the memory control logic.
Among other advantages, the method for making the integrated circuit with face-to-face bonded passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. Since the passive variable resistance memory cells and the active semiconductor device (e.g., CMOS transistors) are formed on two separate integrated circuit dies, the design, fabrication, and test complications and cost of the integrated circuit are reduced. For example, the die material of the passive variable resistance memory is not limited to silicon and may be any suitable non-silicon materials; and the two integrated circuit dies may be tested separately before bonding. Other advantages will be recognized by those of ordinary skill in the art.
In one example, the method forms a dielectric layer above the integrated circuit die substrate of the first integrated circuit die. The integrated circuit die substrate of the first integrated circuit die may be, for example, a non-silicon substrate. The method then forms a lower electrode layer above the dielectric layer. For example, the method may pattern the lower electrode layer to form a plurality of word lines for the passive variable resistance memory on the first integrated circuit die. Each word line is electrically connected to the memory control logic on the second integrated circuit die through at least one of the plurality of vias. The method then forms a memory layer above the lower electrode layer. For example, the method may pattern the memory layer to form a plurality of memory regions for each of the plurality of passive variable resistance memory cells on the first integrated circuit die. The method then forms an upper electrode layer above the memory layer. For example, the method may pattern the upper electrode layer to form a plurality of bit lines for the passive variable resistance memory on the first integrated circuit die. Each bit line is electrically connected to the memory control logic on the second integrated circuit die through at least one of the plurality of vias. Each memory region of the memory layer is disposed at a place where each word line and bit line overlap, and each passive variable resistance memory cell may be part of a crosspoint array. In this example, the dielectric layer, lower electrode layer, memory layer, and upper electrode constitute one layer of the passive variable resistance memory cells.
In another example, the method forms multiple layers of passive variable resistance memory cells. For example, the method may form a second dielectric layer above the first upper electrode layer to separate the first and second layers of passive variable resistance memory cells. The method then forms a second lower electrode layer above the second dielectric layer and a second memory layer above the second lower electrode layer. The method also forms a second upper electrode layer above the second memory layer.
In still another example, the method also forms a plurality of through-die vias through the first integrated circuit die. The method then mounts the first integrated circuit die on an integrated circuit package, wherein the processor logic and the memory control logic on the second integrated circuit die are electrically connected to the integrated circuit package through the plurality of through-die vias.
Among other advantages, the method for making the integrated circuit with face-to-face bonded passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. Since the passive variable resistance memory cells and the active semiconductor device (e.g., CMOS transistors) are formed on two separate integrated circuit dies, the design, fabrication, and test complications and cost of the integrated circuit are reduced. For example, the die material of the passive variable resistance memory is not limited to silicon and may be any suitable non-silicon materials; and the two integrated circuit dies may be tested separately before bonding. In addition, compared with known integration solutions, the face-to-face bonded passive variable resistance memory eliminates any die area increase and enables faster memory access by both reducing the connection distance and allowing for the increased number of parallel connections. Moreover, the method for making the integrated circuit with face-to-face bonded passive variable resistance memory provides flexibility for adopting various types of passive variable resistance memory such as but not limited to memristor, phase-change memory, or magnetoresistive memory. Other advantages will be recognized by those of ordinary skill in the art.
In this example, the integrated circuit 108 may include a layer of single-crystal silicon as the integrated circuit die substrate 308 of the second integrated circuit die 302. In other examples, the integrated circuit die substrate 308 may be germanium, silicon on insulator (SOI) such as SiO2 based SOI and silicon on sapphire, compound semiconductor such as GaAs, GaN to name a few, organic semiconductor, or any other suitable semiconductor substrate. The integrated circuit 108 includes processor logic 310 and memory control logic 312 formed on the second integrated circuit die 302. The processor logic 310 and memory control logic 312 are operatively coupled to each other in this example. In this example, the logic 310, 312 is formed directly on top of the integrated circuit die substrate 308 without any intervening structures or layers in between them. However, it is understood that in other examples, intervening structures or layers may be formed between the logic 310, 312 and the integrated circuit die substrate 308. The processor logic 310 and memory control logic 312 include active semiconductor devices that are capable of electrically controlling electron flow, such as but not limited to bipolar or field effect transistors (FET), semiconductor controlled rectifiers (SCR), or triode for alternating current (TRIAC), to name a few. The processor logic 310 and memory control logic 312 may also include passive devices that are incapable of controlling current by means of another electrical signal, such as but not limited to resistors, capacitors, inductors, transformers, transmission lines, or any other suitable passive device. In one example, the processor logic 310 and memory control logic 312 mainly include active CMOS circuits and passive devices (e.g. metal interconnections) constructed in the surface of a thin single-crystal silicon layer. As noted above, the processor logic 302 may include at least one of a CPU having one or multiple cores, a discrete or integrated GPU, an APU, a GPGPU, and any other suitable logic. In one example, only passive devices such as passive variable resistance memory or metal interconnections are formed on the first integrated circuit die 300, and no active semiconductor device (e.g., CMOS transistors) is formed on the first integrated circuit die 300. It is understood, however, that in other examples, the integrated circuit 108 may not include the processor logic 310 on the second integrated circuit die 302. Instead, the integrated circuit 108 may only include the memory control logic 312 on the second integrated circuit die 302, and the processor 102 may include another integrated circuit that has processor logic operatively coupled to the memory control logic 312 on the integrated circuit 108 through wire bonding or any other suitable connections known in the art.
In this example, the front side of the second integrated circuit die 302 on which the processor logic 310 and memory control logic 312 are formed is mounted on the front side of the first integrated circuit doe 300 on which the passive variable resistance memory 306 is formed. Moreover, the passive variable resistance memory 306 serves as on-chip memory for the processor 102, such as processor registers, on-chip cache memory (e.g., L1, L2, and L3 caches), or main memory. Each memory cell of the passive variable resistance memory 306 on the first integrated circuit die 300 is electrically connected to the memory control logic 312 on the second integrated circuit die 302 through at least one of a plurality of vias 314, 316. The memory control logic 312 on the second integrated circuit die 302 controls the operation (e.g., write/read) of the passive variable resistance memory 306 on the first integrated circuit die 300 by control signals (e.g., voltage/current) through the vias 314, 316. Although two vias 314, 316 are shown in
In this example, since the first and second integrated circuit dies 300, 302 are face-to-face bonded, through-die vias may be necessary for packaging. For example, a plurality of through-die vias 318, 320 are formed through the first integrate circuit die 300 so that the existing contact pads of the processor logic 310 and memory control logic 312 may be extended to form electrical connection with the integrated circuit package 322 to transmit and receive supply/signal outside the integrated circuit 108. In this example, the first integrated circuit die 300 is mounted on the integrated circuit package 322 such as but not limited to dual in-line package (DIP), pin grid array (PGA), ball grid array (BGA), land grid array (LGA), or any suitable chip carrier/container.
In operation, at block 404, the second integrated circuit die 302 having the memory control logic 312 is mounted on the first integrated circuit die 300 having the plurality of passive variable resistance memory cells of passive variable resistance memory 306 in a face-to-face configuration (mounted upside-down, flipped), such that each of the plurality of passive variable resistance memory cells on the first integrated circuit die 300 is electrically connected to the memory control logic 312 on the second integrated circuit die 302 through at least one of the plurality of vias 314, 316. Depending on the materials of the first and second integrated circuit dies 300, 302, various die bonding techniques known in the art may be applied at block 404, such as but not limited to eutectic bonding, solder binding, adhesive bonding, glass/silver-glass bonding, to name a few. Before die bonding, a dielectric layer such as an insulating tape or a photoresist layer may be applied on the contact surface of the two integrated circuit die 300, 302, except on the openings of the vias 314, 316. The openings of the vias 314, 316 may be filled with solder, metal paste, or any other conductive material during die bonding to achieve electrical connections between the passive variable resistance memory 306 and the memory control logic 312 after bonding.
Although the processing blocks illustrated in
Referring to
Referring now to
At block 602, the lower electrode layer 502 is formed above the dielectric layer 500. The lower electrode layer 502 may be formed using any suitable metal or semiconductor materials such as but not limited to platinum, copper, gold, aluminum, titanium, iridium, iridium oxide, ruthenium, or silver, by thin-film deposition techniques such as CVD, thermal evaporation, sputtering, MBE, or electroplating. Proceeding to block 604, the memory layer 504 is formed above the lower electrode layer 502. The memory layer 504 is formed by thin-film deposition techniques such as CVD, thermal evaporation, sputtering, MBE, electroplating, spin-coating, or any other suitable techniques. The material of the memory layer 504 may be any suitable variable resistance material that is capable of storing state by resistance. Depending on the specific type of passive variable resistance memory 306, the material of the memory layer 504 may include, for example, one or more thin-film oxides (e.g., TiO2, SiO2, NiO, CeO2, VO2, V2O5, Nb2O5, Ti2O3, WO3, Ta2O5, ZrO2, IZO, ITO, etc.) for memristors, chalcogenide for phase-change memory, and ferromagnetic materials (e.g., CoFeB incorporated in MgO) for magnetoresistive memory. Proceeding to block 606, the upper electrode layer 506 is formed above the memory layer 504. The material and fabrication technique of the upper electrode layer 506 is for example the same as of the lower electrode layer 502. However, it is understood that different materials and/or thin-film deposition techniques may be applied to the lower and upper electrode layers 502, 506 if necessary. As discussed previously, blocks 600-606 may be repeated to form multiple layers of passive variable resistance memory cells in the vertical direction to increase the storage size of the passive variable resistance memory 306 without increasing the die area.
After the processing of the passive variable resistance memory 306 on the first integrated circuit die 300, the memory control logic 312 is formed on the second integrated circuit die 302 at block 402; and the second integrated circuit die 302 is mounted on the first integrated circuit die 300 in a face-to-face configuration at bock 404, as discussed previously. Although the processing blocks illustrated in
It is known in the art that memory may be implemented by an array of memory cells. Each memory cell of the array includes a memory region as a place to store state, which represents one bit of information. As shown in
In this example embodiment, each passive variable resistance memory cell (e.g. one bit) may be a memristor of any suitable design. Since a memristor includes a memory region 700 (e.g., a layer of TiO2) between two metal electrodes (e.g., platinum wires), memristors could be accessed in a crosspoint array style (i.e., crossed-wire pairs) with alternating current to non-destructively read out the resistance of each memory cell. A crosspoint array is an array of memory regions 700 that can connect each wire in one set of parallel wires (word lines 702) to every member of a second set of parallel wires (bit lines 704) that intersects the first set (usually the two sets of wires are perpendicular to each other, but this is not a necessary condition). In other words, each memory cell may be, for example, part of a crosspoint array. The memristor disclosed herein may be fabricated using a wide range of material deposition and processing techniques. One example is disclosed in corresponding U.S. Patent Application Publication No. 2008/0090337, having a title “ELECTRICALLY ACTUATED SWITCH”, which is incorporated herein by reference.
In this example, first, a lower electrode (e.g., word line 702) is fabricated using conventional techniques such as photolithography or electron beam lithography, or by more advanced techniques, such as imprint lithography. This may be, for example, the bottom wire (word line 702) of a crossed-wire pair as shown in
In this example, the next component of the memristor to be fabricated is the non-covalent interface layer 804, and may be omitted if greater mechanical strength is required, at the expense of slower switching at higher applied voltages. In this case, a layer of some inert material is deposited. This could be a molecular monolayer formed by a Langmuir-Blodgett (LB) process or it could be a self-assembled monolayer (SAM). In general, this interface layer 804 may form only weak van der Waals-type bonds to the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700. Alternatively, this interface layer 804 may be a thin layer of ice deposited onto a cooled integrated circuit die substrate. The material to form the ice may be an inert gas such as argon, or it could be a species such as CO2. In this case, the ice is a sacrificial layer that prevents strong chemical bonding between the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700, and is lost from the system by heating the integrated circuit die substrate later in the processing sequence to sublime the ice away. One skilled in this art can easily conceive of other ways to form weakly bonded interfaces between the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700.
Next, the material for the primary layer 806 of the memory region 700 is deposited. This can be done by a wide variety of conventional physical and chemical techniques, including evaporation from a Knudsen cell, electron beam evaporation from a crucible, sputtering from a target, or various forms of chemical vapor or beam growth from reactive precursors. The film may be in the range from 1 to 30 nanometers (nm) thick, and it may be grown to be free of dopants. Depending on the thickness of the primary layer 806, it may be nanocrystalline, nanoporous, or amorphous in order to increase the speed with which ions can drift in the material to achieve doping by ion injection or undoping by ion ejection from the primary layer 806. Appropriate growth conditions, such as deposition speed or temperature, may be chosen to achieve the chemical composition and local atomic structure desired for this initially insulating or low conductivity primary layer 806.
The next layer is the dopant source layer (i.e., secondary layer 808) for the primary layer 806, which may also be deposited by any of the techniques mentioned above. This material is chosen to provide the appropriate doping species for the primary layer 806. This secondary layer 808 is chosen to be chemically compatible with the primary layer 806, e.g., the two materials should not react chemically and irreversibly with each other to form a third material. One example of a pair of materials that can be used as the primary and secondary layers 806, 808 is TiO2 and TiO2-x, respectively. TiO2 is a semiconductor with an approximately 3.2 eV bandgap. It is also a weak ionic conductor. A thin film of TiO2 creates the tunnel barrier, and the TiO2-x forms an ideal source of oxygen vacancies to dope the TiO2 and make it conductive.
In this example, finally, an upper electrode (e.g., bit line 704) is fabricated above the secondary layer 808 of the memory region 700, in a manner similar to which the lower electrode (e.g., word lines 702) was created. This may be, for example, the top wire (bit line 704) of the crossed-wire pair as shown in
Proceeding to block 402, in this example, a plurality of through-die vias 318, 320 are formed through the first integrated circuit die 300 by any suitable processing techniques such as chemical or physical etching and laser ablation. In one example, through holes of the through-die vias 318, 320 are formed by dry etching techniques such as deep reactive ion etch (DRIE) with photoresist or hard mask. Then the side-wall insulator of the through holes is formed to separate from conductive material using techniques such as CVD. Lastly, the through holes are filled with conductive materials such as copper using techniques such as metal electroplating, conductive paste printing, or any other suitable techniques to achieve conductivity of the through-die vias 318, 320.
After processing on the first integrated circuit die 300, the process moves to the second integrated circuit die 302, where memory control logic 312 and processor logic 310 are formed at blocks 400, 908, respectively. At block 404, the second integrated circuit die 302 is mounted on the first integrated circuit die 300 in a face-to-face configuration at bock 404 as discussed previously. Finally, the first integrated circuit die 300 is mounted on the integrated circuit package 322 using any suitable packaging process as known in the art such as flip-chip bonding, so that the processor logic 310 and memory control logic 312 on the second integrated circuit die 302 are electrically connected to the integrated circuit package 322 through the through-die vias 318, 320 to transmit and receive supply/signal outside the integrated circuit 108.
Although the processing blocks illustrated in
Also, integrated circuit design systems (e.g., work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic and circuits described herein may also be produced as integrated circuits by such systems using the computer readable medium with instructions stored therein. For example, an integrated circuit with the aforedescribed logic and structure may be created using such integrated circuit fabrication systems. The computer readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. The designed integrated circuit includes a plurality of passive variable resistance memory cells of passive variable resistance memory, wherein each of the plurality of passive variable resistance memory cells is operative to electrically connect to memory control logic of another integrated circuit through at least one of a plurality of vias. The designed integrated circuit also includes a plurality of through-die vias operative to electrically connect to the memory control logic and processor logic of another integrated circuit. The designed integrated circuit may also include any other structure as disclosed herein.
Among other advantages, the method for making the integrated circuit with face-to-face bonded passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. Since the passive variable resistance memory cells and the active semiconductor device (e.g., CMOS transistors) are formed on two separate integrated circuit dies, the design, fabrication, and test complications and cost of the integrated circuit are reduced. For example, the die material of the passive variable resistance memory is not limited to silicon and may be any suitable non-silicon materials; and the two integrated circuit dies may be tested separately before bonding. In addition, compared with known integration solutions, the face-to-face bonded passive variable resistance memory eliminates any die area increase and enables faster memory access by both reducing the connection distance and allowing for the increased number of parallel connections. Moreover, the method for making the integrated circuit with face-to-face bonded passive variable resistance memory provides flexibility for adopting various types of passive variable resistance memory such as but not limited to memristor, phase-change memory, or magnetoresistive memory. Other advantages will be recognized by those of ordinary skill in the art.
The above detailed description of the invention and the examples described therein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present invention cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.
