George Mulfinger

Person

Saratoga Springs, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic fuses with a silicide layer having multiple thicknesses
- Patent number 12,154,854
- Issue date Nov 26, 2024
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shyue Seng Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for random code generation
- Patent number 11,907,685
- Issue date Feb 20, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Judson R. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structure with shared well
- Patent number 11,798,948
- Issue date Oct 24, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Kaustubh Shanbhag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photonics chips including a fully-depleted silicon-on-insulator fie...
- Patent number 11,569,268
- Issue date Jan 31, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure with different stress-inducing isolation dielectrics for...
- Patent number 11,450,573
- Issue date Sep 20, 2022
- GLOBALFOUNDRIES U.S. Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 11,217,678
- Issue date Jan 4, 2022
- GLOBALFOUNDRIES U.S. Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical lateral heterojunction bipolar transistors
- Patent number 11,127,843
- Issue date Sep 21, 2021
- GLOBALFOUNDRIES U.S. INC.
- Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with diffusion blocking spacer sections
- Patent number 11,101,364
- Issue date Aug 24, 2021
- GLOBALFOUNDRIES U.S. INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral heterojunction bipolar transistors with asymmetric junctions
- Patent number 11,094,805
- Issue date Aug 17, 2021
- GLOBALFOUNDRIES U.S. INC.
- Alexander Derrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicided gate structures
- Patent number 11,031,484
- Issue date Jun 8, 2021
- GLOBALFOUNDRIES U.S. INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of enhanced faceted raised source/drain EPI material for...
- Patent number 10,825,897
- Issue date Nov 3, 2020
- GLOBALFOUNDRIES Inc.
- Wei Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of enhanced faceted raised source/drain epi material for...
- Patent number 10,777,642
- Issue date Sep 15, 2020
- GLOBALFOUNDRIES Inc.
- Wei Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Faceted epitaxial source/drain regions
- Patent number 10,756,184
- Issue date Aug 25, 2020
- GLOBALFOUNDRIES Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned sacrificial epitaxial capping for trench silicide
- Patent number 10,741,556
- Issue date Aug 11, 2020
- GLOBALFOUNDRIES Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with a grown silicon-germanium channel
- Patent number 10,680,065
- Issue date Jun 9, 2020
- GlobalFoundries Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 10,522,655
- Issue date Dec 31, 2019
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure including laterally recessed source/dr...
- Patent number 10,396,078
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a gate-to-source/drain contact structure
- Patent number 10,388,654
- Issue date Aug 20, 2019
- GLOBALFOUNDRIES Inc.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post gate silicon germanium channel condensation and method for pro...
- Patent number 10,326,007
- Issue date Jun 18, 2019
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strain retention semiconductor member for channel SiGe layer of pFET
- Patent number 10,236,343
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Dina H. Triyoso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for patterning active regions of transistor elements in a...
- Patent number 10,217,660
- Issue date Feb 26, 2019
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Punchthrough stop layers for fin-type field-effect transistors
- Patent number 10,056,381
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for late differential SOI thinning for improved FDSOI perfor...
- Patent number 10,050,119
- Issue date Aug 14, 2018
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post gate silicon germanium channel condensation and method for pro...
- Patent number 10,043,893
- Issue date Aug 7, 2018
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure including laterally recessed source/dr...
- Patent number 10,020,307
- Issue date Jul 10, 2018
- GLOBALFOUNDRIES Inc.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epi facet height uniformity improvement for FDSOI technologies
- Patent number 10,008,576
- Issue date Jun 26, 2018
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffusion break forming after source/drain forming and related IC s...
- Patent number 9,917,103
- Issue date Mar 13, 2018
- GLOBALFOUNDRIES Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned sacrificial epitaxial capping for trench silicide
- Patent number 9,812,453
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 9,806,170
- Issue date Oct 31, 2017
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epi facet height uniformity improvement for FDSOI technologies
- Patent number 9,704,971
- Issue date Jul 11, 2017
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
IC DEVICE WITH VERTICALLY-GRADED SILICON GERMANIUM REGION ADJACENT...
- Publication number 20240258376
- Publication date Aug 1, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Judson Robert Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH ISOLATION STRUCTURES IN ACTIVE REGIONS
- Publication number 20240234425
- Publication date Jul 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Tamilmani ETHIRAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ONE-TIME PROGRAMMABLE FUSE USING PN JUNCTION OVER GATE METAL LAYER,...
- Publication number 20240188287
- Publication date Jun 6, 2024
- GLOBALFOUNDRIES U.S. Inc.
- George Robert Mulfinger
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE WITH LATERALLY GRADED CHANNEL REGION
- Publication number 20240128322
- Publication date Apr 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- George R. MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD OF FORMING SPACERS ON UNFACETED RAISED SOURCE/...
- Publication number 20230352348
- Publication date Nov 2, 2023
- GLOBALFOUNDRIES U.S. Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC FUSES WITH A SILICIDE LAYER HAVING MULTIPLE THICKNESSES
- Publication number 20230223336
- Publication date Jul 13, 2023
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Shyue Seng Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH FACETED, RAISED SOURCE/DRAIN REGION
- Publication number 20230146952
- Publication date May 11, 2023
- GLOBALFOUNDRIES U.S. Inc.
- George R. MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH SHARED WELL
- Publication number 20230112377
- Publication date Apr 13, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Kaustubh Shanbhag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...
- Publication number 20230047046
- Publication date Feb 16, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...
- Publication number 20230038887
- Publication date Feb 9, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR...
- Publication number 20210398862
- Publication date Dec 23, 2021
- GLOBALFOUNDRIES U.S. Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH ASYMMETRIC JUNCTIONS
- Publication number 20210226044
- Publication date Jul 22, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Alexander Derrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR RANDOM CODE GENERATION
- Publication number 20210141610
- Publication date May 13, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Judson R. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS
- Publication number 20210091212
- Publication date Mar 25, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN STRUCTURES OF FINFET DEVICES
- Publication number 20210091222
- Publication date Mar 25, 2021
- GLOBALFOUNDRIES U.S. Inc.
- TAO CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SILICIDE STRUCTURES
- Publication number 20200411666
- Publication date Dec 31, 2020
- GLOBALFOUNDRIES INC.
- George R. MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH DIFFUSION BLOCKING SPACER SECTIONS
- Publication number 20200287019
- Publication date Sep 10, 2020
- GLOBALFOUNDRIES INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF ENHANCED FACETED RAISED SOURCE/DRAIN EPI MATERIAL FOR...
- Publication number 20200243646
- Publication date Jul 30, 2020
- GLOBALFOUNDRIES INC.
- Wei Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF ENHANCED FACETED RAISED SOURCE/DRAIN EPI MATERIAL FOR...
- Publication number 20200243645
- Publication date Jul 30, 2020
- GLOBALFOUNDRIES INC.
- Wei Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FACETED EPITAXIAL SOURCE/DRAIN REGIONS
- Publication number 20200144365
- Publication date May 7, 2020
- GLOBALFOUNDRIES INC.
- George R. MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...
- Publication number 20200083346
- Publication date Mar 12, 2020
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL
- Publication number 20200044029
- Publication date Feb 6, 2020
- GLOBALFOUNDRIES INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPOSITE SPACERS FOR TAILORING THE SHAPE OF THE SOURCE AND DRAIN R...
- Publication number 20200020770
- Publication date Jan 16, 2020
- GLOBALFOUNDRIES INC.
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE WORK FUNCTION ENABLEMENT FOR SILICON NANOWIRE DEVICE
- Publication number 20190221483
- Publication date Jul 18, 2019
- GLOBALFOUNDRIES INC.
- George MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A GATE-TO-SOURCE/DRAIN CONTACT STRUCTURE
- Publication number 20190214387
- Publication date Jul 11, 2019
- GLOBALFOUNDRIES INC.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRO...
- Publication number 20190043967
- Publication date Feb 7, 2019
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHAPED CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH
- Publication number 20190027370
- Publication date Jan 24, 2019
- GLOBALFOUNDRIES INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A...
- Publication number 20190027400
- Publication date Jan 24, 2019
- GLOBALFOUNDRIES INC.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...
- Publication number 20180315832
- Publication date Nov 1, 2018
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DR...
- Publication number 20180286863
- Publication date Oct 4, 2018
- GLOBALFOUNDRIES INC.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS

George Mulfinger

Person

Patents Grantslast 30 patents

Electronic fuses with a silicide layer having multiple thicknesses

Structure and method for random code generation

Semiconductor structure with shared well

Photonics chips including a fully-depleted silicon-on-insulator fie...

Structure with different stress-inducing isolation dielectrics for...

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Asymmetrical lateral heterojunction bipolar transistors

Field-effect transistors with diffusion blocking spacer sections

Lateral heterojunction bipolar transistors with asymmetric junctions

Silicided gate structures

Formation of enhanced faceted raised source/drain EPI material for...

Formation of enhanced faceted raised source/drain epi material for...

Faceted epitaxial source/drain regions

Self-aligned sacrificial epitaxial capping for trench silicide

Field-effect transistors with a grown silicon-germanium channel

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Integrated circuit structure including laterally recessed source/dr...

Methods of forming a gate-to-source/drain contact structure

Post gate silicon germanium channel condensation and method for pro...

Strain retention semiconductor member for channel SiGe layer of pFET

Technique for patterning active regions of transistor elements in a...

Punchthrough stop layers for fin-type field-effect transistors

Method for late differential SOI thinning for improved FDSOI perfor...

Post gate silicon germanium channel condensation and method for pro...

Integrated circuit structure including laterally recessed source/dr...

Epi facet height uniformity improvement for FDSOI technologies

Diffusion break forming after source/drain forming and related IC s...

Self-aligned sacrificial epitaxial capping for trench silicide

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Epi facet height uniformity improvement for FDSOI technologies

Patents Applicationslast 30 patents

IC DEVICE WITH VERTICALLY-GRADED SILICON GERMANIUM REGION ADJACENT...

DEVICE WITH ISOLATION STRUCTURES IN ACTIVE REGIONS

ONE-TIME PROGRAMMABLE FUSE USING PN JUNCTION OVER GATE METAL LAYER,...

DEVICE WITH LATERALLY GRADED CHANNEL REGION

STRUCTURE AND METHOD OF FORMING SPACERS ON UNFACETED RAISED SOURCE/...

ELECTRONIC FUSES WITH A SILICIDE LAYER HAVING MULTIPLE THICKNESSES

TRANSISTOR WITH FACETED, RAISED SOURCE/DRAIN REGION

SEMICONDUCTOR STRUCTURE WITH SHARED WELL

PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...

PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...

STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR...

LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH ASYMMETRIC JUNCTIONS

STRUCTURE AND METHOD FOR RANDOM CODE GENERATION

ASYMMETRICAL LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS

FIN STRUCTURES OF FINFET DEVICES

DIFFERENTIAL SILICIDE STRUCTURES

FIELD-EFFECT TRANSISTORS WITH DIFFUSION BLOCKING SPACER SECTIONS

FORMATION OF ENHANCED FACETED RAISED SOURCE/DRAIN EPI MATERIAL FOR...

FORMATION OF ENHANCED FACETED RAISED SOURCE/DRAIN EPI MATERIAL FOR...

FACETED EPITAXIAL SOURCE/DRAIN REGIONS

DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...

FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL

COMPOSITE SPACERS FOR TAILORING THE SHAPE OF THE SOURCE AND DRAIN R...

SINGLE WORK FUNCTION ENABLEMENT FOR SILICON NANOWIRE DEVICE

METHODS OF FORMING A GATE-TO-SOURCE/DRAIN CONTACT STRUCTURE

POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRO...

SHAPED CAVITY FOR EPITAXIAL SEMICONDUCTOR GROWTH

TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A...

METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...

INTEGRATED CIRCUIT STRUCTURE INCLUDING LATERALLY RECESSED SOURCE/DR...