Patent Application
20210091222
The disclosed subject matter relates generally to semiconductor devices, and more particularly to fin structures of fin-type field effect transistor (FinFET) devices and methods of forming the same.
A fin-type field effect transistor (FinFET) device is a type of non-planar multi-gate transistor device having raised “fin” channels over a semiconductor substrate. The FinFET devices have significantly higher switching speed and higher current density than the mainstream complementary metal-oxide-semiconductor (CMOS) devices. While the FinFET devices show improved leakage current performance over the CMOS devices, leakage current persists due to short channel effects (SCEs) and gate-induced drain leakage (GIDL).
Leakage current due to SCEs and GIDL decreases with narrower fins. However, despite the advantages of narrower fins, the drive current for the FinFET devices may be adversely affected as the fins get thinner, and there may have significant challenges in the fabrication process as well.
For the reasons described above, FinFET devices having fin structures to realize high drive current and low leakage current and methods of forming the same are presented.
To achieve the foregoing and other aspects of the present disclosure, FinFET devices having fin structures to realize high drive current and low leakage current and methods of forming the same are presented.
According to an aspect of the present disclosure, a FinFET device is provided, which includes a semiconductor substrate, a fin structure and a dielectric material. The fin structure is extending from the semiconductor substrate, the fin structure having an upper fin section, a middle fin section and a lower fin section. The dielectric material is over the semiconductor substrate embedding a first portion of the lower fin section. The dielectric material forms shallow trench isolation regions of the FinFET device.
According to another aspect of the present disclosure, a method of fabricating a FinFET device is provided, which includes providing a semiconductor substrate and forming an upper fin section from the semiconductor substrate. A middle fin portion is subsequently formed from the semiconductor substrate. A lower fin section is thereafter formed from the semiconductor substrate. The upper fin section, the middle fin section and the lower fin sections form a fin structure of the FinFET device. Shallow trench isolation regions are formed adjacent to and covering a portion of the lower fin section.
According to yet another aspect of the present disclosure, a method of fabricating a FinFET device is provided, which includes providing a semiconductor substrate and forming an upper fin section having a first width from the semiconductor substrate. A middle fin section having a second width is subsequently formed from the semiconductor substrate. The second width is narrower than the first width. A lower fin section having a third width is thereafter formed from the semiconductor substrate. The third width is wider than the second width. A dielectric material is deposited to form shallow trench isolation covering a portion of the lower fin section.
The embodiments of the present disclosure will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawings:
For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the disclosure. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the disclosure. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.
Various embodiments of the disclosure are described below. The embodiments disclosed herein are exemplary and not intended to be exhaustive or limiting to the disclosure.
The present disclosure relates to fin structures of FinFET devices, the fin structures having laterally opposite concave sidewalls to realize high drive current and low leakage current and methods of forming the same. The concave sidewalls form a narrower width at a middle section of the fin structure that advantageously reduces leakage current, while wider widths at upper sections are ideal for achieving improved drive current for the FinFET devices. It is also preferable to have wider widths at lower sections of the fin structures to improve yield and reduce defects by facilitating subsequent nucleation of epitaxial material. The epitaxial material forms source and drain regions of the FinFET devices. The fin structures of the FinFET devices may be formed on bulk silicon substrate, semiconductor-on-insulator (SOI) substrate or other suitable semiconductor substrates.
Embodiments of the disclosure are now described in detail with accompanying drawings. It is noted that like and corresponding elements are referred to by the use of the same reference numerals.
As illustrated in
A patterning layer (not shown) is deposited over the semiconductor substrate 102 using a suitable deposition process, such as a chemical vapor deposition (CVD) process or a spin-coating process. A plurality of fin-defining masking portions 104 is formed over the semiconductor substrate 102 by forming openings 106 in the patterning layer using a material removing process. Areas of the semiconductor substrate 102 are exposed in the openings 106. An oxide layer 110 may be formed in the exposed areas of the semiconductor substrate 102 as a result of a natural oxidation process.
The masking portions 104 are preferably formed of a material that is capable of protecting the top surface of the semiconductor substrate 102T from subsequent processing steps. The masking portions 104 may include any suitable patterning materials having any suitable thickness; e.g., a polysilicon layer, an oxide layer, a nitride layer or a combination thereof. In some embodiments of the disclosure, the masking portions 104 may include a stack of silicon nitride and silicon oxide. In other embodiments of the disclosure, the masking portions 104 may include an organic planarization layer (OPL) or a photoresist layer
The plurality of fin-defining masking portions 104 laterally extends in a lengthwise direction over the semiconductor substrate 102. Each of the fin-defining masking portion 104 has a pair of substantially vertical laterally opposite sidewalls 108 that are separated along a widthwise direction, perpendicular to the lengthwise direction. As used herein, the term “lengthwise direction” is a direction along which an object extends the most. In one embodiment of the disclosure, each fin-defining masking portion 104 has a substantially uniform width dl.
The material removing process may be performed in a reaction chamber, including plasma of a reactive gas mixture created by applying thereto a radio frequency (RF) power. The reaction chamber may be preferably maintained at a suitable operational pressure to maintain the plasma in the reaction chamber. In this embodiment of the disclosure, the oxide removing process may be performed by an exemplarily etch chemistry including tetrafluoromethane (CF4) and argon (Ar). A combination of CF4 and Ar reactive gases may flow into a reaction chamber at a flow rate of 100 sccm and 200 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 10 mTorr and at a chuck temperature of 88° C. A radio frequency (RF) power of 400 W, coupled with a RF bias of 150 W may be continuously applied for processing duration of 7.5 seconds to effectively remove the undesirable oxide layer 110 from the exposed areas of the semiconductor substrate 102. Various adjustments may be made to the etch chemistry, the operational pressure, the RF power and the processing duration as needed.
The material removing process may be a time-controlled process and may continue until the upper fin sections 112a reach a predetermined upper fin height h1. In one embodiment of the disclosure, the upper fin height h1 is preferably ranging from about 5 nm to about 30 nm. The upper fin sections 112a have an upper fin width w1 that may be substantially similar to the width dl of the fin-defining masking portions 104, the upper fin width w1 ranging from about 10 nm to about 35 nm. In another embodiment of the disclosure, the material removing process may be an anisotropic etching process, such as a reactive ion etching (RIE) process.
In this embodiment of the disclosure, the material removing process may be performed by an exemplarily etch chemistry including nitrogen (N2), oxygen (O2) and chlorine (Cl2). A combination of N2, O2 and Cl2 gases may flow into a reaction chamber at a flow rate of 50 sccm, 2 sccm and 150 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 10 mTorr and at a chuck temperature of 88° C. A continuous RF power of 800 W, coupled with a RF bias of 400 W pulsed at a frequency of 50 Hz using direct current (DC) at 20% bias duty cycle, may be applied for a processing duration of 24 seconds to form the plurality of upper fin sections 112a in the semiconductor substrate 102. As used herein, the duty cycle is defined as the ratio of pulse on time (or pulse width) to pulse off time. Various adjustments may be made to the etch chemistry, the operational pressure, the RF power and the processing duration as needed.
The applied RF bias may be preferably increased to 400 W to increase the etching rate of the semiconductor substrate 102 and to obtain a more vertical sidewall profile on the upper fin sections 112a. The applied RF bias may be pulsed to beneficially modify the overall characteristics of the etching process, such as to obtain increased etch selectivity between the semiconductor substrate 102 and the fin-defining masking portions 104. The increased RF bias may increase the vertical directionality of the plasma of reactive gases, thereby effectively controlling the sidewall profiles of the upper fin sections 112a. The processing duration may also be adjusted accordingly to control the upper fin height h1; a longer processing duration will result in greater upper fin height h1.
In this embodiment of the disclosure, the oxidation process may be performed by an exemplarily oxidizing chemistry including Ar and O2. A combination of Ar and O2 gases may flow into a reaction chamber at a flow rate of 200 sccm and 100 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 20 mTorr and at a chuck temperature of 88° C. A RF power of 1300 W, coupled with a 0 W RF bias, may be continuously applied for processing duration of 45 seconds to form the oxide layer 116 in the outer portions of the upper fin sections 112a. Various adjustments may be made to the oxidizing chemistry, the operational pressure, the RF power and the processing duration as needed.
The applied RF power may be preferably increased to 1300 W, and the operational pressure may be increased to 20 mTorr, to increase the oxidation rate of the outer portions of the upper fin sections 112a. The high RF power advantageously maximizes the number of oxygen radicals in the oxygen-containing environment in order to form a complete oxide layer 116 in the outer portions of the upper fin sections 112a. The processing duration may also be adjusted accordingly to a predetermined upper fin width w1 ‘; a longer processing duration will result in a thicker oxide layer 116 and a narrower upper fin width w1’ of the upper fin sections 112a.
In this embodiment of the disclosure, the material removing process may be performed by an exemplarily etch chemistry including helium (He), CF4 and O2. A combination of He, CF4 and O2 gases may flow into a reaction chamber at a flow rate of 200 sccm, 80 sccm and 8 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 30 mTorr and at a chuck temperature of 88° C. A RF power of 2000 W, coupled with 0 W RF bias, may be continuously applied for processing duration of 11.5 seconds to remove the portions of the oxide layer 116 at the bottom of the cavities 118. Various adjustments may be made to the etch chemistry, the operational pressure, the RF power and the processing duration as needed.
In some embodiments of the disclosure, it is preferable to form the upper fin height h1 beyond the predetermined upper fin height. In those embodiments, the upper fin height h1 is preferably ranging from about 20 nm to 120 nm. Forming the cavities 120 may consequently remove lower portions of the upper fin sections 112a, thereby reducing the upper fin height h1.
A plurality of middle fin sections 112b is formed below the upper fin sections 112a and each of the middle fin section 112b may be separated by an adjacent pair of cavities 120. The middle fin section 112b has a middle fin height h2 and a middle fin width w2 at a narrowest portion of the middle fin section 112b. The middle fin width w2 is narrower than the upper fin width w1′. In one embodiment of the disclosure, the material removing process may be an isotropic etching process, such as an RIE process.
The material removing process may be a time-controlled process and may continue until the middle fin sections 112b reach a predetermined middle fin width w2. In one embodiment, the middle fin width w2 is at least 0.5 nm narrower than the upper fin width w1′. In another embodiment of the disclosure, the middle fin sections 112b have a preferable middle fin width w2 ranging from about 4 nm to about 30 nm. In yet another embodiment of the disclosure, the middle fin sections 112b have a preferable middle fin height h2 ranging from about 5 nm to about 30 nm.
In one embodiment of the disclosure, the material removing process may be performed by an exemplarily etch chemistry including N2, Cl2 and nitrogen trifluoride (NF3). A combination of N2, Cl2 and NH3 gases may flow into a reaction chamber at a flow rate of 50 sccm, 50 sccm, and 20 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 10 mTorr and at a chuck temperature of 88° C. A RF power of 800 W, coupled with 0 W RF bias, may be continuously applied for a processing duration of 30 seconds to form the middle fin sections 112b. Various adjustments may be made to the etch chemistry, the operational pressure, the RF power and the processing duration as needed.
The applied RF power may be preferably decreased to 800 W and the operational pressure may be decreased to 10 mTorr to enable a highly isotropic etching process to form the “ball-shaped” cavities 120. The “ball-shape” cavities 120 consequently affect the middle fin width w2, i.e., the bigger the “ball-shaped” cavities 120, the narrower the middle fin width w2.
The material removing process may be a time-controlled process and may continue until the lower fin sections 112c reach a predetermined lower fin height h3. In one embodiment of the disclosure, the lower fin height h3 is preferably ranging from about 55 nm to about 130 nm. In another embodiment of the disclosure, the lower fin width w3 is preferably ranging from about 5 nm to about 30 nm.
In this embodiment of the disclosure, the material removing process may be performed by an exemplarily etch chemistry including N2, O2, Cl2 and hydrogen bromide (HBr). A combination of N2, O2, Cl2 and HBr gases may flow into a reaction chamber at a flow rate of 50 sccm, 3 sccm, 150 sccm and 15 sccm, respectively. The reaction chamber may be maintained at an operational pressure of 10 mTorr and at a chuck temperature of 88° C. A continuous RF power of 800 W, coupled with a RF bias of 500 W pulsed at a frequency of 50 Hz using DC at 20% bias duty cycle may be applied for a processing duration of 22 seconds to form the lower fin sections 112c. Various adjustments may be made to the etch chemistry, the operational pressure, the RF power and processing duration as needed.
The dielectric material 126 may be subsequently recessed using a one or a multi-step material removing process. In one embodiment of the disclosure, the dielectric material 126 may be recessed using an isotropic etching process to a predetermined level. In another embodiment of the disclosure, the dielectric material 126 may be recessed using an anisotropic etching process, followed by an isotropic etching process to a predetermined level. The isotropic etching process advantageously removes potential dielectric material residue on sidewalls of the fin structures.
The dielectric material 126 is recessed to a level to expose a desired fin height H1. The desired fin height H1 may vary according to the specific designs of the FinFET devices. The exposed sections of the fin structures 112 form active regions that may function as channels for current flow for the FinFET device 100. A lower first portion of the lower fin section 112cb remains embedded in the dielectric material 124 and an upper second portion of the lower fin section 112ct is exposed. The dielectric material 126 may preferably be a dielectric material suitable to electrically isolate the adjacent fin structures 112, e.g., silicon dioxide or tetraethylorthosilicate (TEOS). In some embodiments of the disclosure, the recessed dielectric material 126 forms shallow trench isolation (STI) regions of the FinFET device 100.
In one embodiment of the disclosure, the lower first portion of the lower fin section 112cb may be preferably having a height ranging from about 50 nm to about 100 nm. In another embodiment of the disclosure, the upper second portion of the lower fin section 112cb may be preferably having a height ranging from about 5 nm to about 30 nm. In yet another embodiment of the disclosure, the fin height H1 may be preferably ranging from about 15 nm to about 80 nm. The fin-defining masking portions 104 (not shown) and the oxide material 116 (not shown) may be subsequently removed by employing suitable material removing process, such as a dry plasma ashing process, a selective wet etching process, a combination thereof or other suitable material removing processes.
In the above detailed description, methods of forming fin structures having concave sidewalls are presented. A plurality of fin structures is formed from a semiconductor substrate in several processing steps, including anisotropically removing a first portion of the semiconductor substrate to form substantially vertical upper fin sections, further isotropically removing a second portion of the semiconductor substrate to form middle fin sections having concave sidewalls, and yet further isotropically removing a third portion of the semiconductor substrate to form lower fin sections. The middle fin section has a middle fin width narrower than the upper and lower fin sections. The formation of the fin structures may take place in a single reaction chamber, using a single recipe including different processing steps.
The position of the middle fin sections may be controlled by adjusting the process parameters for forming the upper fin sections. For example, the upper fin sections may be formed deeper into the semiconductor substrate to form the middle fin sections at lower sections of the fin structures. Forming the middle fin section around a location of the fin structure having a highest leakage current advantageously reduces the leakage current at that location. The middle fin width may also be controlled by adjusting the process parameters for forming the middle fin sections. By adjusting the isotropic property of the material removing process, the middle fin width can be controlled. The wider widths at the upper fin sections retain a desirable high drive current for the FinFET devices.
An oxidation process may be performed after forming the upper fin sections, to form an oxide layer at outer portions of the upper fin sections. The oxidation process advantageously controls widths of the upper fin sections, such that the thicker the formed oxide layer, the narrower the width of the upper fin sections.
A dielectric material may be deposited between the fin structures to form shallow trench isolation regions to electrically isolate the adjacent fin structures. A first portion of the lower fin section may be embedded in the dielectric material and a second portion of the lower fin section may be exposed above the dielectric material. The upper fin sections, the middle fin sections and the second portions of the lower fin sections form active regions of the FinFET device. Active regions are regions that may function as channels for current flow for the FinFET device.
The terms “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Similarly, if a method is described herein as involving a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device. Occurrences of the phrase “in one embodiment” herein do not necessarily all refer to the same embodiment.
In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of materials, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about”.
While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that a number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the device, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.
