Hamid R. Azimi

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 10,306,760
- Issue date May 28, 2019
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 9,648,733
- Issue date May 9, 2017
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming molded panel embedded die structure
- Patent number 9,312,233
- Issue date Apr 12, 2016
- Intel Corporation
- Rahul N. Manepalli
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 9,257,380
- Issue date Feb 9, 2016
- Intel Corporation
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 8,987,065
- Issue date Mar 24, 2015
- Intel Corporation
- Ravi K. Nailla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 8,618,652
- Issue date Dec 31, 2013
- Intel Corporation
- Ravi K Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming a substrate core structure using microvia laser d...
- Patent number 8,440,916
- Issue date May 14, 2013
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Microelectronic package and method of manufacturing same
- Patent number 8,035,218
- Issue date Oct 11, 2011
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming collapse chip connection bumps on a semiconductor...
- Patent number 7,985,622
- Issue date Jul 26, 2011
- Intel Corporation
- Ravi Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of forming copper layers
- Patent number 7,413,936
- Issue date Aug 19, 2008
- Intel Corporation
- Hamid Azimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die/package interconnect
- Patent number 7,330,357
- Issue date Feb 12, 2008
- Intel Corporation
- Gilroy J. Vandentop
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with low modulus layer and capacitor/int...
- Patent number 7,042,077
- Issue date May 9, 2006
- Intel Corporation
- Michael J. Walk
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low cost programmable CPU package/substrate
- Patent number 7,005,727
- Issue date Feb 28, 2006
- Intel Corporation
- Hamid Azimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit substrate
- Patent number 6,858,475
- Issue date Feb 22, 2005
- Intel Corporation
- Charan K. Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with surface mounted pins on an organic...
- Patent number 6,600,233
- Issue date Jul 29, 2003
- Intel Corporation
- Hwai-Peng Yeoh
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package
- Patent number 6,430,058
- Issue date Aug 6, 2002
- Intel Corporation
- Bob Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with surface mounted pins on an organic...
- Patent number 6,413,849
- Issue date Jul 2, 2002
- Intel Corporation
- Hwai-Peng Yeoh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...
- Publication number 20240096809
- Publication date Mar 21, 2024
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS
- Publication number 20240030204
- Publication date Jan 25, 2024
- Intel Corporation
- Gang Duan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS
- Publication number 20240030147
- Publication date Jan 25, 2024
- Intel Corporation
- Gang Duan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS
- Publication number 20240030065
- Publication date Jan 25, 2024
- Intel Corporation
- Gang Duan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS
- Publication number 20230317592
- Publication date Oct 5, 2023
- Intel Corporation
- Brandon Christian Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND THIN FILM CAPA...
- Publication number 20230197697
- Publication date Jun 22, 2023
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND PLANAR INDUCTORS
- Publication number 20230187386
- Publication date Jun 15, 2023
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGES WITH EMBEDDED INTERPOSERS
- Publication number 20230094820
- Publication date Mar 30, 2023
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...
- Publication number 20170231092
- Publication date Aug 10, 2017
- Intel Corporation
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS OF FORMING PANEL EMBEDDED DIE STRUCTURES
- Publication number 20160190027
- Publication date Jun 30, 2016
- Intel Corporation
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20150179559
- Publication date Jun 25, 2015
- Intel Corporation
- Ravi K. Nalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING MOLDED PANEL EMBEDDED DIE STRUCTURES
- Publication number 20150003000
- Publication date Jan 1, 2015
- Rahul N. MANEPALLI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20140084467
- Publication date Mar 27, 2014
- Ravi K. Nalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...
- Publication number 20130242498
- Publication date Sep 19, 2013
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME
- Publication number 20110318850
- Publication date Dec 29, 2011
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20110254124
- Publication date Oct 20, 2011
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Microelectronic package and method of manufacturing same
- Publication number 20110101516
- Publication date May 5, 2011
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR...
- Publication number 20100044862
- Publication date Feb 25, 2010
- Ravi Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of Forming a Substrate Core Structure Using Microvia Laser D...
- Publication number 20090002958
- Publication date Jan 1, 2009
- Yonggang Li
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INTEGRATED CIRCUIT DIE/PACKAGE INTERCONNECT
- Publication number 20080096323
- Publication date Apr 24, 2008
- Gilroy J. Vandentop
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low cost programmable CPU package/substrate
- Publication number 20060060946
- Publication date Mar 23, 2006
- Intel Corporation
- Hamid Azimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit package with low modulus layer and capacitor/int...
- Publication number 20050230841
- Publication date Oct 20, 2005
- Michael J. Walk
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Integrated circuit die/package interconnect
- Publication number 20050063164
- Publication date Mar 24, 2005
- Gilroy J. Vandentop
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF FORMING AN INTEGRATED CIRCUIT SUBSTRATE
- Publication number 20040266070
- Publication date Dec 30, 2004
- Charan K. Gurumurthy
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Metal core substrate packaging
- Publication number 20040107569
- Publication date Jun 10, 2004
- John Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low cost programmable CPU package/substrate
- Publication number 20040004232
- Publication date Jan 8, 2004
- Hamid Azimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit package with surface mounted pins on an organic...
- Publication number 20020125583
- Publication date Sep 12, 2002
- Intel Corporation
- Hwai-Peng Yeoh
- H01 - BASIC ELECTRIC ELEMENTS

Hamid R. Azimi

Person

Patents Grantslast 30 patents

Method of forming a substrate core structure using microvia laser d...

Method of forming a substrate core structure using microvia laser d...

Method of forming molded panel embedded die structure

Forming functionalized carrier structures with coreless packages

Forming functionalized carrier structures with coreless packages

Forming functionalized carrier structures with coreless packages

Method of forming a substrate core structure using microvia laser d...

Microelectronic package and method of manufacturing same

Method of forming collapse chip connection bumps on a semiconductor...

Method of forming copper layers

Integrated circuit die/package interconnect

Integrated circuit package with low modulus layer and capacitor/int...

Low cost programmable CPU package/substrate

Method of forming an integrated circuit substrate

Integrated circuit package with surface mounted pins on an organic...

Integrated circuit package

Integrated circuit package with surface mounted pins on an organic...

Patents Applicationslast 30 patents

MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...

MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS

MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS

MULTI-DIE PANEL-LEVEL HIGH PERFORMANCE COMPUTING COMPONENTS

SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS

MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND THIN FILM CAPA...

MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND PLANAR INDUCTORS

MICROELECTRONIC PACKAGES WITH EMBEDDED INTERPOSERS

METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...

METHODS OF FORMING PANEL EMBEDDED DIE STRUCTURES

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

METHODS OF FORMING MOLDED PANEL EMBEDDED DIE STRUCTURES

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER D...

MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

Microelectronic package and method of manufacturing same

METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR...

Method of Forming a Substrate Core Structure Using Microvia Laser D...

INTEGRATED CIRCUIT DIE/PACKAGE INTERCONNECT

Low cost programmable CPU package/substrate

Integrated circuit package with low modulus layer and capacitor/int...

Integrated circuit die/package interconnect

METHOD OF FORMING AN INTEGRATED CIRCUIT SUBSTRATE

Metal core substrate packaging

Low cost programmable CPU package/substrate

Integrated circuit package with surface mounted pins on an organic...