Jack H. Linn

Person

Cadillac, MI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming plasma enhanced deposited, fully oxidized PSG film
- Patent number 7,223,706
- Issue date May 29, 2007
- Intersil Americas, Inc.
- Katie H. Pentas
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of manufacturing a plated electronic termination
- Patent number 7,174,626
- Issue date Feb 13, 2007
- Intersil Americas, Inc.
- Mark A. Kwoka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded substrate for an integrated circuit containing a planar intr...
- Patent number 7,052,973
- Issue date May 30, 2006
- Intersil Americas Inc.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer with metal silicidation
- Patent number 6,909,146
- Issue date Jun 21, 2005
- Intersil Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded substrate for an integrated circuit containing a planar intr...
- Patent number 6,825,532
- Issue date Nov 30, 2004
- Intersil Americas Inc.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for depositing and planarizing BPSG for dense trench MOSFET...
- Patent number 6,465,325
- Issue date Oct 15, 2002
- Fairchild Semiconductor Corporation
- Rodney S. Ridley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power trench transistor device source region formation using silico...
- Patent number 6,455,379
- Issue date Sep 24, 2002
- Fairchild Semiconductor Corporation
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a bonded substrate containing a planar intrinsic...
- Patent number 6,255,195
- Issue date Jul 3, 2001
- Intersil Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power trench transistor device source region formation using silico...
- Patent number 6,246,090
- Issue date Jun 12, 2001
- Intersil Corporation
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inverted thin film resistor and method of manufacture
- Patent number 6,121,105
- Issue date Sep 19, 2000
- Intersil Corporation
- William R. Wade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inverted thin film resistor
- Patent number 6,034,411
- Issue date Mar 7, 2000
- Intersil Corporation
- William R. Wade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SC-2 based pre-thermal treatment wafer cleaning process
- Patent number 5,932,022
- Issue date Aug 3, 1999
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer microtip probe and method
- Patent number 5,892,223
- Issue date Apr 6, 1999
- Harris Corporation
- Elijah Karpov
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Plasma cleaning method for improved ink brand permanency on IC pack...
- Patent number 5,882,423
- Issue date Mar 16, 1999
- Harris Corporation
- Jack H. Linn
- B08 - CLEANING
Information Patent Grant
Bonded wafer processing with oxidative bonding
- Patent number 5,849,627
- Issue date Dec 15, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor structure in a bonded wafer and method of fabrication
- Patent number 5,841,182
- Issue date Nov 24, 1998
- Harris Corporation
- Jack Howard Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planarization method by use of particle dispersion and subsequent t...
- Patent number 5,837,603
- Issue date Nov 17, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for cleaning semiconductor wafers to improve dice to substra...
- Patent number 5,833,758
- Issue date Nov 10, 1998
- Harris Corporation
- Jack H. Linn
- B08 - CLEANING
Information Patent Grant
Method for providing a silicon and diamond substrate having a carbo...
- Patent number 5,782,975
- Issue date Jul 21, 1998
- Jack H. Linn
- C30 - CRYSTAL GROWTH
Information Patent Grant
Bonded wafer
- Patent number 5,744,852
- Issue date Apr 28, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing
- Patent number 5,728,624
- Issue date Mar 17, 1998
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diamond insulator devices and method of fabrication
- Patent number 5,683,939
- Issue date Nov 4, 1997
- Harris Corporation
- Gregory Schrantz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with diamond insulator
- Patent number 5,650,639
- Issue date Jul 22, 1997
- Harris Corporation
- Gregory A. Schrantz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer and method of fabrication thereof
- Patent number 5,603,779
- Issue date Feb 18, 1997
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonded wafer processing with metal silicidation
- Patent number 5,569,620
- Issue date Oct 29, 1996
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die separation method for silicon on diamond circuit structures
- Patent number 5,552,345
- Issue date Sep 3, 1996
- Harris Corporation
- Gregory A. Schrantz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct etch for thin film resistor using a hard mask
- Patent number 5,547,896
- Issue date Aug 20, 1996
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for providing a silicon and diamond substrate having a carbo...
- Patent number 5,526,768
- Issue date Jun 18, 1996
- Harris Corporation
- Jack H. Linn
- C30 - CRYSTAL GROWTH
Information Patent Grant
Bonded wafer processing
- Patent number 5,517,047
- Issue date May 14, 1996
- Harris Corporation
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma cleaning method for improved ink brand permanency on IC pack...
- Patent number 5,451,263
- Issue date Sep 19, 1995
- Harris Corporation
- Jack H. Linn
- B08 - CLEANING

Patents Applicationslast 30 patents

Information Patent Application
Plasma Enhanced Deposited, Fully Oxidized PSG Film
- Publication number 20070187803
- Publication date Aug 16, 2007
- INTERSIL AMERICAS INC.
- Katie H. Pentas
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Plasma enhanced deposited, fully oxidized PSG film
- Publication number 20060001127
- Publication date Jan 5, 2006
- INTERSIL AMERICAS INC.
- Katie H. Pentas
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Bonded substrate for an integrated circuit containing a planar intr...
- Publication number 20040180512
- Publication date Sep 16, 2004
- INTERSIL AMERICAS INC.
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS
- Publication number 20020189640
- Publication date Dec 19, 2002
- JACK H. LINN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR DEPOSITING AND PLANARIZING BPSG FOR DENSE TRENCH MOSFET...
- Publication number 20020119639
- Publication date Aug 29, 2002
- Rodney S. Ridley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING A PLATED ELECTRONIC TERMINATION
- Publication number 20020029473
- Publication date Mar 14, 2002
- MARK A. KWOKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power trench transistor device source region formation using silico...
- Publication number 20010022379
- Publication date Sep 20, 2001
- INTERSIL CORPORATION
- Linda S. Brush
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a bonded substrate containing a planar intrinsic...
- Publication number 20010016399
- Publication date Aug 23, 2001
- HARRIS CORPORATION
- Jack H. Linn
- H01 - BASIC ELECTRIC ELEMENTS

Jack H. Linn

Person

Patents Grantslast 30 patents

Method for forming plasma enhanced deposited, fully oxidized PSG film

Method of manufacturing a plated electronic termination

Bonded substrate for an integrated circuit containing a planar intr...

Bonded wafer with metal silicidation

Bonded substrate for an integrated circuit containing a planar intr...

Process for depositing and planarizing BPSG for dense trench MOSFET...

Power trench transistor device source region formation using silico...

Method for forming a bonded substrate containing a planar intrinsic...

Power trench transistor device source region formation using silico...

Inverted thin film resistor and method of manufacture

Inverted thin film resistor

SC-2 based pre-thermal treatment wafer cleaning process

Multilayer microtip probe and method

Plasma cleaning method for improved ink brand permanency on IC pack...

Bonded wafer processing with oxidative bonding

Capacitor structure in a bonded wafer and method of fabrication

Planarization method by use of particle dispersion and subsequent t...

Method for cleaning semiconductor wafers to improve dice to substra...

Method for providing a silicon and diamond substrate having a carbo...

Bonded wafer

Bonded wafer processing

Diamond insulator devices and method of fabrication

Integrated circuit with diamond insulator

Bonded wafer and method of fabrication thereof

Bonded wafer processing with metal silicidation

Die separation method for silicon on diamond circuit structures

Direct etch for thin film resistor using a hard mask

Method for providing a silicon and diamond substrate having a carbo...

Bonded wafer processing

Plasma cleaning method for improved ink brand permanency on IC pack...

Patents Applicationslast 30 patents

Plasma Enhanced Deposited, Fully Oxidized PSG Film

Plasma enhanced deposited, fully oxidized PSG film

Bonded substrate for an integrated circuit containing a planar intr...

SC-2 BASED PRE-THERMAL TREATMENT WAFER CLEANING PROCESS

PROCESS FOR DEPOSITING AND PLANARIZING BPSG FOR DENSE TRENCH MOSFET...

METHOD OF MANUFACTURING A PLATED ELECTRONIC TERMINATION

Power trench transistor device source region formation using silico...

Method for forming a bonded substrate containing a planar intrinsic...