James D. Sansbury

Person

Portola Valley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Nonvolatile memory cell with low doping region
- Patent number 6,828,620
- Issue date Dec 7, 2004
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,781,883
- Issue date Aug 24, 2004
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,646,919
- Issue date Nov 11, 2003
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell with low doping region
- Patent number 6,573,138
- Issue date Jun 3, 2003
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,532,170
- Issue date Mar 11, 2003
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable impedance device
- Patent number 6,456,529
- Issue date Sep 24, 2002
- SanDisk Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell with multiple gate oxide thicknesses
- Patent number 6,442,073
- Issue date Aug 27, 2002
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,366,498
- Issue date Apr 2, 2002
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable impedance device
- Patent number 6,320,788
- Issue date Nov 20, 2001
- SanDisk Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,295,230
- Issue date Sep 25, 2001
- Altera Coporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Evaluation of memory cell characteristics
- Patent number 6,282,122
- Issue date Aug 28, 2001
- Altera Corporation
- James D. Sansbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,268,623
- Issue date Jul 31, 2001
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact electrically erasable memory cells and arrays
- Patent number 6,243,296
- Issue date Jun 5, 2001
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell with multiple gate oxide thicknesses
- Patent number 6,236,597
- Issue date May 22, 2001
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to configure nonvolatile cells and cell arrays
- Patent number 6,226,201
- Issue date May 1, 2001
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable impedance device
- Patent number 6,201,734
- Issue date Mar 13, 2001
- SanDisk Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of margin testing programmable interconnect cell
- Patent number 6,122,209
- Issue date Sep 19, 2000
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,078,521
- Issue date Jun 20, 2000
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,052,309
- Issue date Apr 18, 2000
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Evaluation of memory cell characteristics
- Patent number 6,031,763
- Issue date Feb 29, 2000
- Altera Corporation
- James D. Sansbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile static memory circuit
- Patent number 6,028,787
- Issue date Feb 22, 2000
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,018,476
- Issue date Jan 25, 2000
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile configuration cells and cell arrays
- Patent number 6,005,806
- Issue date Dec 21, 1999
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Evaluation of memory cell characteristics
- Patent number 5,959,891
- Issue date Sep 28, 1999
- Altera Corporation
- James D. Sansbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable interconnect junction
- Patent number 5,949,710
- Issue date Sep 7, 1999
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compact electrically erasable memory cells and arrays
- Patent number 5,914,904
- Issue date Jun 22, 1999
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing scheme for reducing stress and improving reliability in EEP...
- Patent number 5,905,675
- Issue date May 18, 1999
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile SRAM cells and cell arrays
- Patent number 5,812,450
- Issue date Sep 22, 1998
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile SRAM cells and cell arrays
- Patent number 5,581,501
- Issue date Dec 3, 1996
- Altera Corporation
- James D. Sansbury
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming programmable elements in programmable devices
- Patent number 5,200,920
- Issue date Apr 6, 1993
- Altera Corporation
- Kevin A. Norman
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Nonvolatile memory cell with low doping region
- Publication number 20030197218
- Publication date Oct 23, 2003
- Altera Corporation
- Christopher J. Pass
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable impedance device
- Publication number 20020034098
- Publication date Mar 21, 2002
- James D. Sansbury
- G11 - INFORMATION STORAGE

James D. Sansbury

Person

Patents Grantslast 30 patents

Nonvolatile memory cell with low doping region

Apparatus and method for margin testing single polysilicon EEPROM c...

Apparatus and method for margin testing single polysilicon EEPROM c...

Nonvolatile memory cell with low doping region

Nonvolatile configuration cells and cell arrays

Programmable impedance device

Nonvolatile memory cell with multiple gate oxide thicknesses

Nonvolatile configuration cells and cell arrays

Programmable impedance device

Nonvolatile configuration cells and cell arrays

Evaluation of memory cell characteristics

Apparatus and method for margin testing single polysilicon EEPROM c...

Compact electrically erasable memory cells and arrays

Nonvolatile memory cell with multiple gate oxide thicknesses

Techniques to configure nonvolatile cells and cell arrays

Programmable impedance device

Method of margin testing programmable interconnect cell

Nonvolatile configuration cells and cell arrays

Nonvolatile configuration cells and cell arrays

Evaluation of memory cell characteristics

Nonvolatile static memory circuit

Nonvolatile configuration cells and cell arrays

Nonvolatile configuration cells and cell arrays

Evaluation of memory cell characteristics

Programmable interconnect junction

Compact electrically erasable memory cells and arrays

Biasing scheme for reducing stress and improving reliability in EEP...

Nonvolatile SRAM cells and cell arrays

Nonvolatile SRAM cells and cell arrays

Method for programming programmable elements in programmable devices

Patents Applicationslast 30 patents

Nonvolatile memory cell with low doping region

Programmable impedance device