Jayashree Saxena

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Determining test conditions for at-speed transition delay fault tes...
- Patent number 10,107,859
- Issue date Oct 23, 2018
- Anora LLC
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Automatable scan partitioning for low power using external control
- Patent number 9,103,882
- Issue date Aug 11, 2015
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Decoder providing separate clock and enable for scan path segments
- Patent number 8,769,358
- Issue date Jul 1, 2014
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Decode logic driving segmented scan cells with clocks and enables
- Patent number 8,539,294
- Issue date Sep 17, 2013
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Divided scan path segments maintaining test pattern of stimulus/res...
- Patent number 8,321,729
- Issue date Nov 27, 2012
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Automatable scan partitioning for low power using external control
- Patent number 7,954,030
- Issue date May 31, 2011
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
Automatable scan partitioning for low power using external control
- Patent number 7,870,451
- Issue date Jan 11, 2011
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
System and method for estimating test escapes in integrated circuits
- Patent number 7,865,849
- Issue date Jan 4, 2011
- Texas Instruments Incorporated
- Kenneth M. Butler
- G01 - MEASURING TESTING
Information Patent Grant
Automatable scan partitioning for low power using external control
- Patent number 7,617,429
- Issue date Nov 10, 2009
- Texas Instruments Incorporated
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test protocol manager for massive multi-site test
- Patent number 7,580,807
- Issue date Aug 25, 2009
- Texas Instruments Incorporated
- Matthew Craig Bullock
- G01 - MEASURING TESTING
Information Patent Grant
Timing closure for system on a chip using voltage drop based standa...
- Patent number 7,324,914
- Issue date Jan 29, 2008
- Texas Instruments Incorporated
- Atul K. Jain
- G01 - MEASURING TESTING
Information Patent Grant
Decode logic selecting IC scan path parts
- Patent number 7,219,284
- Issue date May 15, 2007
- Texas Instruments Incorporated
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Divided scan path with decode logic receiving select control signals
- Patent number 6,766,487
- Issue date Jul 20, 2004
- Texas Instruments Incorporated
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Grant
System and method for pruning a bridging diagnostic list
- Patent number 6,618,830
- Issue date Sep 9, 2003
- Texas Instruments Incorporated
- Hari Balachandran
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20140250342
- Publication date Sep 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20130339773
- Publication date Dec 19, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20130047048
- Publication date Feb 21, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20110197102
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20110078524
- Publication date Mar 31, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20100023823
- Publication date Jan 28, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS
- Publication number 20090210830
- Publication date Aug 20, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Kenneth M. Butler
- G01 - MEASURING TESTING
Information Patent Application
Test Protocol Manager for Massive Multi-Site Test
- Publication number 20080015798
- Publication date Jan 17, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Matthew Craig Bullock
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL
- Publication number 20070162805
- Publication date Jul 12, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing closure for system on a chip using voltage drop based standa...
- Publication number 20060106564
- Publication date May 18, 2006
- Atul K. Jain
- G01 - MEASURING TESTING
Information Patent Application
Power reduction in module-based scan testing
- Publication number 20060107144
- Publication date May 18, 2006
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Application
Automatable scan partitioning for low power using external control
- Publication number 20040260990
- Publication date Dec 23, 2004
- Jayashree Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for efficient burn-in of electronic circuits
- Publication number 20030149913
- Publication date Aug 7, 2003
- Hari Balachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power reduction in module-based scan testing
- Publication number 20020170010
- Publication date Nov 14, 2002
- Jayashree Saxena
- G01 - MEASURING TESTING
Information Patent Application
Automatable scan partitioning for low power using external control
- Publication number 20020104050
- Publication date Aug 1, 2002
- Jayashree Saxena
- G01 - MEASURING TESTING

Jayashree Saxena

Person

Patents Grantslast 30 patents

Determining test conditions for at-speed transition delay fault tes...

Automatable scan partitioning for low power using external control

Decoder providing separate clock and enable for scan path segments

Decode logic driving segmented scan cells with clocks and enables

Divided scan path segments maintaining test pattern of stimulus/res...

Automatable scan partitioning for low power using external control

Automatable scan partitioning for low power using external control

System and method for estimating test escapes in integrated circuits

Automatable scan partitioning for low power using external control

Test protocol manager for massive multi-site test

Timing closure for system on a chip using voltage drop based standa...

Decode logic selecting IC scan path parts

Divided scan path with decode logic receiving select control signals

System and method for pruning a bridging diagnostic list

Patents Applicationslast 30 patents

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

SYSTEM AND METHOD FOR ESTIMATING TEST ESCAPES IN INTEGRATED CIRCUITS

Test Protocol Manager for Massive Multi-Site Test

AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL

Timing closure for system on a chip using voltage drop based standa...

Power reduction in module-based scan testing

Automatable scan partitioning for low power using external control

Method and apparatus for efficient burn-in of electronic circuits

Power reduction in module-based scan testing

Automatable scan partitioning for low power using external control