John W. Golz

Person

Garrison, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,870,979
- Issue date Jan 16, 2018
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-sided segmented line architecture in 3D integration
- Patent number 9,559,040
- Issue date Jan 31, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combination of TSV and back side wiring in 3D integration
- Patent number 9,543,229
- Issue date Jan 10, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combination of TSV and back side wiring in 3D integration
- Patent number 9,536,809
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power manager for standby operation of memory system
- Patent number 7,046,572
- Issue date May 16, 2006
- International Business Machines Corporation
- David R. Hansen
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power manager for standby operation of a memory system
- Patent number 7,023,758
- Issue date Apr 4, 2006
- International Business Machines Corporation
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory with smart refresh scheduler
- Patent number 6,954,387
- Issue date Oct 11, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and system-on-chip integration of a two-transistor and tw...
- Patent number 6,845,033
- Issue date Jan 18, 2005
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Bi-directional read write data structure and method for memory
- Patent number 6,816,397
- Issue date Nov 9, 2004
- International Business Machines Corporation
- John W. Golz
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method of making three finger folded field effect tra...
- Patent number 6,768,143
- Issue date Jul 27, 2004
- International Business Machines Corporation
- Gregory J. Fredeman
- G11 - INFORMATION STORAGE
Information Patent Grant
Gain cell structure with deep trench capacitor
- Patent number 6,747,890
- Issue date Jun 8, 2004
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming active devices of different gatelengths using lit...
- Patent number 6,703,312
- Issue date Mar 9, 2004
- International Business Machines Corporation
- John Walter Golz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with self-aligned channel edge implant and method
- Patent number 6,472,274
- Issue date Oct 29, 2002
- International Business Machines Corporation
- John Walter Golz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for resist planarization
- Patent number 6,440,638
- Issue date Aug 27, 2002
- International Business Machines Corp.
- John Golz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual mask process for semiconductor devices
- Patent number 6,429,067
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Joyce C. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for resist filling and planarization of high aspect ratio fe...
- Patent number 6,303,275
- Issue date Oct 16, 2001
- International Business Machines Corporation
- Robert A. Coles
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Self-aligned contact for closely spaced transistors
- Patent number 6,294,449
- Issue date Sep 25, 2001
- International Business Machines Corporation
- Teresa J. Wu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POWER DISTRIBUTION NETWORKS FOR SEMICONDUCTOR CHIP
- Publication number 20230326854
- Publication date Oct 12, 2023
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION
- Publication number 20150371927
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150364401
- Publication date Dec 17, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION
- Publication number 20150187642
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION
- Publication number 20150187733
- Publication date Jul 2, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM
- Publication number 20060039226
- Publication date Feb 23, 2006
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER
- Publication number 20050013185
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Hoki Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Low power manager for standby operation
- Publication number 20040252573
- Publication date Dec 16, 2004
- International Business Machine Corporation
- David R. Hanson
- G11 - INFORMATION STORAGE
Information Patent Application
BI-DIRECTIONAL READ WRITE DATA STRUCTURE AND METHOD FOR MEMORY
- Publication number 20040240246
- Publication date Dec 2, 2004
- John W. Golz
- G11 - INFORMATION STORAGE
Information Patent Application
Structure and System-on-Chip Integration of a Two-Transistor and Tw...
- Publication number 20040174733
- Publication date Sep 9, 2004
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Application
Method of forming active devices of different gatelengths using lit...
- Publication number 20030216050
- Publication date Nov 20, 2003
- International Business Machines Corporation
- John Walter Golz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL MASK PROCESS FOR SEMICONDUCTOR DEVICES
- Publication number 20020094637
- Publication date Jul 18, 2002
- International Business Machines Corporation
- Joyce C. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR RESIST PLANARIZATION
- Publication number 20010006761
- Publication date Jul 5, 2001
- JOHN GOLZ
- H01 - BASIC ELECTRIC ELEMENTS

John W. Golz

Person

Patents Grantslast 30 patents

Double-sided segmented line architecture in 3D integration

Double-sided segmented line architecture in 3D integration

Combination of TSV and back side wiring in 3D integration

Combination of TSV and back side wiring in 3D integration

Low power manager for standby operation of memory system

Low power manager for standby operation of a memory system

Dynamic random access memory with smart refresh scheduler

Structure and system-on-chip integration of a two-transistor and tw...

Bi-directional read write data structure and method for memory

Structure and method of making three finger folded field effect tra...

Gain cell structure with deep trench capacitor

Method of forming active devices of different gatelengths using lit...

MOSFET with self-aligned channel edge implant and method

Method and apparatus for resist planarization

Dual mask process for semiconductor devices

Method for resist filling and planarization of high aspect ratio fe...

Self-aligned contact for closely spaced transistors

Patents Applicationslast 30 patents

POWER DISTRIBUTION NETWORKS FOR SEMICONDUCTOR CHIP

COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

DOUBLE-SIDED SEGMENTED LINE ARCHITECTURE IN 3D INTEGRATION

COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION

LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM

DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER

Low power manager for standby operation

BI-DIRECTIONAL READ WRITE DATA STRUCTURE AND METHOD FOR MEMORY

Structure and System-on-Chip Integration of a Two-Transistor and Tw...

Method of forming active devices of different gatelengths using lit...

DUAL MASK PROCESS FOR SEMICONDUCTOR DEVICES

METHOD AND APPARATUS FOR RESIST PLANARIZATION