Patent Application
20230326854
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to a power and signal distribution network for semiconductor chips.
A semiconductor chip contains millions or even billions of transistors that are interconnected and electrically powered to achieve certain device functionality. Current chip technology generally employs wiring made at the frontside of the chip for both power and signal distribution. As a result, the power wiring and signal wiring compete for a same limited wiring area. The ability to rout wire efficiently is quickly becoming a serious challenge for the development of next node technology where the limited wiring area is becoming even scarcer.
As a new technology platform, there is a developing trend of moving the entire power delivery or distribution network to the backside of the chip, leaving the limited real estate of frontside of the chip for signal routing only. This increases not only power delivery efficiency at the backside but also signal routing resources at the frontside.
However, many currently existing and matured circuit blocks, which for example may form various circuit regions in a chip layout, are not suited for or designed to be compatible with backside power delivery because they are mostly, and traditionally, designed for frontside power delivery. A complete revamp or re-design of these circuit blocks to suit for backside power delivery may significantly reduce the efficiency of the semiconductor chip design.
Embodiments of present invention provide semiconductor chip. The semiconductor chip includes a device layer having a first and a second circuit region; a frontside distribution network (FSDN) above the device layer and powering the first circuit region; and a backside distribution network (BSDN) below the device layer and powering the second circuit region, wherein the BSDN is electrically connected to the FSDN through the device layer and the FSDN is electrically connected to the first circuit region through one or more frontside metal layers, and wherein the BSDN is electrically connected to transistors of the second circuit region through the device layer.
In one embodiment, the BSDN is electrically connected to a bottom of the second circuit region through one or more through-device-layer-vias (TDLVs), and in one aspect the one or more TDLVs are connected directly to the transistors of the second circuit region.
In another embodiment, the FSDN is connected to the BSDN through one or more connections, the one or more connections being a single power via, a power via stacked on top of a TDLV, or a stack of wires and vias stacked on top of a TDLV.
In one embodiment, the FSDN includes a ring above the first circuit region, the FSDN receives power from the BSDN through an electrical connection made at the ring.
In another embodiment, the FSDN includes a grid above the first circuit region, the FSDN receives power from the BSDN through two or more electrical connections made to the grid.
In one embodiment, the FSDN provides a voltage V2 to the first circuit region, voltage V2 being different from a voltage V1 of the BSDN and being derived from V1 through a voltage regulator in the device layer.
In another embodiment, a voltage V3 derived from a voltage V1 of the BSDN through a voltage regulator in the device layer is provided back to the BSDN and used to power the second circuit region through a TDLV.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures may not be repeated for each of the drawings.
The backside layer 100 may include a backside distribution network (BSDN) 120 and may include one or more connections to some external sources such as external bump pads 111 and 113 (see
The device layer 200 may include one or more circuit regions such as, for example, a first circuit region 210 and a second circuit region 220. A circuit region, for example the first circuit region 210, may include one or more transistors such as logic transistors. In one embodiment, a circuit region may be a set of transistors with wiring schemes fabricated according to a pre-existing layout, design, or otherwise a widely used or commercially available design for a functional circuitry, and the circuit region generally requires a frontside powering and/or signaling scheme such as using a frontside distribution network (FSDN) 310. In another embodiment, a circuit region may be a circuit that requires frontside powering and/or signaling scheme such as using the FSDN 310 and may be powered up or receive electrical signals from a backside as well using a backside powering and/or signaling scheme such as using the BSDN 120. In yet another embodiment, a circuit region such as the second circuit region 220, may be powered up and/or receive electric signals only from a backside powering and/or signaling scheme through one or more through-device-layer-vias (TDLVs) such as TDLV 201, TDLV 202 and TDLV 203, and in doing so by using the BSDN 120. For example, the second circuit region 220 may be a transistor or a set of transistors and the transistor or set of transistors may be directly connected to the TDLV 201, TDLV 202, and/or TDLV 203 to receive power and/or other electrical signals from the BSDN 120.
The frontside layer 300 may include the FSDN 310. The FSDN 310 may provide power and/or voltage to one or more circuit regions such as the first circuit region 210 through one or more metal layers such as one or more metal layers 320. The BSDN 120 may be electrically connected to the FSDN 310 through one or more connections such as, for example, a connection 410, as being described below in more details.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Although exemplary embodiments have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.
It is to be understood that the various layers, structures, and/or regions described above are not necessarily drawn to scale. In addition, for ease of explanation one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.
Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Terms such as “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount.
In some embodiments, the above-described techniques are used in connection with manufacture of semiconductor integrated circuit devices that illustratively include, by way of non-limiting example, CMOS devices, MOSFET devices, and/or FinFET devices, and/or other types of semiconductor integrated circuit devices that incorporate or otherwise utilize CMOS, MOSFET, and/or FinFET technology.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
