Patent Application
20250022800
The present application relates to semiconductor technology, and more particularly to a three-dimensional (3D) chip (or wafer) stack including a customized redistribution layer that is present between each stacked semiconductor wafer.
The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there is a need for advanced packaging techniques of semiconductor dies to increase interconnection density and performance.
As semiconductor technologies further advance, stacked semiconductor devices, e.g., 3D integrated circuits (ICs), have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits and the like can be fabricated on different semiconductor wafers. Two or more semiconductor wafers can be stacked on top of one another to reduce the form factor of the semiconductor device. Two semiconductor wafers can be bonded together through suitable bonding techniques. An electrical connection can be provided between the stacked semiconductor wafers. The stacked semiconductor devices can provide a higher density with smaller form factors and allow for increased performance and lower power consumption.
A 3D chip (or wafer) stack is provided in which a customized redistribution layer is located between each semiconductor wafer of the 3D chip (or wafer) stack. The chip (or wafer) includes one or more “die sites”, a term used throughout the present application to denote an area of the semiconductor wafer in which a set of circuits are present. A wafer map typically identifies die site location by row and column designator. The set of circuits within the die site can be fully functional and thus the die site can be referred to as a functional die site. The set of circuits within the die site can be fully non-functional and thus the die site can be referred as a non-functional die site. The set of circuits within the die site may include both functional and non-functional circuits and thus may be referred to as partially a functional die site. The customized redistribution layer connects functional circuits within die sites on a first semiconductor wafer to functional circuits within die sites on a second semiconductor wafer, while by-passing non-functional circuits within die sites on the second semiconductor wafer.
In one aspect of the present application, a 3D stack is provided. In the present application, the term ‘3D stack’ is meant to include a chip stack (after wafer stacking and dicing or after dicing and stacking) or a wafer stack (after stacking and no dicing). In one embodiment of the present application, the 3D stack includes a first semiconductor wafer including a plurality of first die sites, wherein the plurality of first die sites includes at least first functional die sites. The 3D stack further includes a second semiconductor wafer stacked above the first semiconductor wafer. The second semiconductor wafer includes a plurality of second die sites, wherein the plurality of second die sites includes second functional die sites, second partially functional die sites (in some embodiments these partially functional die sites can be optional) and second non-functional die sites. The 3D stack even further includes a redistribution layer located between the first semiconductor wafer and the second semiconductor wafer. The redistribution layer electrically connects the first functional die sites of the first semiconductor wafer to the second functional die sites, and, if present, the second partially functional die sites of the second semiconductor wafer and by-passes the second non-functional die sites of the second semiconductor wafer. In the present application, a plurality of semiconductor wafers can be stacked one on top the other, with a customized redistribution layer located between each semiconductor wafer.
In another aspect of the present application, a method of 3D stacking is provided. In one embodiment, the method includes processing a first semiconductor wafer including a plurality of first die sites and a second semiconductor wafer including a plurality of second die sites; individually testing the first die sites of the first semiconductor wafer and the second die sites of the second semiconductor wafer to determine the functionality or non-functionality of each first die site and each second die site; preparing a first semiconductor wafer map of the functionality or non-functionality of each first die site and a second semiconductor wafer map of the functionally or non-functionality of each second die site; forming, by utilizing the first semiconductor wafer map and the second semiconductor wafer map, a redistribution layer on the first semiconductor wafer to include electrically conductive wiring that electrically connects the partially and fully functional die sites of the first semiconductor wafer to the partially and fully functional die sites of the second semiconductor wafer, while by-passing non-functional die sites of the second semiconductor wafer; and attaching the first semiconductor wafer to the second semiconductor wafer. The method can be employed using a plurality of semiconductor wafers.
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
In stacking semiconductor wafers including functional die sites and non-functional die sites, wafer assignment algorithms have been used to maximize the functional yield of the wafer-to-wafer 3D integration. Wafer assignment algorithms have limited benefit.
Another technique used in semiconductor wafers including functional die sites and non-functional die sites is to include redundant circuits in at least some of the wafers. Redundant circuits have substantial overhead and design complexity.
Neither of the above techniques enable the ability to disconnect power to a die or die circuit blocks while further enabling passthrough where needed.
The present application provides a solution to the above problems by providing a customized redistribution layer between each semiconductor wafer of a stack of semiconductor wafers. The customized redistribution layer connects fully or partial functional die sites on a first semiconductor wafer to fully or partial functional die sites on a second semiconductor wafer, while by-passing non-functional die sites on the second semiconductor wafer. The customized redistribution layer has different patterns associated with connection and by-passing.
Notably, and in one embodiment, a 3D stack, e.g., a die stack, is provided that includes a first semiconductor wafer including a plurality of first die sites, wherein the plurality of first die sites includes at least first functional die sites. The 3D stack further includes a second semiconductor wafer stacked above the first semiconductor wafer. The second semiconductor wafer includes a plurality of second die sites, wherein the plurality of second die sites includes second functional die sites and second non-functional die sites; second partially functional die sites can also be present. The 3D stack even further includes a redistribution layer located between the first semiconductor wafer and the second semiconductor wafer. The redistribution layer electrically connects the first functional die sites of the first semiconductor wafer to the second functional die sites and, if present, the second partially functional dies sites of the second semiconductor wafer and by-passes the second non-functional die sites of the second semiconductor wafer. In the present application, a plurality of semiconductor wafers can be stacked one on top the other, with a customized redistribution layer located between each semiconductor wafer. These and other aspects of the present application will now be described in greater detail.
Reference is first made to
The term “semiconductor wafer” is used through-out the present application to denote a substrate that is composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that can be used in the present application include, but are not limited to, silicon (Si), a silicon germanium (SiGe) alloy, a silicon germanium carbide (SiGeC) alloy, germanium (Ge), III/V compound semiconductors or II/VI compound semiconductors. In some embodiments, the semiconductor wafer is a bulk semiconductor substrate that is entirely composed of one or more semiconductor materials. In other embodiments, the semiconductor wafer is a semiconductor-on-insulator substrate that includes a dielectric material such as silicon dioxide, diamond-like carbon (DLC), boron nitride or combinations thereof positioned between a first semiconductor layer and a second semiconductor layer.
Each semiconductor wafer includes a frontside and a backside. The frontside of the semiconductor wafer is a side of the semiconductor wafer that includes a front-end-of-the-line (FEOL) level, a middle-of-the-line (MOL) level and a back-end-of-the-line (BEOL) level. The FEOL level is a level in which individual components (e.g., transistors, capacitors, and/or resistors) are fabricated. On the frontside of each semiconductor wafer, the individual components can be connected by metal wires/traces (present in the MOL and BEOL levels) to form an electronic circuit (hereinafter referred to as just “circuit”). The backside of the semiconductor wafer is a side of the wafer opposite the frontside that contains the FEOL level. The backside of the semiconductor wafer contains various backside structures including, but not limited, to backside wiring structures. Through vias may be fabricated within the semiconductor wafer which provide electrical connections from the FEOL level. MOL level and BEOL level to the backside of the wafer.
In the present application, each semiconductor wafer including the four depicted in the drawings of the present application are processed to include a FEOL level, a MOL level and a BEOL level, and backside structures. Three of the semiconductor wafers exemplified in the present application include through vias which connect the frontside structures to the backside of the wafer. The topmost wafer does not have through vias. For clarity. the FEOL level, the MOL level and the BEOL level, and backside structures are not shown. The processing of the frontside and the backside includes techniques that are well known to a skilled artisan. As such, and so not to obscure any aspects of the present application the techniques used in processing the frontside and the backside are not described herein.
In the present application. cach semiconductor wafer including the four depicted in the drawings of the present application includes a plurality of die sites which in the top-down views are present in rows and columns. As mentioned above, the term “die site” is used throughout the present application to denote an area of the semiconductor wafer in which a set of circuits are present. The set of circuits within each die site can be fully functional circuits and thus the die site can be referred to as a functional die site. The set of circuits within the die site can be fully non-functional circuits and thus the die site can be referred as a non-functional die site. The set of circuit within the die site may include both functional and non-functional circuits and thus may be referred to as a partially functional die site. In the present application, a semiconductor wafer can include fully functional die sites, or a combination of fully functional die sites, partially functional die sites and fully non-functional die sites. The number of functional die sites, partially functional die sites and non-functional die sites on any given semiconductor wafer can vary and is not limited to the illustrated embodiments depicted in
In the present application, and after processing each of the semiconductor wafers, the die sites of the wafer are tested prior to stacking to determine whether the die sites are functional die sites, partially functional die sites or non-functional die sites. Testing can include any standard die site testing process such as, for example, adaptive test, advance DFT (design for test) which can include scan and built-in self-test (BIST), fast mixed signal testers, and fine pitch probe cards. Additionally, other methods can be used to assist in determining die-site functionality, such as wafer level burn-in to eliminate infant mortality. A map of the wafer (hereinafter wafer map) can then be generated using known processes to determine which die sites are functional, partially functional and which are non-functional. The wafer map of each of the semiconductor wafers can be stored in a storage device such as, for example, on a computer hard drive, and be subsequently used in the customization of a redistribution layer. Notably, and in the present application, the wafer maps of the first and the second semiconductor wafers can be used to design a redistribution layer. In the present application, a redistribution layer is designed that connects functional die sites on the first semiconductor wafer with functional die sites (and if present, partially functional die sites) on the second semiconductor wafer, while by-passing any non-functional die site on the second semiconductor wafer. A customized redistribution layer can be designed for each of the semiconductor wafers that are to be stacked one on top of the other using the process mentioned above. In some embodiments, the customized redistribution layer can be formed on the backside of a processed semiconductor wafer, while an array of interconnects can be formed on the frontside of a processed semiconductor wafer. In some embodiments, the customized redistribution layer can be formed on the backside of a lower processed semiconductor wafer, and another customized redistribution layer can be formed on the frontside of an upper processed semiconductor wafer.
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In the present application, the term “redistribution layer” denotes an interconnect structure that contains electrically conductive wires embedded in an interconnect dielectric layer. The electrically conductive wires can be composed of an electrically conductive metal or an electrically conductive metal alloy. Exemplary electrically conductive materials (i.e., metal or metal alloys) that can provide electrically conductive wires of the redistribution layer include, but are not limited, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), rhodium (Rh), platinum (Pt) and alloys of Cu—Al. The interconnect dielectric layer includes one or more interconnect dielectric materials. Illustrative interconnect dielectric materials that can be used as the interconnect dielectric layer of the redistribution layer include, but are not limited to, silicon dioxide, undoped or doped silicate glass, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, theremosetting polyarylene ethers, polyimides, polybenzoxazole (PBO) or any multilayered combination thereof. The term “polyarylene” is used in this present application to denote aryl moieties or inertly substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, or carbonyl.
In embodiments, a diffusion barrier liner can be present on at least the sidewalls of each of the electrically conductive wires present in the redistribution layer. In some embodiments, no diffusion barrier liner is employed. When present, the diffusion barrier liner is composed of a diffusion barrier material such as, for example, Ta. TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W. WN or any other material that can serve as a barrier to prevent a conductive material from diffusing there through.
The redistribution layer can be formed utilizing processes well known to one skilled in the art. The redistribution layer can be formed by additive processes, such a copper plating through a photoresist mask and subsequent planarization within a dielectric, or a subtractive process, as described herein, a semi-additive process or any combination thereof. In one example, the redistribution layer can be formed utilizing a damascene process. In a damascene process, the interconnect dielectric layer is formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin-on coating. Openings are then formed into the as deposited interconnect dielectric layer by lithography and etching. If present, a layer of a diffusion barrier material can then be formed followed by a layer of an electrically conductive material. A planarization process is then performed to remove the optional layer of diffusion barrier material and the layer of electrically conductive material from outside the openings forming the optional diffusion barrier liner and the electrically conductive wire in each of the openings. The electrically conductive wiring of the redistribution layer can be connected to signal interconnects (i.e., lines) power interconnects (i.e., lines), and ground interconnects (i.c., lines) that can be present in a typical die site on a semiconductor wafer, including the various die sites on the semiconductor wafers shown in
Referring now to
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In embodiments of the present application, the redistribution layer is in direct contact with a backside of a lower semiconductor wafer of a stacked wafer pair and is electrically connected to a frontside of an upper semiconductor wafer of the stacked wafer pair via one or more interconnects, i.e., the signal interconnects 20, power interconnects 22, and ground interconnects 24 mentioned above.
Referring now to
Notably,
The signal lines 32, power lines 34 and ground lines 36 are composed of one of the electrically conductive materials mentioned above for the electrically conductive wiring that is present in each of the first, second and third redistribution layers 30A, 30B and 30C; in the present application, a portion of each of the signal lines 32, power lines 34 and ground lines 36 within the first, second and third redistribution layers 30A, 30B and 30C represents that electrically conductive wiring, while a remaining portion of the signal lines 32, power lines 34 and ground lines 36 present in each of the first, second, and third semiconductor wafers 100, 102 and 104 represents through via wiring that is present in each of the wafers; the wiring is fabricated within each wafer prior to wafer stacking. The through via wiring electrically connects the backside of the semiconductor wafer to the frontside of the semiconductor wafer.
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The 3D stacking can be performed by first forming in any order, an array of interconnects, as defined above, on the frontside of each semiconductor wafer that is to be stacked and a redistribution layer (as defined above) on the backside of a lower semiconductor wafer of a semiconductor wafer bonding pair. In some embodiments another customized redistribution layer can be formed on the frontside of a semiconductor wafer to be stacked. The array of interconnects of a top semiconductor wafer of the semiconductor wafer bonding pair is then brought in intimate contact with the redistribution layer that is formed on the bottom semiconductor wafer of the semiconductor wafer bonding pair. Heat can then be applied to ensure bonding of the two semiconductor wafers. Embodiments include other means of attaching the wafer together. Dicing can occur after chip stacking as is known to those skilled in the art.
While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
